1
2
3
4#include <linux/etherdevice.h>
5#include <linux/iopoll.h>
6#include <net/rtnetlink.h>
7#include "hclgevf_cmd.h"
8#include "hclgevf_main.h"
9#include "hclge_mbx.h"
10#include "hnae3.h"
11
12#define HCLGEVF_NAME "hclgevf"
13
14#define HCLGEVF_RESET_MAX_FAIL_CNT 5
15
16static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
17static struct hnae3_ae_algo ae_algovf;
18
19static struct workqueue_struct *hclgevf_wq;
20
21static const struct pci_device_id ae_algovf_pci_tbl[] = {
22 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
23 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
24 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
25
26 {0, }
27};
28
29static const u8 hclgevf_hash_key[] = {
30 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
31 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
32 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
33 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
34 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
35};
36
37MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
38
39static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
40 HCLGEVF_CMDQ_TX_ADDR_H_REG,
41 HCLGEVF_CMDQ_TX_DEPTH_REG,
42 HCLGEVF_CMDQ_TX_TAIL_REG,
43 HCLGEVF_CMDQ_TX_HEAD_REG,
44 HCLGEVF_CMDQ_RX_ADDR_L_REG,
45 HCLGEVF_CMDQ_RX_ADDR_H_REG,
46 HCLGEVF_CMDQ_RX_DEPTH_REG,
47 HCLGEVF_CMDQ_RX_TAIL_REG,
48 HCLGEVF_CMDQ_RX_HEAD_REG,
49 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
50 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
51 HCLGEVF_CMDQ_INTR_EN_REG,
52 HCLGEVF_CMDQ_INTR_GEN_REG};
53
54static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
55 HCLGEVF_RST_ING,
56 HCLGEVF_GRO_EN_REG};
57
58static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
59 HCLGEVF_RING_RX_ADDR_H_REG,
60 HCLGEVF_RING_RX_BD_NUM_REG,
61 HCLGEVF_RING_RX_BD_LENGTH_REG,
62 HCLGEVF_RING_RX_MERGE_EN_REG,
63 HCLGEVF_RING_RX_TAIL_REG,
64 HCLGEVF_RING_RX_HEAD_REG,
65 HCLGEVF_RING_RX_FBD_NUM_REG,
66 HCLGEVF_RING_RX_OFFSET_REG,
67 HCLGEVF_RING_RX_FBD_OFFSET_REG,
68 HCLGEVF_RING_RX_STASH_REG,
69 HCLGEVF_RING_RX_BD_ERR_REG,
70 HCLGEVF_RING_TX_ADDR_L_REG,
71 HCLGEVF_RING_TX_ADDR_H_REG,
72 HCLGEVF_RING_TX_BD_NUM_REG,
73 HCLGEVF_RING_TX_PRIORITY_REG,
74 HCLGEVF_RING_TX_TC_REG,
75 HCLGEVF_RING_TX_MERGE_EN_REG,
76 HCLGEVF_RING_TX_TAIL_REG,
77 HCLGEVF_RING_TX_HEAD_REG,
78 HCLGEVF_RING_TX_FBD_NUM_REG,
79 HCLGEVF_RING_TX_OFFSET_REG,
80 HCLGEVF_RING_TX_EBD_NUM_REG,
81 HCLGEVF_RING_TX_EBD_OFFSET_REG,
82 HCLGEVF_RING_TX_BD_ERR_REG,
83 HCLGEVF_RING_EN_REG};
84
85static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
86 HCLGEVF_TQP_INTR_GL0_REG,
87 HCLGEVF_TQP_INTR_GL1_REG,
88 HCLGEVF_TQP_INTR_GL2_REG,
89 HCLGEVF_TQP_INTR_RL_REG};
90
91static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
92{
93 if (!handle->client)
94 return container_of(handle, struct hclgevf_dev, nic);
95 else if (handle->client->type == HNAE3_CLIENT_ROCE)
96 return container_of(handle, struct hclgevf_dev, roce);
97 else
98 return container_of(handle, struct hclgevf_dev, nic);
99}
100
101static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
102{
103 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
104 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
105 struct hclgevf_desc desc;
106 struct hclgevf_tqp *tqp;
107 int status;
108 int i;
109
110 for (i = 0; i < kinfo->num_tqps; i++) {
111 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
112 hclgevf_cmd_setup_basic_desc(&desc,
113 HCLGEVF_OPC_QUERY_RX_STATUS,
114 true);
115
116 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
117 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
118 if (status) {
119 dev_err(&hdev->pdev->dev,
120 "Query tqp stat fail, status = %d,queue = %d\n",
121 status, i);
122 return status;
123 }
124 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
125 le32_to_cpu(desc.data[1]);
126
127 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
128 true);
129
130 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
131 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
132 if (status) {
133 dev_err(&hdev->pdev->dev,
134 "Query tqp stat fail, status = %d,queue = %d\n",
135 status, i);
136 return status;
137 }
138 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
139 le32_to_cpu(desc.data[1]);
140 }
141
142 return 0;
143}
144
145static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
146{
147 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
148 struct hclgevf_tqp *tqp;
149 u64 *buff = data;
150 int i;
151
152 for (i = 0; i < kinfo->num_tqps; i++) {
153 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
154 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
155 }
156 for (i = 0; i < kinfo->num_tqps; i++) {
157 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
158 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
159 }
160
161 return buff;
162}
163
164static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
165{
166 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
167
168 return kinfo->num_tqps * 2;
169}
170
171static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
172{
173 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
174 u8 *buff = data;
175 int i;
176
177 for (i = 0; i < kinfo->num_tqps; i++) {
178 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
179 struct hclgevf_tqp, q);
180 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
181 tqp->index);
182 buff += ETH_GSTRING_LEN;
183 }
184
185 for (i = 0; i < kinfo->num_tqps; i++) {
186 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
187 struct hclgevf_tqp, q);
188 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
189 tqp->index);
190 buff += ETH_GSTRING_LEN;
191 }
192
193 return buff;
194}
195
196static void hclgevf_update_stats(struct hnae3_handle *handle,
197 struct net_device_stats *net_stats)
198{
199 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
200 int status;
201
202 status = hclgevf_tqps_update_stats(handle);
203 if (status)
204 dev_err(&hdev->pdev->dev,
205 "VF update of TQPS stats fail, status = %d.\n",
206 status);
207}
208
209static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
210{
211 if (strset == ETH_SS_TEST)
212 return -EOPNOTSUPP;
213 else if (strset == ETH_SS_STATS)
214 return hclgevf_tqps_get_sset_count(handle, strset);
215
216 return 0;
217}
218
219static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
220 u8 *data)
221{
222 u8 *p = (char *)data;
223
224 if (strset == ETH_SS_STATS)
225 p = hclgevf_tqps_get_strings(handle, p);
226}
227
228static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
229{
230 hclgevf_tqps_get_stats(handle, data);
231}
232
233static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
234 u8 subcode)
235{
236 if (msg) {
237 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
238 msg->code = code;
239 msg->subcode = subcode;
240 }
241}
242
243static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
244{
245 struct hclge_vf_to_pf_msg send_msg;
246 u8 resp_msg;
247 int status;
248
249 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0);
250 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
251 sizeof(resp_msg));
252 if (status) {
253 dev_err(&hdev->pdev->dev,
254 "VF request to get TC info from PF failed %d",
255 status);
256 return status;
257 }
258
259 hdev->hw_tc_map = resp_msg;
260
261 return 0;
262}
263
264static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
265{
266 struct hnae3_handle *nic = &hdev->nic;
267 struct hclge_vf_to_pf_msg send_msg;
268 u8 resp_msg;
269 int ret;
270
271 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
272 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
273 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
274 sizeof(u8));
275 if (ret) {
276 dev_err(&hdev->pdev->dev,
277 "VF request to get port based vlan state failed %d",
278 ret);
279 return ret;
280 }
281
282 nic->port_base_vlan_state = resp_msg;
283
284 return 0;
285}
286
287static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
288{
289#define HCLGEVF_TQPS_RSS_INFO_LEN 6
290#define HCLGEVF_TQPS_ALLOC_OFFSET 0
291#define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2
292#define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4
293
294 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
295 struct hclge_vf_to_pf_msg send_msg;
296 int status;
297
298 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
299 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
300 HCLGEVF_TQPS_RSS_INFO_LEN);
301 if (status) {
302 dev_err(&hdev->pdev->dev,
303 "VF request to get tqp info from PF failed %d",
304 status);
305 return status;
306 }
307
308 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET],
309 sizeof(u16));
310 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET],
311 sizeof(u16));
312 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET],
313 sizeof(u16));
314
315 return 0;
316}
317
318static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
319{
320#define HCLGEVF_TQPS_DEPTH_INFO_LEN 4
321#define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0
322#define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2
323
324 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
325 struct hclge_vf_to_pf_msg send_msg;
326 int ret;
327
328 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
329 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
330 HCLGEVF_TQPS_DEPTH_INFO_LEN);
331 if (ret) {
332 dev_err(&hdev->pdev->dev,
333 "VF request to get tqp depth info from PF failed %d",
334 ret);
335 return ret;
336 }
337
338 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET],
339 sizeof(u16));
340 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET],
341 sizeof(u16));
342
343 return 0;
344}
345
346static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
347{
348 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
349 struct hclge_vf_to_pf_msg send_msg;
350 u16 qid_in_pf = 0;
351 u8 resp_data[2];
352 int ret;
353
354 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
355 memcpy(send_msg.data, &queue_id, sizeof(queue_id));
356 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
357 sizeof(resp_data));
358 if (!ret)
359 qid_in_pf = *(u16 *)resp_data;
360
361 return qid_in_pf;
362}
363
364static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
365{
366 struct hclge_vf_to_pf_msg send_msg;
367 u8 resp_msg[2];
368 int ret;
369
370 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
371 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
372 sizeof(resp_msg));
373 if (ret) {
374 dev_err(&hdev->pdev->dev,
375 "VF request to get the pf port media type failed %d",
376 ret);
377 return ret;
378 }
379
380 hdev->hw.mac.media_type = resp_msg[0];
381 hdev->hw.mac.module_type = resp_msg[1];
382
383 return 0;
384}
385
386static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
387{
388 struct hclgevf_tqp *tqp;
389 int i;
390
391 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
392 sizeof(struct hclgevf_tqp), GFP_KERNEL);
393 if (!hdev->htqp)
394 return -ENOMEM;
395
396 tqp = hdev->htqp;
397
398 for (i = 0; i < hdev->num_tqps; i++) {
399 tqp->dev = &hdev->pdev->dev;
400 tqp->index = i;
401
402 tqp->q.ae_algo = &ae_algovf;
403 tqp->q.buf_size = hdev->rx_buf_len;
404 tqp->q.tx_desc_num = hdev->num_tx_desc;
405 tqp->q.rx_desc_num = hdev->num_rx_desc;
406 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
407 i * HCLGEVF_TQP_REG_SIZE;
408
409 tqp++;
410 }
411
412 return 0;
413}
414
415static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
416{
417 struct hnae3_handle *nic = &hdev->nic;
418 struct hnae3_knic_private_info *kinfo;
419 u16 new_tqps = hdev->num_tqps;
420 unsigned int i;
421
422 kinfo = &nic->kinfo;
423 kinfo->num_tc = 0;
424 kinfo->num_tx_desc = hdev->num_tx_desc;
425 kinfo->num_rx_desc = hdev->num_rx_desc;
426 kinfo->rx_buf_len = hdev->rx_buf_len;
427 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
428 if (hdev->hw_tc_map & BIT(i))
429 kinfo->num_tc++;
430
431 kinfo->rss_size
432 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
433 new_tqps = kinfo->rss_size * kinfo->num_tc;
434 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
435
436 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
437 sizeof(struct hnae3_queue *), GFP_KERNEL);
438 if (!kinfo->tqp)
439 return -ENOMEM;
440
441 for (i = 0; i < kinfo->num_tqps; i++) {
442 hdev->htqp[i].q.handle = &hdev->nic;
443 hdev->htqp[i].q.tqp_index = i;
444 kinfo->tqp[i] = &hdev->htqp[i].q;
445 }
446
447
448
449
450 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
451 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc,
452 kinfo->rss_size);
453
454 return 0;
455}
456
457static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
458{
459 struct hclge_vf_to_pf_msg send_msg;
460 int status;
461
462 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
463 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
464 if (status)
465 dev_err(&hdev->pdev->dev,
466 "VF failed to fetch link status(%d) from PF", status);
467}
468
469void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
470{
471 struct hnae3_handle *rhandle = &hdev->roce;
472 struct hnae3_handle *handle = &hdev->nic;
473 struct hnae3_client *rclient;
474 struct hnae3_client *client;
475
476 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
477 return;
478
479 client = handle->client;
480 rclient = hdev->roce_client;
481
482 link_state =
483 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
484
485 if (link_state != hdev->hw.mac.link) {
486 client->ops->link_status_change(handle, !!link_state);
487 if (rclient && rclient->ops->link_status_change)
488 rclient->ops->link_status_change(rhandle, !!link_state);
489 hdev->hw.mac.link = link_state;
490 }
491
492 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
493}
494
495static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
496{
497#define HCLGEVF_ADVERTISING 0
498#define HCLGEVF_SUPPORTED 1
499
500 struct hclge_vf_to_pf_msg send_msg;
501
502 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
503 send_msg.data[0] = HCLGEVF_ADVERTISING;
504 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
505 send_msg.data[0] = HCLGEVF_SUPPORTED;
506 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
507}
508
509static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
510{
511 struct hnae3_handle *nic = &hdev->nic;
512 int ret;
513
514 nic->ae_algo = &ae_algovf;
515 nic->pdev = hdev->pdev;
516 nic->numa_node_mask = hdev->numa_node_mask;
517 nic->flags |= HNAE3_SUPPORT_VF;
518
519 ret = hclgevf_knic_setup(hdev);
520 if (ret)
521 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
522 ret);
523 return ret;
524}
525
526static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
527{
528 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
529 dev_warn(&hdev->pdev->dev,
530 "vector(vector_id %d) has been freed.\n", vector_id);
531 return;
532 }
533
534 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
535 hdev->num_msi_left += 1;
536 hdev->num_msi_used -= 1;
537}
538
539static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
540 struct hnae3_vector_info *vector_info)
541{
542 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
543 struct hnae3_vector_info *vector = vector_info;
544 int alloc = 0;
545 int i, j;
546
547 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
548 vector_num = min(hdev->num_msi_left, vector_num);
549
550 for (j = 0; j < vector_num; j++) {
551 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
552 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
553 vector->vector = pci_irq_vector(hdev->pdev, i);
554 vector->io_addr = hdev->hw.io_base +
555 HCLGEVF_VECTOR_REG_BASE +
556 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
557 hdev->vector_status[i] = 0;
558 hdev->vector_irq[i] = vector->vector;
559
560 vector++;
561 alloc++;
562
563 break;
564 }
565 }
566 }
567 hdev->num_msi_left -= alloc;
568 hdev->num_msi_used += alloc;
569
570 return alloc;
571}
572
573static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
574{
575 int i;
576
577 for (i = 0; i < hdev->num_msi; i++)
578 if (vector == hdev->vector_irq[i])
579 return i;
580
581 return -EINVAL;
582}
583
584static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
585 const u8 hfunc, const u8 *key)
586{
587 struct hclgevf_rss_config_cmd *req;
588 unsigned int key_offset = 0;
589 struct hclgevf_desc desc;
590 int key_counts;
591 int key_size;
592 int ret;
593
594 key_counts = HCLGEVF_RSS_KEY_SIZE;
595 req = (struct hclgevf_rss_config_cmd *)desc.data;
596
597 while (key_counts) {
598 hclgevf_cmd_setup_basic_desc(&desc,
599 HCLGEVF_OPC_RSS_GENERIC_CONFIG,
600 false);
601
602 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
603 req->hash_config |=
604 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
605
606 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts);
607 memcpy(req->hash_key,
608 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
609
610 key_counts -= key_size;
611 key_offset++;
612 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
613 if (ret) {
614 dev_err(&hdev->pdev->dev,
615 "Configure RSS config fail, status = %d\n",
616 ret);
617 return ret;
618 }
619 }
620
621 return 0;
622}
623
624static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
625{
626 return HCLGEVF_RSS_KEY_SIZE;
627}
628
629static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
630{
631 return HCLGEVF_RSS_IND_TBL_SIZE;
632}
633
634static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
635{
636 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
637 struct hclgevf_rss_indirection_table_cmd *req;
638 struct hclgevf_desc desc;
639 int status;
640 int i, j;
641
642 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
643
644 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
645 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
646 false);
647 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
648 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
649 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
650 req->rss_result[j] =
651 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
652
653 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
654 if (status) {
655 dev_err(&hdev->pdev->dev,
656 "VF failed(=%d) to set RSS indirection table\n",
657 status);
658 return status;
659 }
660 }
661
662 return 0;
663}
664
665static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size)
666{
667 struct hclgevf_rss_tc_mode_cmd *req;
668 u16 tc_offset[HCLGEVF_MAX_TC_NUM];
669 u16 tc_valid[HCLGEVF_MAX_TC_NUM];
670 u16 tc_size[HCLGEVF_MAX_TC_NUM];
671 struct hclgevf_desc desc;
672 u16 roundup_size;
673 unsigned int i;
674 int status;
675
676 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
677
678 roundup_size = roundup_pow_of_two(rss_size);
679 roundup_size = ilog2(roundup_size);
680
681 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
682 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
683 tc_size[i] = roundup_size;
684 tc_offset[i] = rss_size * i;
685 }
686
687 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
688 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
689 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
690 (tc_valid[i] & 0x1));
691 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
692 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
693 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
694 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
695 }
696 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
697 if (status)
698 dev_err(&hdev->pdev->dev,
699 "VF failed(=%d) to set rss tc mode\n", status);
700
701 return status;
702}
703
704
705static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
706{
707#define HCLGEVF_RSS_MBX_RESP_LEN 8
708 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
709 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
710 struct hclge_vf_to_pf_msg send_msg;
711 u16 msg_num, hash_key_index;
712 u8 index;
713 int ret;
714
715 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
716 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
717 HCLGEVF_RSS_MBX_RESP_LEN;
718 for (index = 0; index < msg_num; index++) {
719 send_msg.data[0] = index;
720 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
721 HCLGEVF_RSS_MBX_RESP_LEN);
722 if (ret) {
723 dev_err(&hdev->pdev->dev,
724 "VF get rss hash key from PF failed, ret=%d",
725 ret);
726 return ret;
727 }
728
729 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
730 if (index == msg_num - 1)
731 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
732 &resp_msg[0],
733 HCLGEVF_RSS_KEY_SIZE - hash_key_index);
734 else
735 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
736 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
737 }
738
739 return 0;
740}
741
742static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
743 u8 *hfunc)
744{
745 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
746 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
747 int i, ret;
748
749 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
750
751 if (hfunc) {
752 switch (rss_cfg->hash_algo) {
753 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
754 *hfunc = ETH_RSS_HASH_TOP;
755 break;
756 case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
757 *hfunc = ETH_RSS_HASH_XOR;
758 break;
759 default:
760 *hfunc = ETH_RSS_HASH_UNKNOWN;
761 break;
762 }
763 }
764
765
766 if (key)
767 memcpy(key, rss_cfg->rss_hash_key,
768 HCLGEVF_RSS_KEY_SIZE);
769 } else {
770 if (hfunc)
771 *hfunc = ETH_RSS_HASH_TOP;
772 if (key) {
773 ret = hclgevf_get_rss_hash_key(hdev);
774 if (ret)
775 return ret;
776 memcpy(key, rss_cfg->rss_hash_key,
777 HCLGEVF_RSS_KEY_SIZE);
778 }
779 }
780
781 if (indir)
782 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
783 indir[i] = rss_cfg->rss_indirection_tbl[i];
784
785 return 0;
786}
787
788static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
789 const u8 *key, const u8 hfunc)
790{
791 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
792 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
793 int ret, i;
794
795 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
796
797 if (key) {
798 switch (hfunc) {
799 case ETH_RSS_HASH_TOP:
800 rss_cfg->hash_algo =
801 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
802 break;
803 case ETH_RSS_HASH_XOR:
804 rss_cfg->hash_algo =
805 HCLGEVF_RSS_HASH_ALGO_SIMPLE;
806 break;
807 case ETH_RSS_HASH_NO_CHANGE:
808 break;
809 default:
810 return -EINVAL;
811 }
812
813 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
814 key);
815 if (ret)
816 return ret;
817
818
819 memcpy(rss_cfg->rss_hash_key, key,
820 HCLGEVF_RSS_KEY_SIZE);
821 }
822 }
823
824
825 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
826 rss_cfg->rss_indirection_tbl[i] = indir[i];
827
828
829 return hclgevf_set_rss_indir_table(hdev);
830}
831
832static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
833{
834 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
835
836 if (nfc->data & RXH_L4_B_2_3)
837 hash_sets |= HCLGEVF_D_PORT_BIT;
838 else
839 hash_sets &= ~HCLGEVF_D_PORT_BIT;
840
841 if (nfc->data & RXH_IP_SRC)
842 hash_sets |= HCLGEVF_S_IP_BIT;
843 else
844 hash_sets &= ~HCLGEVF_S_IP_BIT;
845
846 if (nfc->data & RXH_IP_DST)
847 hash_sets |= HCLGEVF_D_IP_BIT;
848 else
849 hash_sets &= ~HCLGEVF_D_IP_BIT;
850
851 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
852 hash_sets |= HCLGEVF_V_TAG_BIT;
853
854 return hash_sets;
855}
856
857static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
858 struct ethtool_rxnfc *nfc)
859{
860 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
861 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
862 struct hclgevf_rss_input_tuple_cmd *req;
863 struct hclgevf_desc desc;
864 u8 tuple_sets;
865 int ret;
866
867 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
868 return -EOPNOTSUPP;
869
870 if (nfc->data &
871 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
872 return -EINVAL;
873
874 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
875 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
876
877 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
878 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
879 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
880 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
881 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
882 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
883 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
884 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
885
886 tuple_sets = hclgevf_get_rss_hash_bits(nfc);
887 switch (nfc->flow_type) {
888 case TCP_V4_FLOW:
889 req->ipv4_tcp_en = tuple_sets;
890 break;
891 case TCP_V6_FLOW:
892 req->ipv6_tcp_en = tuple_sets;
893 break;
894 case UDP_V4_FLOW:
895 req->ipv4_udp_en = tuple_sets;
896 break;
897 case UDP_V6_FLOW:
898 req->ipv6_udp_en = tuple_sets;
899 break;
900 case SCTP_V4_FLOW:
901 req->ipv4_sctp_en = tuple_sets;
902 break;
903 case SCTP_V6_FLOW:
904 if ((nfc->data & RXH_L4_B_0_1) ||
905 (nfc->data & RXH_L4_B_2_3))
906 return -EINVAL;
907
908 req->ipv6_sctp_en = tuple_sets;
909 break;
910 case IPV4_FLOW:
911 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
912 break;
913 case IPV6_FLOW:
914 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
915 break;
916 default:
917 return -EINVAL;
918 }
919
920 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
921 if (ret) {
922 dev_err(&hdev->pdev->dev,
923 "Set rss tuple fail, status = %d\n", ret);
924 return ret;
925 }
926
927 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
928 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
929 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
930 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
931 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
932 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
933 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
934 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
935 return 0;
936}
937
938static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
939 struct ethtool_rxnfc *nfc)
940{
941 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
942 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
943 u8 tuple_sets;
944
945 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
946 return -EOPNOTSUPP;
947
948 nfc->data = 0;
949
950 switch (nfc->flow_type) {
951 case TCP_V4_FLOW:
952 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
953 break;
954 case UDP_V4_FLOW:
955 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en;
956 break;
957 case TCP_V6_FLOW:
958 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
959 break;
960 case UDP_V6_FLOW:
961 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en;
962 break;
963 case SCTP_V4_FLOW:
964 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
965 break;
966 case SCTP_V6_FLOW:
967 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
968 break;
969 case IPV4_FLOW:
970 case IPV6_FLOW:
971 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
972 break;
973 default:
974 return -EINVAL;
975 }
976
977 if (!tuple_sets)
978 return 0;
979
980 if (tuple_sets & HCLGEVF_D_PORT_BIT)
981 nfc->data |= RXH_L4_B_2_3;
982 if (tuple_sets & HCLGEVF_S_PORT_BIT)
983 nfc->data |= RXH_L4_B_0_1;
984 if (tuple_sets & HCLGEVF_D_IP_BIT)
985 nfc->data |= RXH_IP_DST;
986 if (tuple_sets & HCLGEVF_S_IP_BIT)
987 nfc->data |= RXH_IP_SRC;
988
989 return 0;
990}
991
992static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
993 struct hclgevf_rss_cfg *rss_cfg)
994{
995 struct hclgevf_rss_input_tuple_cmd *req;
996 struct hclgevf_desc desc;
997 int ret;
998
999 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
1000
1001 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
1002
1003 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
1004 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
1005 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
1006 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
1007 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
1008 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
1009 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
1010 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
1011
1012 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1013 if (ret)
1014 dev_err(&hdev->pdev->dev,
1015 "Configure rss input fail, status = %d\n", ret);
1016 return ret;
1017}
1018
1019static int hclgevf_get_tc_size(struct hnae3_handle *handle)
1020{
1021 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1022 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1023
1024 return rss_cfg->rss_size;
1025}
1026
1027static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
1028 int vector_id,
1029 struct hnae3_ring_chain_node *ring_chain)
1030{
1031 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1032 struct hclge_vf_to_pf_msg send_msg;
1033 struct hnae3_ring_chain_node *node;
1034 int status;
1035 int i = 0;
1036
1037 memset(&send_msg, 0, sizeof(send_msg));
1038 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
1039 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
1040 send_msg.vector_id = vector_id;
1041
1042 for (node = ring_chain; node; node = node->next) {
1043 send_msg.param[i].ring_type =
1044 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
1045
1046 send_msg.param[i].tqp_index = node->tqp_index;
1047 send_msg.param[i].int_gl_index =
1048 hnae3_get_field(node->int_gl_idx,
1049 HNAE3_RING_GL_IDX_M,
1050 HNAE3_RING_GL_IDX_S);
1051
1052 i++;
1053 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
1054 send_msg.ring_num = i;
1055
1056 status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
1057 NULL, 0);
1058 if (status) {
1059 dev_err(&hdev->pdev->dev,
1060 "Map TQP fail, status is %d.\n",
1061 status);
1062 return status;
1063 }
1064 i = 0;
1065 }
1066 }
1067
1068 return 0;
1069}
1070
1071static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
1072 struct hnae3_ring_chain_node *ring_chain)
1073{
1074 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1075 int vector_id;
1076
1077 vector_id = hclgevf_get_vector_index(hdev, vector);
1078 if (vector_id < 0) {
1079 dev_err(&handle->pdev->dev,
1080 "Get vector index fail. ret =%d\n", vector_id);
1081 return vector_id;
1082 }
1083
1084 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
1085}
1086
1087static int hclgevf_unmap_ring_from_vector(
1088 struct hnae3_handle *handle,
1089 int vector,
1090 struct hnae3_ring_chain_node *ring_chain)
1091{
1092 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1093 int ret, vector_id;
1094
1095 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1096 return 0;
1097
1098 vector_id = hclgevf_get_vector_index(hdev, vector);
1099 if (vector_id < 0) {
1100 dev_err(&handle->pdev->dev,
1101 "Get vector index fail. ret =%d\n", vector_id);
1102 return vector_id;
1103 }
1104
1105 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
1106 if (ret)
1107 dev_err(&handle->pdev->dev,
1108 "Unmap ring from vector fail. vector=%d, ret =%d\n",
1109 vector_id,
1110 ret);
1111
1112 return ret;
1113}
1114
1115static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
1116{
1117 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1118 int vector_id;
1119
1120 vector_id = hclgevf_get_vector_index(hdev, vector);
1121 if (vector_id < 0) {
1122 dev_err(&handle->pdev->dev,
1123 "hclgevf_put_vector get vector index fail. ret =%d\n",
1124 vector_id);
1125 return vector_id;
1126 }
1127
1128 hclgevf_free_vector(hdev, vector_id);
1129
1130 return 0;
1131}
1132
1133static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
1134 bool en_uc_pmc, bool en_mc_pmc,
1135 bool en_bc_pmc)
1136{
1137 struct hclge_vf_to_pf_msg send_msg;
1138 int ret;
1139
1140 memset(&send_msg, 0, sizeof(send_msg));
1141 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
1142 send_msg.en_bc = en_bc_pmc ? 1 : 0;
1143 send_msg.en_uc = en_uc_pmc ? 1 : 0;
1144 send_msg.en_mc = en_mc_pmc ? 1 : 0;
1145
1146 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1147 if (ret)
1148 dev_err(&hdev->pdev->dev,
1149 "Set promisc mode fail, status is %d.\n", ret);
1150
1151 return ret;
1152}
1153
1154static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
1155 bool en_mc_pmc)
1156{
1157 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1158 bool en_bc_pmc;
1159
1160 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
1161
1162 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
1163 en_bc_pmc);
1164}
1165
1166static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
1167{
1168 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1169
1170 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1171}
1172
1173static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
1174{
1175 struct hnae3_handle *handle = &hdev->nic;
1176 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
1177 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
1178 int ret;
1179
1180 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
1181 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
1182 if (!ret)
1183 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1184 }
1185}
1186
1187static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id,
1188 int stream_id, bool enable)
1189{
1190 struct hclgevf_cfg_com_tqp_queue_cmd *req;
1191 struct hclgevf_desc desc;
1192 int status;
1193
1194 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
1195
1196 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
1197 false);
1198 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
1199 req->stream_id = cpu_to_le16(stream_id);
1200 if (enable)
1201 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
1202
1203 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1204 if (status)
1205 dev_err(&hdev->pdev->dev,
1206 "TQP enable fail, status =%d.\n", status);
1207
1208 return status;
1209}
1210
1211static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
1212{
1213 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1214 struct hclgevf_tqp *tqp;
1215 int i;
1216
1217 for (i = 0; i < kinfo->num_tqps; i++) {
1218 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
1219 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
1220 }
1221}
1222
1223static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
1224{
1225 struct hclge_vf_to_pf_msg send_msg;
1226 u8 host_mac[ETH_ALEN];
1227 int status;
1228
1229 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
1230 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
1231 ETH_ALEN);
1232 if (status) {
1233 dev_err(&hdev->pdev->dev,
1234 "fail to get VF MAC from host %d", status);
1235 return status;
1236 }
1237
1238 ether_addr_copy(p, host_mac);
1239
1240 return 0;
1241}
1242
1243static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
1244{
1245 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1246 u8 host_mac_addr[ETH_ALEN];
1247
1248 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
1249 return;
1250
1251 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
1252 if (hdev->has_pf_mac)
1253 ether_addr_copy(p, host_mac_addr);
1254 else
1255 ether_addr_copy(p, hdev->hw.mac.mac_addr);
1256}
1257
1258static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
1259 bool is_first)
1260{
1261 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1262 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
1263 struct hclge_vf_to_pf_msg send_msg;
1264 u8 *new_mac_addr = (u8 *)p;
1265 int status;
1266
1267 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
1268 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1269 ether_addr_copy(send_msg.data, new_mac_addr);
1270 if (is_first && !hdev->has_pf_mac)
1271 eth_zero_addr(&send_msg.data[ETH_ALEN]);
1272 else
1273 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
1274 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1275 if (!status)
1276 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1277
1278 return status;
1279}
1280
1281static struct hclgevf_mac_addr_node *
1282hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
1283{
1284 struct hclgevf_mac_addr_node *mac_node, *tmp;
1285
1286 list_for_each_entry_safe(mac_node, tmp, list, node)
1287 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
1288 return mac_node;
1289
1290 return NULL;
1291}
1292
1293static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
1294 enum HCLGEVF_MAC_NODE_STATE state)
1295{
1296 switch (state) {
1297
1298 case HCLGEVF_MAC_TO_ADD:
1299 if (mac_node->state == HCLGEVF_MAC_TO_DEL)
1300 mac_node->state = HCLGEVF_MAC_ACTIVE;
1301 break;
1302
1303 case HCLGEVF_MAC_TO_DEL:
1304 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1305 list_del(&mac_node->node);
1306 kfree(mac_node);
1307 } else {
1308 mac_node->state = HCLGEVF_MAC_TO_DEL;
1309 }
1310 break;
1311
1312
1313
1314 case HCLGEVF_MAC_ACTIVE:
1315 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1316 mac_node->state = HCLGEVF_MAC_ACTIVE;
1317 break;
1318 }
1319}
1320
1321static int hclgevf_update_mac_list(struct hnae3_handle *handle,
1322 enum HCLGEVF_MAC_NODE_STATE state,
1323 enum HCLGEVF_MAC_ADDR_TYPE mac_type,
1324 const unsigned char *addr)
1325{
1326 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1327 struct hclgevf_mac_addr_node *mac_node;
1328 struct list_head *list;
1329
1330 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1331 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1332
1333 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1334
1335
1336
1337
1338
1339 mac_node = hclgevf_find_mac_node(list, addr);
1340 if (mac_node) {
1341 hclgevf_update_mac_node(mac_node, state);
1342 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1343 return 0;
1344 }
1345
1346 if (state == HCLGEVF_MAC_TO_DEL) {
1347 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1348 return -ENOENT;
1349 }
1350
1351 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
1352 if (!mac_node) {
1353 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1354 return -ENOMEM;
1355 }
1356
1357 mac_node->state = state;
1358 ether_addr_copy(mac_node->mac_addr, addr);
1359 list_add_tail(&mac_node->node, list);
1360
1361 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1362 return 0;
1363}
1364
1365static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1366 const unsigned char *addr)
1367{
1368 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1369 HCLGEVF_MAC_ADDR_UC, addr);
1370}
1371
1372static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1373 const unsigned char *addr)
1374{
1375 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1376 HCLGEVF_MAC_ADDR_UC, addr);
1377}
1378
1379static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1380 const unsigned char *addr)
1381{
1382 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1383 HCLGEVF_MAC_ADDR_MC, addr);
1384}
1385
1386static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1387 const unsigned char *addr)
1388{
1389 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1390 HCLGEVF_MAC_ADDR_MC, addr);
1391}
1392
1393static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
1394 struct hclgevf_mac_addr_node *mac_node,
1395 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1396{
1397 struct hclge_vf_to_pf_msg send_msg;
1398 u8 code, subcode;
1399
1400 if (mac_type == HCLGEVF_MAC_ADDR_UC) {
1401 code = HCLGE_MBX_SET_UNICAST;
1402 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1403 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
1404 else
1405 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
1406 } else {
1407 code = HCLGE_MBX_SET_MULTICAST;
1408 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1409 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1410 else
1411 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1412 }
1413
1414 hclgevf_build_send_msg(&send_msg, code, subcode);
1415 ether_addr_copy(send_msg.data, mac_node->mac_addr);
1416 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1417}
1418
1419static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1420 struct list_head *list,
1421 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1422{
1423 struct hclgevf_mac_addr_node *mac_node, *tmp;
1424 int ret;
1425
1426 list_for_each_entry_safe(mac_node, tmp, list, node) {
1427 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1428 if (ret) {
1429 dev_err(&hdev->pdev->dev,
1430 "failed to configure mac %pM, state = %d, ret = %d\n",
1431 mac_node->mac_addr, mac_node->state, ret);
1432 return;
1433 }
1434 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1435 mac_node->state = HCLGEVF_MAC_ACTIVE;
1436 } else {
1437 list_del(&mac_node->node);
1438 kfree(mac_node);
1439 }
1440 }
1441}
1442
1443static void hclgevf_sync_from_add_list(struct list_head *add_list,
1444 struct list_head *mac_list)
1445{
1446 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1447
1448 list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1449
1450
1451
1452
1453
1454
1455
1456 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1457 if (new_node) {
1458 hclgevf_update_mac_node(new_node, mac_node->state);
1459 list_del(&mac_node->node);
1460 kfree(mac_node);
1461 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1462 mac_node->state = HCLGEVF_MAC_TO_DEL;
1463 list_del(&mac_node->node);
1464 list_add_tail(&mac_node->node, mac_list);
1465 } else {
1466 list_del(&mac_node->node);
1467 kfree(mac_node);
1468 }
1469 }
1470}
1471
1472static void hclgevf_sync_from_del_list(struct list_head *del_list,
1473 struct list_head *mac_list)
1474{
1475 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1476
1477 list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1478 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1479 if (new_node) {
1480
1481
1482
1483
1484
1485 new_node->state = HCLGEVF_MAC_ACTIVE;
1486 list_del(&mac_node->node);
1487 kfree(mac_node);
1488 } else {
1489 list_del(&mac_node->node);
1490 list_add_tail(&mac_node->node, mac_list);
1491 }
1492 }
1493}
1494
1495static void hclgevf_clear_list(struct list_head *list)
1496{
1497 struct hclgevf_mac_addr_node *mac_node, *tmp;
1498
1499 list_for_each_entry_safe(mac_node, tmp, list, node) {
1500 list_del(&mac_node->node);
1501 kfree(mac_node);
1502 }
1503}
1504
1505static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1506 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1507{
1508 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1509 struct list_head tmp_add_list, tmp_del_list;
1510 struct list_head *list;
1511
1512 INIT_LIST_HEAD(&tmp_add_list);
1513 INIT_LIST_HEAD(&tmp_del_list);
1514
1515
1516
1517
1518 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1519 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1520
1521 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1522
1523 list_for_each_entry_safe(mac_node, tmp, list, node) {
1524 switch (mac_node->state) {
1525 case HCLGEVF_MAC_TO_DEL:
1526 list_del(&mac_node->node);
1527 list_add_tail(&mac_node->node, &tmp_del_list);
1528 break;
1529 case HCLGEVF_MAC_TO_ADD:
1530 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1531 if (!new_node)
1532 goto stop_traverse;
1533
1534 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1535 new_node->state = mac_node->state;
1536 list_add_tail(&new_node->node, &tmp_add_list);
1537 break;
1538 default:
1539 break;
1540 }
1541 }
1542
1543stop_traverse:
1544 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1545
1546
1547 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1548 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1549
1550
1551
1552
1553 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1554
1555 hclgevf_sync_from_del_list(&tmp_del_list, list);
1556 hclgevf_sync_from_add_list(&tmp_add_list, list);
1557
1558 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1559}
1560
1561static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1562{
1563 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1564 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1565}
1566
1567static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1568{
1569 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1570
1571 hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1572 hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1573
1574 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1575}
1576
1577static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1578 __be16 proto, u16 vlan_id,
1579 bool is_kill)
1580{
1581#define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0
1582#define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1
1583#define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3
1584
1585 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1586 struct hclge_vf_to_pf_msg send_msg;
1587 int ret;
1588
1589 if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1590 return -EINVAL;
1591
1592 if (proto != htons(ETH_P_8021Q))
1593 return -EPROTONOSUPPORT;
1594
1595
1596
1597
1598
1599 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1600 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1601 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1602 return -EBUSY;
1603 }
1604
1605 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1606 HCLGE_MBX_VLAN_FILTER);
1607 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill;
1608 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id,
1609 sizeof(vlan_id));
1610 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto,
1611 sizeof(proto));
1612
1613
1614
1615
1616 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1617 if (is_kill && ret)
1618 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1619
1620 return ret;
1621}
1622
1623static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1624{
1625#define HCLGEVF_MAX_SYNC_COUNT 60
1626 struct hnae3_handle *handle = &hdev->nic;
1627 int ret, sync_cnt = 0;
1628 u16 vlan_id;
1629
1630 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1631 while (vlan_id != VLAN_N_VID) {
1632 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1633 vlan_id, true);
1634 if (ret)
1635 return;
1636
1637 clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1638 sync_cnt++;
1639 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1640 return;
1641
1642 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1643 }
1644}
1645
1646static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1647{
1648 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1649 struct hclge_vf_to_pf_msg send_msg;
1650
1651 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1652 HCLGE_MBX_VLAN_RX_OFF_CFG);
1653 send_msg.data[0] = enable ? 1 : 0;
1654 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1655}
1656
1657static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
1658{
1659 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1660 struct hclge_vf_to_pf_msg send_msg;
1661 int ret;
1662
1663
1664 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
1665 if (ret)
1666 return ret;
1667
1668 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1669 memcpy(send_msg.data, &queue_id, sizeof(queue_id));
1670 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1671}
1672
1673static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1674{
1675 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1676 struct hclge_vf_to_pf_msg send_msg;
1677
1678 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1679 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu));
1680 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1681}
1682
1683static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1684 enum hnae3_reset_notify_type type)
1685{
1686 struct hnae3_client *client = hdev->nic_client;
1687 struct hnae3_handle *handle = &hdev->nic;
1688 int ret;
1689
1690 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1691 !client)
1692 return 0;
1693
1694 if (!client->ops->reset_notify)
1695 return -EOPNOTSUPP;
1696
1697 ret = client->ops->reset_notify(handle, type);
1698 if (ret)
1699 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1700 type, ret);
1701
1702 return ret;
1703}
1704
1705static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
1706 enum hnae3_reset_notify_type type)
1707{
1708 struct hnae3_client *client = hdev->roce_client;
1709 struct hnae3_handle *handle = &hdev->roce;
1710 int ret;
1711
1712 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)
1713 return 0;
1714
1715 if (!client->ops->reset_notify)
1716 return -EOPNOTSUPP;
1717
1718 ret = client->ops->reset_notify(handle, type);
1719 if (ret)
1720 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
1721 type, ret);
1722 return ret;
1723}
1724
1725static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1726{
1727#define HCLGEVF_RESET_WAIT_US 20000
1728#define HCLGEVF_RESET_WAIT_CNT 2000
1729#define HCLGEVF_RESET_WAIT_TIMEOUT_US \
1730 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1731
1732 u32 val;
1733 int ret;
1734
1735 if (hdev->reset_type == HNAE3_VF_RESET)
1736 ret = readl_poll_timeout(hdev->hw.io_base +
1737 HCLGEVF_VF_RST_ING, val,
1738 !(val & HCLGEVF_VF_RST_ING_BIT),
1739 HCLGEVF_RESET_WAIT_US,
1740 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1741 else
1742 ret = readl_poll_timeout(hdev->hw.io_base +
1743 HCLGEVF_RST_ING, val,
1744 !(val & HCLGEVF_RST_ING_BITS),
1745 HCLGEVF_RESET_WAIT_US,
1746 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1747
1748
1749 if (ret) {
1750 dev_err(&hdev->pdev->dev,
1751 "couldn't get reset done status from h/w, timeout!\n");
1752 return ret;
1753 }
1754
1755
1756
1757
1758
1759 msleep(5000);
1760
1761 return 0;
1762}
1763
1764static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1765{
1766 u32 reg_val;
1767
1768 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
1769 if (enable)
1770 reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1771 else
1772 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1773
1774 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG,
1775 reg_val);
1776}
1777
1778static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1779{
1780 int ret;
1781
1782
1783 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1784 if (ret)
1785 return ret;
1786
1787
1788 ret = hclgevf_reset_hdev(hdev);
1789 if (ret) {
1790 dev_err(&hdev->pdev->dev,
1791 "hclge device re-init failed, VF is disabled!\n");
1792 return ret;
1793 }
1794
1795
1796 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1797 if (ret)
1798 return ret;
1799
1800
1801 hclgevf_reset_handshake(hdev, false);
1802
1803
1804 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1805}
1806
1807static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1808{
1809#define HCLGEVF_RESET_SYNC_TIME 100
1810
1811 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1812 struct hclge_vf_to_pf_msg send_msg;
1813 int ret;
1814
1815 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1816 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1817 if (ret) {
1818 dev_err(&hdev->pdev->dev,
1819 "failed to assert VF reset, ret = %d\n", ret);
1820 return ret;
1821 }
1822 hdev->rst_stats.vf_func_rst_cnt++;
1823 }
1824
1825 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1826
1827 msleep(HCLGEVF_RESET_SYNC_TIME);
1828 hclgevf_reset_handshake(hdev, true);
1829 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",
1830 hdev->reset_type);
1831
1832 return 0;
1833}
1834
1835static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1836{
1837 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1838 hdev->rst_stats.vf_func_rst_cnt);
1839 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1840 hdev->rst_stats.flr_rst_cnt);
1841 dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1842 hdev->rst_stats.vf_rst_cnt);
1843 dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1844 hdev->rst_stats.rst_done_cnt);
1845 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1846 hdev->rst_stats.hw_rst_done_cnt);
1847 dev_info(&hdev->pdev->dev, "reset count: %u\n",
1848 hdev->rst_stats.rst_cnt);
1849 dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1850 hdev->rst_stats.rst_fail_cnt);
1851 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1852 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1853 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1854 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
1855 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1856 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
1857 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1858 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1859 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1860}
1861
1862static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1863{
1864
1865 hclgevf_reset_handshake(hdev, true);
1866 hdev->rst_stats.rst_fail_cnt++;
1867 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1868 hdev->rst_stats.rst_fail_cnt);
1869
1870 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1871 set_bit(hdev->reset_type, &hdev->reset_pending);
1872
1873 if (hclgevf_is_reset_pending(hdev)) {
1874 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1875 hclgevf_reset_task_schedule(hdev);
1876 } else {
1877 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1878 hclgevf_dump_rst_info(hdev);
1879 }
1880}
1881
1882static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
1883{
1884 int ret;
1885
1886 hdev->rst_stats.rst_cnt++;
1887
1888
1889 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
1890 if (ret)
1891 return ret;
1892
1893 rtnl_lock();
1894
1895 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1896 rtnl_unlock();
1897 if (ret)
1898 return ret;
1899
1900 return hclgevf_reset_prepare_wait(hdev);
1901}
1902
1903static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
1904{
1905 int ret;
1906
1907 hdev->rst_stats.hw_rst_done_cnt++;
1908 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
1909 if (ret)
1910 return ret;
1911
1912 rtnl_lock();
1913
1914 ret = hclgevf_reset_stack(hdev);
1915 rtnl_unlock();
1916 if (ret) {
1917 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1918 return ret;
1919 }
1920
1921 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
1922
1923
1924
1925 if (ret &&
1926 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)
1927 return ret;
1928
1929 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);
1930 if (ret)
1931 return ret;
1932
1933 hdev->last_reset_time = jiffies;
1934 hdev->rst_stats.rst_done_cnt++;
1935 hdev->rst_stats.rst_fail_cnt = 0;
1936 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1937
1938 return 0;
1939}
1940
1941static void hclgevf_reset(struct hclgevf_dev *hdev)
1942{
1943 if (hclgevf_reset_prepare(hdev))
1944 goto err_reset;
1945
1946
1947
1948
1949 if (hclgevf_reset_wait(hdev)) {
1950
1951 dev_err(&hdev->pdev->dev,
1952 "failed to fetch H/W reset completion status\n");
1953 goto err_reset;
1954 }
1955
1956 if (hclgevf_reset_rebuild(hdev))
1957 goto err_reset;
1958
1959 return;
1960
1961err_reset:
1962 hclgevf_reset_err_handle(hdev);
1963}
1964
1965static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
1966 unsigned long *addr)
1967{
1968 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
1969
1970
1971 if (test_bit(HNAE3_VF_RESET, addr)) {
1972 rst_level = HNAE3_VF_RESET;
1973 clear_bit(HNAE3_VF_RESET, addr);
1974 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1975 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1976 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
1977 rst_level = HNAE3_VF_FULL_RESET;
1978 clear_bit(HNAE3_VF_FULL_RESET, addr);
1979 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1980 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
1981 rst_level = HNAE3_VF_PF_FUNC_RESET;
1982 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1983 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1984 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
1985 rst_level = HNAE3_VF_FUNC_RESET;
1986 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1987 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
1988 rst_level = HNAE3_FLR_RESET;
1989 clear_bit(HNAE3_FLR_RESET, addr);
1990 }
1991
1992 return rst_level;
1993}
1994
1995static void hclgevf_reset_event(struct pci_dev *pdev,
1996 struct hnae3_handle *handle)
1997{
1998 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1999 struct hclgevf_dev *hdev = ae_dev->priv;
2000
2001 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
2002
2003 if (hdev->default_reset_request)
2004 hdev->reset_level =
2005 hclgevf_get_reset_level(hdev,
2006 &hdev->default_reset_request);
2007 else
2008 hdev->reset_level = HNAE3_VF_FUNC_RESET;
2009
2010
2011 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
2012 hclgevf_reset_task_schedule(hdev);
2013
2014 hdev->last_reset_time = jiffies;
2015}
2016
2017static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2018 enum hnae3_reset_type rst_type)
2019{
2020 struct hclgevf_dev *hdev = ae_dev->priv;
2021
2022 set_bit(rst_type, &hdev->default_reset_request);
2023}
2024
2025static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
2026{
2027 writel(en ? 1 : 0, vector->addr);
2028}
2029
2030static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev)
2031{
2032#define HCLGEVF_FLR_RETRY_WAIT_MS 500
2033#define HCLGEVF_FLR_RETRY_CNT 5
2034
2035 struct hclgevf_dev *hdev = ae_dev->priv;
2036 int retry_cnt = 0;
2037 int ret;
2038
2039retry:
2040 down(&hdev->reset_sem);
2041 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2042 hdev->reset_type = HNAE3_FLR_RESET;
2043 ret = hclgevf_reset_prepare(hdev);
2044 if (ret) {
2045 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n",
2046 ret);
2047 if (hdev->reset_pending ||
2048 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) {
2049 dev_err(&hdev->pdev->dev,
2050 "reset_pending:0x%lx, retry_cnt:%d\n",
2051 hdev->reset_pending, retry_cnt);
2052 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2053 up(&hdev->reset_sem);
2054 msleep(HCLGEVF_FLR_RETRY_WAIT_MS);
2055 goto retry;
2056 }
2057 }
2058
2059
2060 hclgevf_enable_vector(&hdev->misc_vector, false);
2061 hdev->rst_stats.flr_rst_cnt++;
2062}
2063
2064static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev)
2065{
2066 struct hclgevf_dev *hdev = ae_dev->priv;
2067 int ret;
2068
2069 hclgevf_enable_vector(&hdev->misc_vector, true);
2070
2071 ret = hclgevf_reset_rebuild(hdev);
2072 if (ret)
2073 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
2074 ret);
2075
2076 hdev->reset_type = HNAE3_NONE_RESET;
2077 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2078 up(&hdev->reset_sem);
2079}
2080
2081static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
2082{
2083 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2084
2085 return hdev->fw_version;
2086}
2087
2088static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
2089{
2090 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
2091
2092 vector->vector_irq = pci_irq_vector(hdev->pdev,
2093 HCLGEVF_MISC_VECTOR_NUM);
2094 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
2095
2096 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
2097 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
2098
2099 hdev->num_msi_left -= 1;
2100 hdev->num_msi_used += 1;
2101}
2102
2103void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
2104{
2105 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2106 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
2107 &hdev->state))
2108 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2109}
2110
2111void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
2112{
2113 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2114 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
2115 &hdev->state))
2116 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2117}
2118
2119static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
2120 unsigned long delay)
2121{
2122 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2123 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2124 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
2125}
2126
2127static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
2128{
2129#define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3
2130
2131 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
2132 return;
2133
2134 down(&hdev->reset_sem);
2135 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2136
2137 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
2138 &hdev->reset_state)) {
2139
2140
2141
2142
2143
2144 hdev->reset_attempts = 0;
2145
2146 hdev->last_reset_time = jiffies;
2147 while ((hdev->reset_type =
2148 hclgevf_get_reset_level(hdev, &hdev->reset_pending))
2149 != HNAE3_NONE_RESET)
2150 hclgevf_reset(hdev);
2151 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
2152 &hdev->reset_state)) {
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
2177
2178 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
2179
2180
2181 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2182 } else {
2183 hdev->reset_attempts++;
2184
2185 set_bit(hdev->reset_level, &hdev->reset_pending);
2186 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2187 }
2188 hclgevf_reset_task_schedule(hdev);
2189 }
2190
2191 hdev->reset_type = HNAE3_NONE_RESET;
2192 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2193 up(&hdev->reset_sem);
2194}
2195
2196static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
2197{
2198 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
2199 return;
2200
2201 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
2202 return;
2203
2204 hclgevf_mbx_async_handler(hdev);
2205
2206 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2207}
2208
2209static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
2210{
2211 struct hclge_vf_to_pf_msg send_msg;
2212 int ret;
2213
2214 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
2215 return;
2216
2217 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
2218 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2219 if (ret)
2220 dev_err(&hdev->pdev->dev,
2221 "VF sends keep alive cmd failed(=%d)\n", ret);
2222}
2223
2224static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
2225{
2226 unsigned long delta = round_jiffies_relative(HZ);
2227 struct hnae3_handle *handle = &hdev->nic;
2228
2229 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2230 return;
2231
2232 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
2233 delta = jiffies - hdev->last_serv_processed;
2234
2235 if (delta < round_jiffies_relative(HZ)) {
2236 delta = round_jiffies_relative(HZ) - delta;
2237 goto out;
2238 }
2239 }
2240
2241 hdev->serv_processed_cnt++;
2242 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
2243 hclgevf_keep_alive(hdev);
2244
2245 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
2246 hdev->last_serv_processed = jiffies;
2247 goto out;
2248 }
2249
2250 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
2251 hclgevf_tqps_update_stats(handle);
2252
2253
2254
2255
2256 hclgevf_request_link_info(hdev);
2257
2258 hclgevf_update_link_mode(hdev);
2259
2260 hclgevf_sync_vlan_filter(hdev);
2261
2262 hclgevf_sync_mac_table(hdev);
2263
2264 hclgevf_sync_promisc_mode(hdev);
2265
2266 hdev->last_serv_processed = jiffies;
2267
2268out:
2269 hclgevf_task_schedule(hdev, delta);
2270}
2271
2272static void hclgevf_service_task(struct work_struct *work)
2273{
2274 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
2275 service_task.work);
2276
2277 hclgevf_reset_service_task(hdev);
2278 hclgevf_mailbox_service_task(hdev);
2279 hclgevf_periodic_service_task(hdev);
2280
2281
2282
2283
2284
2285 hclgevf_reset_service_task(hdev);
2286 hclgevf_mailbox_service_task(hdev);
2287}
2288
2289static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
2290{
2291 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
2292}
2293
2294static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
2295 u32 *clearval)
2296{
2297 u32 val, cmdq_stat_reg, rst_ing_reg;
2298
2299
2300 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
2301 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
2302
2303 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
2304 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2305 dev_info(&hdev->pdev->dev,
2306 "receive reset interrupt 0x%x!\n", rst_ing_reg);
2307 set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
2308 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2309 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
2310 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
2311 hdev->rst_stats.vf_rst_cnt++;
2312
2313
2314
2315 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
2316 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
2317 val | HCLGEVF_VF_RST_ING_BIT);
2318 return HCLGEVF_VECTOR0_EVENT_RST;
2319 }
2320
2321
2322 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
2323
2324
2325
2326
2327
2328
2329
2330 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
2331 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2332 else
2333 *clearval = cmdq_stat_reg &
2334 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2335
2336 return HCLGEVF_VECTOR0_EVENT_MBX;
2337 }
2338
2339
2340 dev_info(&hdev->pdev->dev,
2341 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
2342 cmdq_stat_reg);
2343
2344 return HCLGEVF_VECTOR0_EVENT_OTHER;
2345}
2346
2347static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
2348{
2349 enum hclgevf_evt_cause event_cause;
2350 struct hclgevf_dev *hdev = data;
2351 u32 clearval;
2352
2353 hclgevf_enable_vector(&hdev->misc_vector, false);
2354 event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2355
2356 switch (event_cause) {
2357 case HCLGEVF_VECTOR0_EVENT_RST:
2358 hclgevf_reset_task_schedule(hdev);
2359 break;
2360 case HCLGEVF_VECTOR0_EVENT_MBX:
2361 hclgevf_mbx_handler(hdev);
2362 break;
2363 default:
2364 break;
2365 }
2366
2367 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
2368 hclgevf_clear_event_cause(hdev, clearval);
2369 hclgevf_enable_vector(&hdev->misc_vector, true);
2370 }
2371
2372 return IRQ_HANDLED;
2373}
2374
2375static int hclgevf_configure(struct hclgevf_dev *hdev)
2376{
2377 int ret;
2378
2379
2380 ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2381 if (ret)
2382 return ret;
2383
2384
2385 ret = hclgevf_get_queue_info(hdev);
2386 if (ret)
2387 return ret;
2388
2389
2390 ret = hclgevf_get_queue_depth(hdev);
2391 if (ret)
2392 return ret;
2393
2394 ret = hclgevf_get_pf_media_type(hdev);
2395 if (ret)
2396 return ret;
2397
2398
2399 return hclgevf_get_tc_info(hdev);
2400}
2401
2402static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2403{
2404 struct pci_dev *pdev = ae_dev->pdev;
2405 struct hclgevf_dev *hdev;
2406
2407 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2408 if (!hdev)
2409 return -ENOMEM;
2410
2411 hdev->pdev = pdev;
2412 hdev->ae_dev = ae_dev;
2413 ae_dev->priv = hdev;
2414
2415 return 0;
2416}
2417
2418static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2419{
2420 struct hnae3_handle *roce = &hdev->roce;
2421 struct hnae3_handle *nic = &hdev->nic;
2422
2423 roce->rinfo.num_vectors = hdev->num_roce_msix;
2424
2425 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2426 hdev->num_msi_left == 0)
2427 return -EINVAL;
2428
2429 roce->rinfo.base_vector = hdev->roce_base_vector;
2430
2431 roce->rinfo.netdev = nic->kinfo.netdev;
2432 roce->rinfo.roce_io_base = hdev->hw.io_base;
2433
2434 roce->pdev = nic->pdev;
2435 roce->ae_algo = nic->ae_algo;
2436 roce->numa_node_mask = nic->numa_node_mask;
2437
2438 return 0;
2439}
2440
2441static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
2442{
2443 struct hclgevf_cfg_gro_status_cmd *req;
2444 struct hclgevf_desc desc;
2445 int ret;
2446
2447 if (!hnae3_dev_gro_supported(hdev))
2448 return 0;
2449
2450 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
2451 false);
2452 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2453
2454 req->gro_en = en ? 1 : 0;
2455
2456 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2457 if (ret)
2458 dev_err(&hdev->pdev->dev,
2459 "VF GRO hardware config cmd failed, ret = %d.\n", ret);
2460
2461 return ret;
2462}
2463
2464static void hclgevf_rss_init_cfg(struct hclgevf_dev *hdev)
2465{
2466 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2467 struct hclgevf_rss_tuple_cfg *tuple_sets;
2468 u32 i;
2469
2470 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
2471 rss_cfg->rss_size = hdev->nic.kinfo.rss_size;
2472 tuple_sets = &rss_cfg->rss_tuple_sets;
2473 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2474 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
2475 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
2476 HCLGEVF_RSS_KEY_SIZE);
2477
2478 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2479 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2480 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2481 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2482 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2483 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2484 tuple_sets->ipv6_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2485 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2486 }
2487
2488
2489 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
2490 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size;
2491}
2492
2493static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2494{
2495 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2496 int ret;
2497
2498 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2499 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
2500 rss_cfg->rss_hash_key);
2501 if (ret)
2502 return ret;
2503
2504 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
2505 if (ret)
2506 return ret;
2507 }
2508
2509 ret = hclgevf_set_rss_indir_table(hdev);
2510 if (ret)
2511 return ret;
2512
2513 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size);
2514}
2515
2516static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2517{
2518 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2519 false);
2520}
2521
2522static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2523{
2524#define HCLGEVF_FLUSH_LINK_TIMEOUT 100000
2525
2526 unsigned long last = hdev->serv_processed_cnt;
2527 int i = 0;
2528
2529 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2530 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2531 last == hdev->serv_processed_cnt)
2532 usleep_range(1, 1);
2533}
2534
2535static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2536{
2537 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2538
2539 if (enable) {
2540 hclgevf_task_schedule(hdev, 0);
2541 } else {
2542 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2543
2544
2545 smp_mb__before_atomic();
2546 hclgevf_flush_link_update(hdev);
2547 }
2548}
2549
2550static int hclgevf_ae_start(struct hnae3_handle *handle)
2551{
2552 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2553
2554 hclgevf_reset_tqp_stats(handle);
2555
2556 hclgevf_request_link_info(hdev);
2557
2558 hclgevf_update_link_mode(hdev);
2559
2560 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2561
2562 return 0;
2563}
2564
2565static void hclgevf_ae_stop(struct hnae3_handle *handle)
2566{
2567 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2568 int i;
2569
2570 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2571
2572 if (hdev->reset_type != HNAE3_VF_RESET)
2573 for (i = 0; i < handle->kinfo.num_tqps; i++)
2574 if (hclgevf_reset_tqp(handle, i))
2575 break;
2576
2577 hclgevf_reset_tqp_stats(handle);
2578 hclgevf_update_link_status(hdev, 0);
2579}
2580
2581static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2582{
2583#define HCLGEVF_STATE_ALIVE 1
2584#define HCLGEVF_STATE_NOT_ALIVE 0
2585
2586 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2587 struct hclge_vf_to_pf_msg send_msg;
2588
2589 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2590 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2591 HCLGEVF_STATE_NOT_ALIVE;
2592 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2593}
2594
2595static int hclgevf_client_start(struct hnae3_handle *handle)
2596{
2597 return hclgevf_set_alive(handle, true);
2598}
2599
2600static void hclgevf_client_stop(struct hnae3_handle *handle)
2601{
2602 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2603 int ret;
2604
2605 ret = hclgevf_set_alive(handle, false);
2606 if (ret)
2607 dev_warn(&hdev->pdev->dev,
2608 "%s failed %d\n", __func__, ret);
2609}
2610
2611static void hclgevf_state_init(struct hclgevf_dev *hdev)
2612{
2613 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2614 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2615 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2616
2617 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2618
2619 mutex_init(&hdev->mbx_resp.mbx_mutex);
2620 sema_init(&hdev->reset_sem, 1);
2621
2622 spin_lock_init(&hdev->mac_table.mac_list_lock);
2623 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2624 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2625
2626
2627 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2628}
2629
2630static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2631{
2632 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2633 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2634
2635 if (hdev->service_task.work.func)
2636 cancel_delayed_work_sync(&hdev->service_task);
2637
2638 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2639}
2640
2641static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2642{
2643 struct pci_dev *pdev = hdev->pdev;
2644 int vectors;
2645 int i;
2646
2647 if (hnae3_dev_roce_supported(hdev))
2648 vectors = pci_alloc_irq_vectors(pdev,
2649 hdev->roce_base_msix_offset + 1,
2650 hdev->num_msi,
2651 PCI_IRQ_MSIX);
2652 else
2653 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2654 hdev->num_msi,
2655 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2656
2657 if (vectors < 0) {
2658 dev_err(&pdev->dev,
2659 "failed(%d) to allocate MSI/MSI-X vectors\n",
2660 vectors);
2661 return vectors;
2662 }
2663 if (vectors < hdev->num_msi)
2664 dev_warn(&hdev->pdev->dev,
2665 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2666 hdev->num_msi, vectors);
2667
2668 hdev->num_msi = vectors;
2669 hdev->num_msi_left = vectors;
2670
2671 hdev->base_msi_vector = pdev->irq;
2672 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
2673
2674 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2675 sizeof(u16), GFP_KERNEL);
2676 if (!hdev->vector_status) {
2677 pci_free_irq_vectors(pdev);
2678 return -ENOMEM;
2679 }
2680
2681 for (i = 0; i < hdev->num_msi; i++)
2682 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2683
2684 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2685 sizeof(int), GFP_KERNEL);
2686 if (!hdev->vector_irq) {
2687 devm_kfree(&pdev->dev, hdev->vector_status);
2688 pci_free_irq_vectors(pdev);
2689 return -ENOMEM;
2690 }
2691
2692 return 0;
2693}
2694
2695static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2696{
2697 struct pci_dev *pdev = hdev->pdev;
2698
2699 devm_kfree(&pdev->dev, hdev->vector_status);
2700 devm_kfree(&pdev->dev, hdev->vector_irq);
2701 pci_free_irq_vectors(pdev);
2702}
2703
2704static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2705{
2706 int ret;
2707
2708 hclgevf_get_misc_vector(hdev);
2709
2710 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2711 HCLGEVF_NAME, pci_name(hdev->pdev));
2712 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2713 0, hdev->misc_vector.name, hdev);
2714 if (ret) {
2715 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2716 hdev->misc_vector.vector_irq);
2717 return ret;
2718 }
2719
2720 hclgevf_clear_event_cause(hdev, 0);
2721
2722
2723 hclgevf_enable_vector(&hdev->misc_vector, true);
2724
2725 return ret;
2726}
2727
2728static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2729{
2730
2731 hclgevf_enable_vector(&hdev->misc_vector, false);
2732 synchronize_irq(hdev->misc_vector.vector_irq);
2733 free_irq(hdev->misc_vector.vector_irq, hdev);
2734 hclgevf_free_vector(hdev, 0);
2735}
2736
2737static void hclgevf_info_show(struct hclgevf_dev *hdev)
2738{
2739 struct device *dev = &hdev->pdev->dev;
2740
2741 dev_info(dev, "VF info begin:\n");
2742
2743 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2744 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2745 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2746 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2747 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2748 dev_info(dev, "PF media type of this VF: %u\n",
2749 hdev->hw.mac.media_type);
2750
2751 dev_info(dev, "VF info end.\n");
2752}
2753
2754static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2755 struct hnae3_client *client)
2756{
2757 struct hclgevf_dev *hdev = ae_dev->priv;
2758 int rst_cnt = hdev->rst_stats.rst_cnt;
2759 int ret;
2760
2761 ret = client->ops->init_instance(&hdev->nic);
2762 if (ret)
2763 return ret;
2764
2765 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2766 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2767 rst_cnt != hdev->rst_stats.rst_cnt) {
2768 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2769
2770 client->ops->uninit_instance(&hdev->nic, 0);
2771 return -EBUSY;
2772 }
2773
2774 hnae3_set_client_init_flag(client, ae_dev, 1);
2775
2776 if (netif_msg_drv(&hdev->nic))
2777 hclgevf_info_show(hdev);
2778
2779 return 0;
2780}
2781
2782static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2783 struct hnae3_client *client)
2784{
2785 struct hclgevf_dev *hdev = ae_dev->priv;
2786 int ret;
2787
2788 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2789 !hdev->nic_client)
2790 return 0;
2791
2792 ret = hclgevf_init_roce_base_info(hdev);
2793 if (ret)
2794 return ret;
2795
2796 ret = client->ops->init_instance(&hdev->roce);
2797 if (ret)
2798 return ret;
2799
2800 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2801 hnae3_set_client_init_flag(client, ae_dev, 1);
2802
2803 return 0;
2804}
2805
2806static int hclgevf_init_client_instance(struct hnae3_client *client,
2807 struct hnae3_ae_dev *ae_dev)
2808{
2809 struct hclgevf_dev *hdev = ae_dev->priv;
2810 int ret;
2811
2812 switch (client->type) {
2813 case HNAE3_CLIENT_KNIC:
2814 hdev->nic_client = client;
2815 hdev->nic.client = client;
2816
2817 ret = hclgevf_init_nic_client_instance(ae_dev, client);
2818 if (ret)
2819 goto clear_nic;
2820
2821 ret = hclgevf_init_roce_client_instance(ae_dev,
2822 hdev->roce_client);
2823 if (ret)
2824 goto clear_roce;
2825
2826 break;
2827 case HNAE3_CLIENT_ROCE:
2828 if (hnae3_dev_roce_supported(hdev)) {
2829 hdev->roce_client = client;
2830 hdev->roce.client = client;
2831 }
2832
2833 ret = hclgevf_init_roce_client_instance(ae_dev, client);
2834 if (ret)
2835 goto clear_roce;
2836
2837 break;
2838 default:
2839 return -EINVAL;
2840 }
2841
2842 return 0;
2843
2844clear_nic:
2845 hdev->nic_client = NULL;
2846 hdev->nic.client = NULL;
2847 return ret;
2848clear_roce:
2849 hdev->roce_client = NULL;
2850 hdev->roce.client = NULL;
2851 return ret;
2852}
2853
2854static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2855 struct hnae3_ae_dev *ae_dev)
2856{
2857 struct hclgevf_dev *hdev = ae_dev->priv;
2858
2859
2860 if (hdev->roce_client) {
2861 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2862 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
2863 hdev->roce_client = NULL;
2864 hdev->roce.client = NULL;
2865 }
2866
2867
2868 if (client->ops->uninit_instance && hdev->nic_client &&
2869 client->type != HNAE3_CLIENT_ROCE) {
2870 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2871
2872 client->ops->uninit_instance(&hdev->nic, 0);
2873 hdev->nic_client = NULL;
2874 hdev->nic.client = NULL;
2875 }
2876}
2877
2878static int hclgevf_pci_init(struct hclgevf_dev *hdev)
2879{
2880 struct pci_dev *pdev = hdev->pdev;
2881 struct hclgevf_hw *hw;
2882 int ret;
2883
2884 ret = pci_enable_device(pdev);
2885 if (ret) {
2886 dev_err(&pdev->dev, "failed to enable PCI device\n");
2887 return ret;
2888 }
2889
2890 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2891 if (ret) {
2892 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
2893 goto err_disable_device;
2894 }
2895
2896 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
2897 if (ret) {
2898 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
2899 goto err_disable_device;
2900 }
2901
2902 pci_set_master(pdev);
2903 hw = &hdev->hw;
2904 hw->hdev = hdev;
2905 hw->io_base = pci_iomap(pdev, 2, 0);
2906 if (!hw->io_base) {
2907 dev_err(&pdev->dev, "can't map configuration register space\n");
2908 ret = -ENOMEM;
2909 goto err_clr_master;
2910 }
2911
2912 return 0;
2913
2914err_clr_master:
2915 pci_clear_master(pdev);
2916 pci_release_regions(pdev);
2917err_disable_device:
2918 pci_disable_device(pdev);
2919
2920 return ret;
2921}
2922
2923static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
2924{
2925 struct pci_dev *pdev = hdev->pdev;
2926
2927 pci_iounmap(pdev, hdev->hw.io_base);
2928 pci_clear_master(pdev);
2929 pci_release_regions(pdev);
2930 pci_disable_device(pdev);
2931}
2932
2933static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
2934{
2935 struct hclgevf_query_res_cmd *req;
2936 struct hclgevf_desc desc;
2937 int ret;
2938
2939 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
2940 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2941 if (ret) {
2942 dev_err(&hdev->pdev->dev,
2943 "query vf resource failed, ret = %d.\n", ret);
2944 return ret;
2945 }
2946
2947 req = (struct hclgevf_query_res_cmd *)desc.data;
2948
2949 if (hnae3_dev_roce_supported(hdev)) {
2950 hdev->roce_base_msix_offset =
2951 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
2952 HCLGEVF_MSIX_OFT_ROCEE_M,
2953 HCLGEVF_MSIX_OFT_ROCEE_S);
2954 hdev->num_roce_msix =
2955 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2956 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2957
2958
2959 hdev->num_nic_msix = hdev->num_roce_msix;
2960
2961
2962
2963
2964 hdev->num_msi = hdev->num_roce_msix +
2965 hdev->roce_base_msix_offset;
2966 } else {
2967 hdev->num_msi =
2968 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2969 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2970
2971 hdev->num_nic_msix = hdev->num_msi;
2972 }
2973
2974 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
2975 dev_err(&hdev->pdev->dev,
2976 "Just %u msi resources, not enough for vf(min:2).\n",
2977 hdev->num_nic_msix);
2978 return -EINVAL;
2979 }
2980
2981 return 0;
2982}
2983
2984static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
2985{
2986#define HCLGEVF_MAX_NON_TSO_BD_NUM 8U
2987
2988 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2989
2990 ae_dev->dev_specs.max_non_tso_bd_num =
2991 HCLGEVF_MAX_NON_TSO_BD_NUM;
2992 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
2993 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
2994}
2995
2996static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
2997 struct hclgevf_desc *desc)
2998{
2999 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3000 struct hclgevf_dev_specs_0_cmd *req0;
3001
3002 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
3003
3004 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
3005 ae_dev->dev_specs.rss_ind_tbl_size =
3006 le16_to_cpu(req0->rss_ind_tbl_size);
3007 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
3008}
3009
3010static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
3011{
3012 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
3013
3014 if (!dev_specs->max_non_tso_bd_num)
3015 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;
3016 if (!dev_specs->rss_ind_tbl_size)
3017 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3018 if (!dev_specs->rss_key_size)
3019 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3020}
3021
3022static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
3023{
3024 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
3025 int ret;
3026 int i;
3027
3028
3029
3030
3031 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
3032 hclgevf_set_default_dev_specs(hdev);
3033 return 0;
3034 }
3035
3036 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3037 hclgevf_cmd_setup_basic_desc(&desc[i],
3038 HCLGEVF_OPC_QUERY_DEV_SPECS, true);
3039 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT);
3040 }
3041 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS,
3042 true);
3043
3044 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
3045 if (ret)
3046 return ret;
3047
3048 hclgevf_parse_dev_specs(hdev, desc);
3049 hclgevf_check_dev_specs(hdev);
3050
3051 return 0;
3052}
3053
3054static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
3055{
3056 struct pci_dev *pdev = hdev->pdev;
3057 int ret = 0;
3058
3059 if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
3060 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3061 hclgevf_misc_irq_uninit(hdev);
3062 hclgevf_uninit_msi(hdev);
3063 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3064 }
3065
3066 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3067 pci_set_master(pdev);
3068 ret = hclgevf_init_msi(hdev);
3069 if (ret) {
3070 dev_err(&pdev->dev,
3071 "failed(%d) to init MSI/MSI-X\n", ret);
3072 return ret;
3073 }
3074
3075 ret = hclgevf_misc_irq_init(hdev);
3076 if (ret) {
3077 hclgevf_uninit_msi(hdev);
3078 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
3079 ret);
3080 return ret;
3081 }
3082
3083 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3084 }
3085
3086 return ret;
3087}
3088
3089static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
3090{
3091 struct hclge_vf_to_pf_msg send_msg;
3092
3093 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
3094 HCLGE_MBX_VPORT_LIST_CLEAR);
3095 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3096}
3097
3098static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
3099{
3100 struct pci_dev *pdev = hdev->pdev;
3101 int ret;
3102
3103 ret = hclgevf_pci_reset(hdev);
3104 if (ret) {
3105 dev_err(&pdev->dev, "pci reset failed %d\n", ret);
3106 return ret;
3107 }
3108
3109 ret = hclgevf_cmd_init(hdev);
3110 if (ret) {
3111 dev_err(&pdev->dev, "cmd failed %d\n", ret);
3112 return ret;
3113 }
3114
3115 ret = hclgevf_rss_init_hw(hdev);
3116 if (ret) {
3117 dev_err(&hdev->pdev->dev,
3118 "failed(%d) to initialize RSS\n", ret);
3119 return ret;
3120 }
3121
3122 ret = hclgevf_config_gro(hdev, true);
3123 if (ret)
3124 return ret;
3125
3126 ret = hclgevf_init_vlan_config(hdev);
3127 if (ret) {
3128 dev_err(&hdev->pdev->dev,
3129 "failed(%d) to initialize VLAN config\n", ret);
3130 return ret;
3131 }
3132
3133 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
3134
3135 dev_info(&hdev->pdev->dev, "Reset done\n");
3136
3137 return 0;
3138}
3139
3140static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
3141{
3142 struct pci_dev *pdev = hdev->pdev;
3143 int ret;
3144
3145 ret = hclgevf_pci_init(hdev);
3146 if (ret)
3147 return ret;
3148
3149 ret = hclgevf_cmd_queue_init(hdev);
3150 if (ret)
3151 goto err_cmd_queue_init;
3152
3153 ret = hclgevf_cmd_init(hdev);
3154 if (ret)
3155 goto err_cmd_init;
3156
3157
3158 ret = hclgevf_query_vf_resource(hdev);
3159 if (ret)
3160 goto err_cmd_init;
3161
3162 ret = hclgevf_query_dev_specs(hdev);
3163 if (ret) {
3164 dev_err(&pdev->dev,
3165 "failed to query dev specifications, ret = %d\n", ret);
3166 goto err_cmd_init;
3167 }
3168
3169 ret = hclgevf_init_msi(hdev);
3170 if (ret) {
3171 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
3172 goto err_cmd_init;
3173 }
3174
3175 hclgevf_state_init(hdev);
3176 hdev->reset_level = HNAE3_VF_FUNC_RESET;
3177 hdev->reset_type = HNAE3_NONE_RESET;
3178
3179 ret = hclgevf_misc_irq_init(hdev);
3180 if (ret)
3181 goto err_misc_irq_init;
3182
3183 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3184
3185 ret = hclgevf_configure(hdev);
3186 if (ret) {
3187 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
3188 goto err_config;
3189 }
3190
3191 ret = hclgevf_alloc_tqps(hdev);
3192 if (ret) {
3193 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
3194 goto err_config;
3195 }
3196
3197 ret = hclgevf_set_handle_info(hdev);
3198 if (ret)
3199 goto err_config;
3200
3201 ret = hclgevf_config_gro(hdev, true);
3202 if (ret)
3203 goto err_config;
3204
3205
3206 hclgevf_rss_init_cfg(hdev);
3207 ret = hclgevf_rss_init_hw(hdev);
3208 if (ret) {
3209 dev_err(&hdev->pdev->dev,
3210 "failed(%d) to initialize RSS\n", ret);
3211 goto err_config;
3212 }
3213
3214
3215 ret = hclgevf_clear_vport_list(hdev);
3216 if (ret) {
3217 dev_err(&pdev->dev,
3218 "failed to clear tbl list configuration, ret = %d.\n",
3219 ret);
3220 goto err_config;
3221 }
3222
3223 ret = hclgevf_init_vlan_config(hdev);
3224 if (ret) {
3225 dev_err(&hdev->pdev->dev,
3226 "failed(%d) to initialize VLAN config\n", ret);
3227 goto err_config;
3228 }
3229
3230 hdev->last_reset_time = jiffies;
3231 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
3232 HCLGEVF_DRIVER_NAME);
3233
3234 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
3235
3236 return 0;
3237
3238err_config:
3239 hclgevf_misc_irq_uninit(hdev);
3240err_misc_irq_init:
3241 hclgevf_state_uninit(hdev);
3242 hclgevf_uninit_msi(hdev);
3243err_cmd_init:
3244 hclgevf_cmd_uninit(hdev);
3245err_cmd_queue_init:
3246 hclgevf_pci_uninit(hdev);
3247 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3248 return ret;
3249}
3250
3251static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
3252{
3253 struct hclge_vf_to_pf_msg send_msg;
3254
3255 hclgevf_state_uninit(hdev);
3256
3257 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
3258 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3259
3260 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3261 hclgevf_misc_irq_uninit(hdev);
3262 hclgevf_uninit_msi(hdev);
3263 }
3264
3265 hclgevf_cmd_uninit(hdev);
3266 hclgevf_pci_uninit(hdev);
3267 hclgevf_uninit_mac_list(hdev);
3268}
3269
3270static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
3271{
3272 struct pci_dev *pdev = ae_dev->pdev;
3273 int ret;
3274
3275 ret = hclgevf_alloc_hdev(ae_dev);
3276 if (ret) {
3277 dev_err(&pdev->dev, "hclge device allocation failed\n");
3278 return ret;
3279 }
3280
3281 ret = hclgevf_init_hdev(ae_dev->priv);
3282 if (ret) {
3283 dev_err(&pdev->dev, "hclge device initialization failed\n");
3284 return ret;
3285 }
3286
3287 return 0;
3288}
3289
3290static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3291{
3292 struct hclgevf_dev *hdev = ae_dev->priv;
3293
3294 hclgevf_uninit_hdev(hdev);
3295 ae_dev->priv = NULL;
3296}
3297
3298static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3299{
3300 struct hnae3_handle *nic = &hdev->nic;
3301 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3302
3303 return min_t(u32, hdev->rss_size_max,
3304 hdev->num_tqps / kinfo->num_tc);
3305}
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317static void hclgevf_get_channels(struct hnae3_handle *handle,
3318 struct ethtool_channels *ch)
3319{
3320 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3321
3322 ch->max_combined = hclgevf_get_max_channels(hdev);
3323 ch->other_count = 0;
3324 ch->max_other = 0;
3325 ch->combined_count = handle->kinfo.rss_size;
3326}
3327
3328static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3329 u16 *alloc_tqps, u16 *max_rss_size)
3330{
3331 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3332
3333 *alloc_tqps = hdev->num_tqps;
3334 *max_rss_size = hdev->rss_size_max;
3335}
3336
3337static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3338 u32 new_tqps_num)
3339{
3340 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3341 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3342 u16 max_rss_size;
3343
3344 kinfo->req_rss_size = new_tqps_num;
3345
3346 max_rss_size = min_t(u16, hdev->rss_size_max,
3347 hdev->num_tqps / kinfo->num_tc);
3348
3349
3350
3351
3352 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3353 kinfo->req_rss_size <= max_rss_size)
3354 kinfo->rss_size = kinfo->req_rss_size;
3355 else if (kinfo->rss_size > max_rss_size ||
3356 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3357 kinfo->rss_size = max_rss_size;
3358
3359 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size;
3360}
3361
3362static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3363 bool rxfh_configured)
3364{
3365 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3366 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3367 u16 cur_rss_size = kinfo->rss_size;
3368 u16 cur_tqps = kinfo->num_tqps;
3369 u32 *rss_indir;
3370 unsigned int i;
3371 int ret;
3372
3373 hclgevf_update_rss_size(handle, new_tqps_num);
3374
3375 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size);
3376 if (ret)
3377 return ret;
3378
3379
3380 if (rxfh_configured)
3381 goto out;
3382
3383
3384 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3385 if (!rss_indir)
3386 return -ENOMEM;
3387
3388 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
3389 rss_indir[i] = i % kinfo->rss_size;
3390
3391 hdev->rss_cfg.rss_size = kinfo->rss_size;
3392
3393 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3394 if (ret)
3395 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3396 ret);
3397
3398 kfree(rss_indir);
3399
3400out:
3401 if (!ret)
3402 dev_info(&hdev->pdev->dev,
3403 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3404 cur_rss_size, kinfo->rss_size,
3405 cur_tqps, kinfo->rss_size * kinfo->num_tc);
3406
3407 return ret;
3408}
3409
3410static int hclgevf_get_status(struct hnae3_handle *handle)
3411{
3412 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3413
3414 return hdev->hw.mac.link;
3415}
3416
3417static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3418 u8 *auto_neg, u32 *speed,
3419 u8 *duplex)
3420{
3421 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3422
3423 if (speed)
3424 *speed = hdev->hw.mac.speed;
3425 if (duplex)
3426 *duplex = hdev->hw.mac.duplex;
3427 if (auto_neg)
3428 *auto_neg = AUTONEG_DISABLE;
3429}
3430
3431void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3432 u8 duplex)
3433{
3434 hdev->hw.mac.speed = speed;
3435 hdev->hw.mac.duplex = duplex;
3436}
3437
3438static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3439{
3440 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3441
3442 return hclgevf_config_gro(hdev, enable);
3443}
3444
3445static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3446 u8 *module_type)
3447{
3448 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3449
3450 if (media_type)
3451 *media_type = hdev->hw.mac.media_type;
3452
3453 if (module_type)
3454 *module_type = hdev->hw.mac.module_type;
3455}
3456
3457static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3458{
3459 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3460
3461 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3462}
3463
3464static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)
3465{
3466 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3467
3468 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
3469}
3470
3471static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3472{
3473 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3474
3475 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3476}
3477
3478static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3479{
3480 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3481
3482 return hdev->rst_stats.hw_rst_done_cnt;
3483}
3484
3485static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3486 unsigned long *supported,
3487 unsigned long *advertising)
3488{
3489 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3490
3491 *supported = hdev->hw.mac.supported;
3492 *advertising = hdev->hw.mac.advertising;
3493}
3494
3495#define MAX_SEPARATE_NUM 4
3496#define SEPARATOR_VALUE 0xFFFFFFFF
3497#define REG_NUM_PER_LINE 4
3498#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
3499
3500static int hclgevf_get_regs_len(struct hnae3_handle *handle)
3501{
3502 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
3503 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3504
3505 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
3506 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
3507 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
3508 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
3509
3510 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
3511 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
3512}
3513
3514static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
3515 void *data)
3516{
3517 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3518 int i, j, reg_um, separator_num;
3519 u32 *reg = data;
3520
3521 *version = hdev->fw_version;
3522
3523
3524 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
3525 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3526 for (i = 0; i < reg_um; i++)
3527 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
3528 for (i = 0; i < separator_num; i++)
3529 *reg++ = SEPARATOR_VALUE;
3530
3531 reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
3532 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3533 for (i = 0; i < reg_um; i++)
3534 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
3535 for (i = 0; i < separator_num; i++)
3536 *reg++ = SEPARATOR_VALUE;
3537
3538 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
3539 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3540 for (j = 0; j < hdev->num_tqps; j++) {
3541 for (i = 0; i < reg_um; i++)
3542 *reg++ = hclgevf_read_dev(&hdev->hw,
3543 ring_reg_addr_list[i] +
3544 0x200 * j);
3545 for (i = 0; i < separator_num; i++)
3546 *reg++ = SEPARATOR_VALUE;
3547 }
3548
3549 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
3550 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3551 for (j = 0; j < hdev->num_msi_used - 1; j++) {
3552 for (i = 0; i < reg_um; i++)
3553 *reg++ = hclgevf_read_dev(&hdev->hw,
3554 tqp_intr_reg_addr_list[i] +
3555 4 * j);
3556 for (i = 0; i < separator_num; i++)
3557 *reg++ = SEPARATOR_VALUE;
3558 }
3559}
3560
3561void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3562 u8 *port_base_vlan_info, u8 data_size)
3563{
3564 struct hnae3_handle *nic = &hdev->nic;
3565 struct hclge_vf_to_pf_msg send_msg;
3566 int ret;
3567
3568 rtnl_lock();
3569
3570 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3571 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3572 dev_warn(&hdev->pdev->dev,
3573 "is resetting when updating port based vlan info\n");
3574 rtnl_unlock();
3575 return;
3576 }
3577
3578 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3579 if (ret) {
3580 rtnl_unlock();
3581 return;
3582 }
3583
3584
3585 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3586 HCLGE_MBX_PORT_BASE_VLAN_CFG);
3587 memcpy(send_msg.data, port_base_vlan_info, data_size);
3588 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3589 if (!ret) {
3590 if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3591 nic->port_base_vlan_state = state;
3592 else
3593 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3594 }
3595
3596 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3597 rtnl_unlock();
3598}
3599
3600static const struct hnae3_ae_ops hclgevf_ops = {
3601 .init_ae_dev = hclgevf_init_ae_dev,
3602 .uninit_ae_dev = hclgevf_uninit_ae_dev,
3603 .flr_prepare = hclgevf_flr_prepare,
3604 .flr_done = hclgevf_flr_done,
3605 .init_client_instance = hclgevf_init_client_instance,
3606 .uninit_client_instance = hclgevf_uninit_client_instance,
3607 .start = hclgevf_ae_start,
3608 .stop = hclgevf_ae_stop,
3609 .client_start = hclgevf_client_start,
3610 .client_stop = hclgevf_client_stop,
3611 .map_ring_to_vector = hclgevf_map_ring_to_vector,
3612 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3613 .get_vector = hclgevf_get_vector,
3614 .put_vector = hclgevf_put_vector,
3615 .reset_queue = hclgevf_reset_tqp,
3616 .get_mac_addr = hclgevf_get_mac_addr,
3617 .set_mac_addr = hclgevf_set_mac_addr,
3618 .add_uc_addr = hclgevf_add_uc_addr,
3619 .rm_uc_addr = hclgevf_rm_uc_addr,
3620 .add_mc_addr = hclgevf_add_mc_addr,
3621 .rm_mc_addr = hclgevf_rm_mc_addr,
3622 .get_stats = hclgevf_get_stats,
3623 .update_stats = hclgevf_update_stats,
3624 .get_strings = hclgevf_get_strings,
3625 .get_sset_count = hclgevf_get_sset_count,
3626 .get_rss_key_size = hclgevf_get_rss_key_size,
3627 .get_rss_indir_size = hclgevf_get_rss_indir_size,
3628 .get_rss = hclgevf_get_rss,
3629 .set_rss = hclgevf_set_rss,
3630 .get_rss_tuple = hclgevf_get_rss_tuple,
3631 .set_rss_tuple = hclgevf_set_rss_tuple,
3632 .get_tc_size = hclgevf_get_tc_size,
3633 .get_fw_version = hclgevf_get_fw_version,
3634 .set_vlan_filter = hclgevf_set_vlan_filter,
3635 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3636 .reset_event = hclgevf_reset_event,
3637 .set_default_reset_request = hclgevf_set_def_reset_request,
3638 .set_channels = hclgevf_set_channels,
3639 .get_channels = hclgevf_get_channels,
3640 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3641 .get_regs_len = hclgevf_get_regs_len,
3642 .get_regs = hclgevf_get_regs,
3643 .get_status = hclgevf_get_status,
3644 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3645 .get_media_type = hclgevf_get_media_type,
3646 .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3647 .ae_dev_resetting = hclgevf_ae_dev_resetting,
3648 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3649 .set_gro_en = hclgevf_gro_en,
3650 .set_mtu = hclgevf_set_mtu,
3651 .get_global_queue_id = hclgevf_get_qid_global,
3652 .set_timer_task = hclgevf_set_timer_task,
3653 .get_link_mode = hclgevf_get_link_mode,
3654 .set_promisc_mode = hclgevf_set_promisc_mode,
3655 .request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3656 .get_cmdq_stat = hclgevf_get_cmdq_stat,
3657};
3658
3659static struct hnae3_ae_algo ae_algovf = {
3660 .ops = &hclgevf_ops,
3661 .pdev_id_table = ae_algovf_pci_tbl,
3662};
3663
3664static int hclgevf_init(void)
3665{
3666 pr_info("%s is initializing\n", HCLGEVF_NAME);
3667
3668 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME);
3669 if (!hclgevf_wq) {
3670 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3671 return -ENOMEM;
3672 }
3673
3674 hnae3_register_ae_algo(&ae_algovf);
3675
3676 return 0;
3677}
3678
3679static void hclgevf_exit(void)
3680{
3681 hnae3_unregister_ae_algo(&ae_algovf);
3682 destroy_workqueue(hclgevf_wq);
3683}
3684module_init(hclgevf_init);
3685module_exit(hclgevf_exit);
3686
3687MODULE_LICENSE("GPL");
3688MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3689MODULE_DESCRIPTION("HCLGEVF Driver");
3690MODULE_VERSION(HCLGEVF_MOD_VERSION);
3691