1
2
3
4#include "ice_sched.h"
5
6
7
8
9
10
11
12
13
14static enum ice_status
15ice_sched_add_root_node(struct ice_port_info *pi,
16 struct ice_aqc_txsched_elem_data *info)
17{
18 struct ice_sched_node *root;
19 struct ice_hw *hw;
20
21 if (!pi)
22 return ICE_ERR_PARAM;
23
24 hw = pi->hw;
25
26 root = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*root), GFP_KERNEL);
27 if (!root)
28 return ICE_ERR_NO_MEMORY;
29
30
31 root->children = devm_kcalloc(ice_hw_to_dev(hw), hw->max_children[0],
32 sizeof(*root), GFP_KERNEL);
33 if (!root->children) {
34 devm_kfree(ice_hw_to_dev(hw), root);
35 return ICE_ERR_NO_MEMORY;
36 }
37
38 memcpy(&root->info, info, sizeof(*info));
39 pi->root = root;
40 return 0;
41}
42
43
44
45
46
47
48
49
50
51
52
53
54struct ice_sched_node *
55ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid)
56{
57 u16 i;
58
59
60 if (ICE_TXSCHED_GET_NODE_TEID(start_node) == teid)
61 return start_node;
62
63
64 if (!start_node->num_children ||
65 start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM ||
66 start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF)
67 return NULL;
68
69
70 for (i = 0; i < start_node->num_children; i++)
71 if (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid)
72 return start_node->children[i];
73
74
75 for (i = 0; i < start_node->num_children; i++) {
76 struct ice_sched_node *tmp;
77
78 tmp = ice_sched_find_node_by_teid(start_node->children[i],
79 teid);
80 if (tmp)
81 return tmp;
82 }
83
84 return NULL;
85}
86
87
88
89
90
91
92
93
94
95
96
97
98
99static enum ice_status
100ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc,
101 u16 elems_req, void *buf, u16 buf_size,
102 u16 *elems_resp, struct ice_sq_cd *cd)
103{
104 struct ice_aqc_sched_elem_cmd *cmd;
105 struct ice_aq_desc desc;
106 enum ice_status status;
107
108 cmd = &desc.params.sched_elem_cmd;
109 ice_fill_dflt_direct_cmd_desc(&desc, cmd_opc);
110 cmd->num_elem_req = cpu_to_le16(elems_req);
111 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
113 if (!status && elems_resp)
114 *elems_resp = le16_to_cpu(cmd->num_elem_resp);
115
116 return status;
117}
118
119
120
121
122
123
124
125
126
127
128
129
130enum ice_status
131ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
132 struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
133 u16 *elems_ret, struct ice_sq_cd *cd)
134{
135 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_get_sched_elems,
136 elems_req, (void *)buf, buf_size,
137 elems_ret, cd);
138}
139
140
141
142
143
144
145
146
147
148enum ice_status
149ice_sched_add_node(struct ice_port_info *pi, u8 layer,
150 struct ice_aqc_txsched_elem_data *info)
151{
152 struct ice_aqc_txsched_elem_data elem;
153 struct ice_sched_node *parent;
154 struct ice_sched_node *node;
155 enum ice_status status;
156 struct ice_hw *hw;
157
158 if (!pi)
159 return ICE_ERR_PARAM;
160
161 hw = pi->hw;
162
163
164 parent = ice_sched_find_node_by_teid(pi->root,
165 le32_to_cpu(info->parent_teid));
166 if (!parent) {
167 ice_debug(hw, ICE_DBG_SCHED,
168 "Parent Node not found for parent_teid=0x%x\n",
169 le32_to_cpu(info->parent_teid));
170 return ICE_ERR_PARAM;
171 }
172
173
174
175
176 status = ice_sched_query_elem(hw, le32_to_cpu(info->node_teid), &elem);
177 if (status)
178 return status;
179
180 node = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*node), GFP_KERNEL);
181 if (!node)
182 return ICE_ERR_NO_MEMORY;
183 if (hw->max_children[layer]) {
184
185 node->children = devm_kcalloc(ice_hw_to_dev(hw),
186 hw->max_children[layer],
187 sizeof(*node), GFP_KERNEL);
188 if (!node->children) {
189 devm_kfree(ice_hw_to_dev(hw), node);
190 return ICE_ERR_NO_MEMORY;
191 }
192 }
193
194 node->in_use = true;
195 node->parent = parent;
196 node->tx_sched_layer = layer;
197 parent->children[parent->num_children++] = node;
198 node->info = elem;
199 return 0;
200}
201
202
203
204
205
206
207
208
209
210
211
212
213static enum ice_status
214ice_aq_delete_sched_elems(struct ice_hw *hw, u16 grps_req,
215 struct ice_aqc_delete_elem *buf, u16 buf_size,
216 u16 *grps_del, struct ice_sq_cd *cd)
217{
218 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_delete_sched_elems,
219 grps_req, (void *)buf, buf_size,
220 grps_del, cd);
221}
222
223
224
225
226
227
228
229
230
231
232static enum ice_status
233ice_sched_remove_elems(struct ice_hw *hw, struct ice_sched_node *parent,
234 u16 num_nodes, u32 *node_teids)
235{
236 struct ice_aqc_delete_elem *buf;
237 u16 i, num_groups_removed = 0;
238 enum ice_status status;
239 u16 buf_size;
240
241 buf_size = struct_size(buf, teid, num_nodes);
242 buf = devm_kzalloc(ice_hw_to_dev(hw), buf_size, GFP_KERNEL);
243 if (!buf)
244 return ICE_ERR_NO_MEMORY;
245
246 buf->hdr.parent_teid = parent->info.node_teid;
247 buf->hdr.num_elems = cpu_to_le16(num_nodes);
248 for (i = 0; i < num_nodes; i++)
249 buf->teid[i] = cpu_to_le32(node_teids[i]);
250
251 status = ice_aq_delete_sched_elems(hw, 1, buf, buf_size,
252 &num_groups_removed, NULL);
253 if (status || num_groups_removed != 1)
254 ice_debug(hw, ICE_DBG_SCHED, "remove node failed FW error %d\n",
255 hw->adminq.sq_last_status);
256
257 devm_kfree(ice_hw_to_dev(hw), buf);
258 return status;
259}
260
261
262
263
264
265
266
267
268
269static struct ice_sched_node *
270ice_sched_get_first_node(struct ice_port_info *pi,
271 struct ice_sched_node *parent, u8 layer)
272{
273 return pi->sib_head[parent->tc_num][layer];
274}
275
276
277
278
279
280
281
282
283struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)
284{
285 u8 i;
286
287 if (!pi || !pi->root)
288 return NULL;
289 for (i = 0; i < pi->root->num_children; i++)
290 if (pi->root->children[i]->tc_num == tc)
291 return pi->root->children[i];
292 return NULL;
293}
294
295
296
297
298
299
300
301
302
303
304void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node)
305{
306 struct ice_sched_node *parent;
307 struct ice_hw *hw = pi->hw;
308 u8 i, j;
309
310
311
312
313
314 while (node->num_children)
315 ice_free_sched_node(pi, node->children[0]);
316
317
318 if (node->tx_sched_layer >= hw->sw_entry_point_layer &&
319 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&
320 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT &&
321 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) {
322 u32 teid = le32_to_cpu(node->info.node_teid);
323
324 ice_sched_remove_elems(hw, node->parent, 1, &teid);
325 }
326 parent = node->parent;
327
328 if (parent) {
329 struct ice_sched_node *p;
330
331
332 for (i = 0; i < parent->num_children; i++)
333 if (parent->children[i] == node) {
334 for (j = i + 1; j < parent->num_children; j++)
335 parent->children[j - 1] =
336 parent->children[j];
337 parent->num_children--;
338 break;
339 }
340
341 p = ice_sched_get_first_node(pi, node, node->tx_sched_layer);
342 while (p) {
343 if (p->sibling == node) {
344 p->sibling = node->sibling;
345 break;
346 }
347 p = p->sibling;
348 }
349
350
351 if (pi->sib_head[node->tc_num][node->tx_sched_layer] == node)
352 pi->sib_head[node->tc_num][node->tx_sched_layer] =
353 node->sibling;
354 }
355
356
357 if (node->children)
358 devm_kfree(ice_hw_to_dev(hw), node->children);
359 devm_kfree(ice_hw_to_dev(hw), node);
360}
361
362
363
364
365
366
367
368
369
370
371
372
373static enum ice_status
374ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport,
375 struct ice_aqc_get_topo_elem *buf, u16 buf_size,
376 u8 *num_branches, struct ice_sq_cd *cd)
377{
378 struct ice_aqc_get_topo *cmd;
379 struct ice_aq_desc desc;
380 enum ice_status status;
381
382 cmd = &desc.params.get_topo;
383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo);
384 cmd->port_num = lport;
385 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
386 if (!status && num_branches)
387 *num_branches = cmd->num_branches;
388
389 return status;
390}
391
392
393
394
395
396
397
398
399
400
401
402
403static enum ice_status
404ice_aq_add_sched_elems(struct ice_hw *hw, u16 grps_req,
405 struct ice_aqc_add_elem *buf, u16 buf_size,
406 u16 *grps_added, struct ice_sq_cd *cd)
407{
408 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_add_sched_elems,
409 grps_req, (void *)buf, buf_size,
410 grps_added, cd);
411}
412
413
414
415
416
417
418
419
420
421
422
423
424static enum ice_status
425ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req,
426 struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
427 u16 *elems_cfgd, struct ice_sq_cd *cd)
428{
429 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_cfg_sched_elems,
430 elems_req, (void *)buf, buf_size,
431 elems_cfgd, cd);
432}
433
434
435
436
437
438
439
440
441
442
443
444
445static enum ice_status
446ice_aq_suspend_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf,
447 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd)
448{
449 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_suspend_sched_elems,
450 elems_req, (void *)buf, buf_size,
451 elems_ret, cd);
452}
453
454
455
456
457
458
459
460
461
462
463
464
465static enum ice_status
466ice_aq_resume_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf,
467 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd)
468{
469 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_resume_sched_elems,
470 elems_req, (void *)buf, buf_size,
471 elems_ret, cd);
472}
473
474
475
476
477
478
479
480
481
482
483static enum ice_status
484ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size,
485 struct ice_aqc_query_txsched_res_resp *buf,
486 struct ice_sq_cd *cd)
487{
488 struct ice_aq_desc desc;
489
490 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res);
491 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
492}
493
494
495
496
497
498
499
500
501
502
503static enum ice_status
504ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids,
505 bool suspend)
506{
507 u16 i, buf_size, num_elem_ret = 0;
508 enum ice_status status;
509 __le32 *buf;
510
511 buf_size = sizeof(*buf) * num_nodes;
512 buf = devm_kzalloc(ice_hw_to_dev(hw), buf_size, GFP_KERNEL);
513 if (!buf)
514 return ICE_ERR_NO_MEMORY;
515
516 for (i = 0; i < num_nodes; i++)
517 buf[i] = cpu_to_le32(node_teids[i]);
518
519 if (suspend)
520 status = ice_aq_suspend_sched_elems(hw, num_nodes, buf,
521 buf_size, &num_elem_ret,
522 NULL);
523 else
524 status = ice_aq_resume_sched_elems(hw, num_nodes, buf,
525 buf_size, &num_elem_ret,
526 NULL);
527 if (status || num_elem_ret != num_nodes)
528 ice_debug(hw, ICE_DBG_SCHED, "suspend/resume failed\n");
529
530 devm_kfree(ice_hw_to_dev(hw), buf);
531 return status;
532}
533
534
535
536
537
538
539
540
541static enum ice_status
542ice_alloc_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 new_numqs)
543{
544 struct ice_vsi_ctx *vsi_ctx;
545 struct ice_q_ctx *q_ctx;
546
547 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);
548 if (!vsi_ctx)
549 return ICE_ERR_PARAM;
550
551 if (!vsi_ctx->lan_q_ctx[tc]) {
552 vsi_ctx->lan_q_ctx[tc] = devm_kcalloc(ice_hw_to_dev(hw),
553 new_numqs,
554 sizeof(*q_ctx),
555 GFP_KERNEL);
556 if (!vsi_ctx->lan_q_ctx[tc])
557 return ICE_ERR_NO_MEMORY;
558 vsi_ctx->num_lan_q_entries[tc] = new_numqs;
559 return 0;
560 }
561
562 if (new_numqs > vsi_ctx->num_lan_q_entries[tc]) {
563 u16 prev_num = vsi_ctx->num_lan_q_entries[tc];
564
565 q_ctx = devm_kcalloc(ice_hw_to_dev(hw), new_numqs,
566 sizeof(*q_ctx), GFP_KERNEL);
567 if (!q_ctx)
568 return ICE_ERR_NO_MEMORY;
569 memcpy(q_ctx, vsi_ctx->lan_q_ctx[tc],
570 prev_num * sizeof(*q_ctx));
571 devm_kfree(ice_hw_to_dev(hw), vsi_ctx->lan_q_ctx[tc]);
572 vsi_ctx->lan_q_ctx[tc] = q_ctx;
573 vsi_ctx->num_lan_q_entries[tc] = new_numqs;
574 }
575 return 0;
576}
577
578
579
580
581
582
583
584
585
586
587
588
589
590static enum ice_status
591ice_aq_rl_profile(struct ice_hw *hw, enum ice_adminq_opc opcode,
592 u16 num_profiles, struct ice_aqc_rl_profile_elem *buf,
593 u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd)
594{
595 struct ice_aqc_rl_profile *cmd;
596 struct ice_aq_desc desc;
597 enum ice_status status;
598
599 cmd = &desc.params.rl_profile;
600
601 ice_fill_dflt_direct_cmd_desc(&desc, opcode);
602 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
603 cmd->num_profiles = cpu_to_le16(num_profiles);
604 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
605 if (!status && num_processed)
606 *num_processed = le16_to_cpu(cmd->num_processed);
607 return status;
608}
609
610
611
612
613
614
615
616
617
618
619
620
621static enum ice_status
622ice_aq_add_rl_profile(struct ice_hw *hw, u16 num_profiles,
623 struct ice_aqc_rl_profile_elem *buf, u16 buf_size,
624 u16 *num_profiles_added, struct ice_sq_cd *cd)
625{
626 return ice_aq_rl_profile(hw, ice_aqc_opc_add_rl_profiles, num_profiles,
627 buf, buf_size, num_profiles_added, cd);
628}
629
630
631
632
633
634
635
636
637
638
639
640
641static enum ice_status
642ice_aq_remove_rl_profile(struct ice_hw *hw, u16 num_profiles,
643 struct ice_aqc_rl_profile_elem *buf, u16 buf_size,
644 u16 *num_profiles_removed, struct ice_sq_cd *cd)
645{
646 return ice_aq_rl_profile(hw, ice_aqc_opc_remove_rl_profiles,
647 num_profiles, buf, buf_size,
648 num_profiles_removed, cd);
649}
650
651
652
653
654
655
656
657
658
659
660static enum ice_status
661ice_sched_del_rl_profile(struct ice_hw *hw,
662 struct ice_aqc_rl_profile_info *rl_info)
663{
664 struct ice_aqc_rl_profile_elem *buf;
665 u16 num_profiles_removed;
666 enum ice_status status;
667 u16 num_profiles = 1;
668
669 if (rl_info->prof_id_ref != 0)
670 return ICE_ERR_IN_USE;
671
672
673 buf = &rl_info->profile;
674 status = ice_aq_remove_rl_profile(hw, num_profiles, buf, sizeof(*buf),
675 &num_profiles_removed, NULL);
676 if (status || num_profiles_removed != num_profiles)
677 return ICE_ERR_CFG;
678
679
680 list_del(&rl_info->list_entry);
681 devm_kfree(ice_hw_to_dev(hw), rl_info);
682 return status;
683}
684
685
686
687
688
689
690
691static void ice_sched_clear_rl_prof(struct ice_port_info *pi)
692{
693 u16 ln;
694
695 for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
696 struct ice_aqc_rl_profile_info *rl_prof_elem;
697 struct ice_aqc_rl_profile_info *rl_prof_tmp;
698
699 list_for_each_entry_safe(rl_prof_elem, rl_prof_tmp,
700 &pi->rl_prof_list[ln], list_entry) {
701 struct ice_hw *hw = pi->hw;
702 enum ice_status status;
703
704 rl_prof_elem->prof_id_ref = 0;
705 status = ice_sched_del_rl_profile(hw, rl_prof_elem);
706 if (status) {
707 ice_debug(hw, ICE_DBG_SCHED,
708 "Remove rl profile failed\n");
709
710 list_del(&rl_prof_elem->list_entry);
711 devm_kfree(ice_hw_to_dev(hw), rl_prof_elem);
712 }
713 }
714 }
715}
716
717
718
719
720
721
722
723
724void ice_sched_clear_agg(struct ice_hw *hw)
725{
726 struct ice_sched_agg_info *agg_info;
727 struct ice_sched_agg_info *atmp;
728
729 list_for_each_entry_safe(agg_info, atmp, &hw->agg_list, list_entry) {
730 struct ice_sched_agg_vsi_info *agg_vsi_info;
731 struct ice_sched_agg_vsi_info *vtmp;
732
733 list_for_each_entry_safe(agg_vsi_info, vtmp,
734 &agg_info->agg_vsi_list, list_entry) {
735 list_del(&agg_vsi_info->list_entry);
736 devm_kfree(ice_hw_to_dev(hw), agg_vsi_info);
737 }
738 list_del(&agg_info->list_entry);
739 devm_kfree(ice_hw_to_dev(hw), agg_info);
740 }
741}
742
743
744
745
746
747
748
749static void ice_sched_clear_tx_topo(struct ice_port_info *pi)
750{
751 if (!pi)
752 return;
753
754 ice_sched_clear_rl_prof(pi);
755 if (pi->root) {
756 ice_free_sched_node(pi, pi->root);
757 pi->root = NULL;
758 }
759}
760
761
762
763
764
765
766
767void ice_sched_clear_port(struct ice_port_info *pi)
768{
769 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
770 return;
771
772 pi->port_state = ICE_SCHED_PORT_STATE_INIT;
773 mutex_lock(&pi->sched_lock);
774 ice_sched_clear_tx_topo(pi);
775 mutex_unlock(&pi->sched_lock);
776 mutex_destroy(&pi->sched_lock);
777}
778
779
780
781
782
783
784
785void ice_sched_cleanup_all(struct ice_hw *hw)
786{
787 if (!hw)
788 return;
789
790 if (hw->layer_info) {
791 devm_kfree(ice_hw_to_dev(hw), hw->layer_info);
792 hw->layer_info = NULL;
793 }
794
795 ice_sched_clear_port(hw->port_info);
796
797 hw->num_tx_sched_layers = 0;
798 hw->num_tx_sched_phys_layers = 0;
799 hw->flattened_layers = 0;
800 hw->max_cgds = 0;
801}
802
803
804
805
806
807
808
809
810
811
812
813
814
815static enum ice_status
816ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,
817 struct ice_sched_node *parent, u8 layer, u16 num_nodes,
818 u16 *num_nodes_added, u32 *first_node_teid)
819{
820 struct ice_sched_node *prev, *new_node;
821 struct ice_aqc_add_elem *buf;
822 u16 i, num_groups_added = 0;
823 enum ice_status status = 0;
824 struct ice_hw *hw = pi->hw;
825 size_t buf_size;
826 u32 teid;
827
828 buf_size = struct_size(buf, generic, num_nodes);
829 buf = devm_kzalloc(ice_hw_to_dev(hw), buf_size, GFP_KERNEL);
830 if (!buf)
831 return ICE_ERR_NO_MEMORY;
832
833 buf->hdr.parent_teid = parent->info.node_teid;
834 buf->hdr.num_elems = cpu_to_le16(num_nodes);
835 for (i = 0; i < num_nodes; i++) {
836 buf->generic[i].parent_teid = parent->info.node_teid;
837 buf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC;
838 buf->generic[i].data.valid_sections =
839 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
840 ICE_AQC_ELEM_VALID_EIR;
841 buf->generic[i].data.generic = 0;
842 buf->generic[i].data.cir_bw.bw_profile_idx =
843 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
844 buf->generic[i].data.cir_bw.bw_alloc =
845 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
846 buf->generic[i].data.eir_bw.bw_profile_idx =
847 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
848 buf->generic[i].data.eir_bw.bw_alloc =
849 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
850 }
851
852 status = ice_aq_add_sched_elems(hw, 1, buf, buf_size,
853 &num_groups_added, NULL);
854 if (status || num_groups_added != 1) {
855 ice_debug(hw, ICE_DBG_SCHED, "add node failed FW Error %d\n",
856 hw->adminq.sq_last_status);
857 devm_kfree(ice_hw_to_dev(hw), buf);
858 return ICE_ERR_CFG;
859 }
860
861 *num_nodes_added = num_nodes;
862
863 for (i = 0; i < num_nodes; i++) {
864 status = ice_sched_add_node(pi, layer, &buf->generic[i]);
865 if (status) {
866 ice_debug(hw, ICE_DBG_SCHED,
867 "add nodes in SW DB failed status =%d\n",
868 status);
869 break;
870 }
871
872 teid = le32_to_cpu(buf->generic[i].node_teid);
873 new_node = ice_sched_find_node_by_teid(parent, teid);
874 if (!new_node) {
875 ice_debug(hw, ICE_DBG_SCHED,
876 "Node is missing for teid =%d\n", teid);
877 break;
878 }
879
880 new_node->sibling = NULL;
881 new_node->tc_num = tc_node->tc_num;
882
883
884
885 prev = ice_sched_get_first_node(pi, tc_node, layer);
886 if (prev && prev != new_node) {
887 while (prev->sibling)
888 prev = prev->sibling;
889 prev->sibling = new_node;
890 }
891
892
893 if (!pi->sib_head[tc_node->tc_num][layer])
894 pi->sib_head[tc_node->tc_num][layer] = new_node;
895
896 if (i == 0)
897 *first_node_teid = teid;
898 }
899
900 devm_kfree(ice_hw_to_dev(hw), buf);
901 return status;
902}
903
904
905
906
907
908
909
910
911
912
913
914
915
916static enum ice_status
917ice_sched_add_nodes_to_layer(struct ice_port_info *pi,
918 struct ice_sched_node *tc_node,
919 struct ice_sched_node *parent, u8 layer,
920 u16 num_nodes, u32 *first_node_teid,
921 u16 *num_nodes_added)
922{
923 u32 *first_teid_ptr = first_node_teid;
924 u16 new_num_nodes, max_child_nodes;
925 enum ice_status status = 0;
926 struct ice_hw *hw = pi->hw;
927 u16 num_added = 0;
928 u32 temp;
929
930 *num_nodes_added = 0;
931
932 if (!num_nodes)
933 return status;
934
935 if (!parent || layer < hw->sw_entry_point_layer)
936 return ICE_ERR_PARAM;
937
938
939 max_child_nodes = hw->max_children[parent->tx_sched_layer];
940
941
942 if ((parent->num_children + num_nodes) > max_child_nodes) {
943
944 if (parent == tc_node)
945 return ICE_ERR_CFG;
946
947
948 if (parent->num_children < max_child_nodes) {
949 new_num_nodes = max_child_nodes - parent->num_children;
950
951
952
953 status = ice_sched_add_nodes_to_layer(pi, tc_node,
954 parent, layer,
955 new_num_nodes,
956 first_node_teid,
957 &num_added);
958 if (status)
959 return status;
960
961 *num_nodes_added += num_added;
962 }
963
964
965
966
967 if (num_added)
968 first_teid_ptr = &temp;
969
970 new_num_nodes = num_nodes - num_added;
971
972
973 parent = parent->sibling;
974
975
976
977
978
979
980 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent,
981 layer, new_num_nodes,
982 first_teid_ptr,
983 &num_added);
984 *num_nodes_added += num_added;
985 return status;
986 }
987
988 status = ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes,
989 num_nodes_added, first_node_teid);
990 return status;
991}
992
993
994
995
996
997
998
999static u8 ice_sched_get_qgrp_layer(struct ice_hw *hw)
1000{
1001
1002 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;
1003}
1004
1005
1006
1007
1008
1009
1010
1011static u8 ice_sched_get_vsi_layer(struct ice_hw *hw)
1012{
1013
1014
1015
1016
1017
1018
1019 if (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) {
1020 u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;
1021
1022 if (layer > hw->sw_entry_point_layer)
1023 return layer;
1024 }
1025 return hw->sw_entry_point_layer;
1026}
1027
1028
1029
1030
1031
1032
1033
1034
1035static void ice_rm_dflt_leaf_node(struct ice_port_info *pi)
1036{
1037 struct ice_sched_node *node;
1038
1039 node = pi->root;
1040 while (node) {
1041 if (!node->num_children)
1042 break;
1043 node = node->children[0];
1044 }
1045 if (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) {
1046 u32 teid = le32_to_cpu(node->info.node_teid);
1047 enum ice_status status;
1048
1049
1050 status = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid);
1051 if (!status)
1052 ice_free_sched_node(pi, node);
1053 }
1054}
1055
1056
1057
1058
1059
1060
1061
1062
1063static void ice_sched_rm_dflt_nodes(struct ice_port_info *pi)
1064{
1065 struct ice_sched_node *node;
1066
1067 ice_rm_dflt_leaf_node(pi);
1068
1069
1070 node = pi->root;
1071 while (node) {
1072 if (node->tx_sched_layer >= pi->hw->sw_entry_point_layer &&
1073 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&
1074 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) {
1075 ice_free_sched_node(pi, node);
1076 break;
1077 }
1078
1079 if (!node->num_children)
1080 break;
1081 node = node->children[0];
1082 }
1083}
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093enum ice_status ice_sched_init_port(struct ice_port_info *pi)
1094{
1095 struct ice_aqc_get_topo_elem *buf;
1096 enum ice_status status;
1097 struct ice_hw *hw;
1098 u8 num_branches;
1099 u16 num_elems;
1100 u8 i, j;
1101
1102 if (!pi)
1103 return ICE_ERR_PARAM;
1104 hw = pi->hw;
1105
1106
1107 buf = devm_kzalloc(ice_hw_to_dev(hw), ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
1108 if (!buf)
1109 return ICE_ERR_NO_MEMORY;
1110
1111
1112 status = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN,
1113 &num_branches, NULL);
1114 if (status)
1115 goto err_init_port;
1116
1117
1118 if (num_branches < 1 || num_branches > ICE_TXSCHED_MAX_BRANCHES) {
1119 ice_debug(hw, ICE_DBG_SCHED, "num_branches unexpected %d\n",
1120 num_branches);
1121 status = ICE_ERR_PARAM;
1122 goto err_init_port;
1123 }
1124
1125
1126 num_elems = le16_to_cpu(buf[0].hdr.num_elems);
1127
1128
1129 if (num_elems < 1 || num_elems > ICE_AQC_TOPO_MAX_LEVEL_NUM) {
1130 ice_debug(hw, ICE_DBG_SCHED, "num_elems unexpected %d\n",
1131 num_elems);
1132 status = ICE_ERR_PARAM;
1133 goto err_init_port;
1134 }
1135
1136
1137
1138
1139 if (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type ==
1140 ICE_AQC_ELEM_TYPE_LEAF)
1141 pi->last_node_teid =
1142 le32_to_cpu(buf[0].generic[num_elems - 2].node_teid);
1143 else
1144 pi->last_node_teid =
1145 le32_to_cpu(buf[0].generic[num_elems - 1].node_teid);
1146
1147
1148 status = ice_sched_add_root_node(pi, &buf[0].generic[0]);
1149 if (status)
1150 goto err_init_port;
1151
1152
1153 for (i = 0; i < num_branches; i++) {
1154 num_elems = le16_to_cpu(buf[i].hdr.num_elems);
1155
1156
1157 for (j = 1; j < num_elems; j++) {
1158
1159 if (buf[0].generic[j].data.elem_type ==
1160 ICE_AQC_ELEM_TYPE_ENTRY_POINT)
1161 hw->sw_entry_point_layer = j;
1162
1163 status = ice_sched_add_node(pi, j, &buf[i].generic[j]);
1164 if (status)
1165 goto err_init_port;
1166 }
1167 }
1168
1169
1170 if (pi->root)
1171 ice_sched_rm_dflt_nodes(pi);
1172
1173
1174 pi->port_state = ICE_SCHED_PORT_STATE_READY;
1175 mutex_init(&pi->sched_lock);
1176 for (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++)
1177 INIT_LIST_HEAD(&pi->rl_prof_list[i]);
1178
1179err_init_port:
1180 if (status && pi->root) {
1181 ice_free_sched_node(pi, pi->root);
1182 pi->root = NULL;
1183 }
1184
1185 devm_kfree(ice_hw_to_dev(hw), buf);
1186 return status;
1187}
1188
1189
1190
1191
1192
1193
1194
1195enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw)
1196{
1197 struct ice_aqc_query_txsched_res_resp *buf;
1198 enum ice_status status = 0;
1199 __le16 max_sibl;
1200 u16 i;
1201
1202 if (hw->layer_info)
1203 return status;
1204
1205 buf = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*buf), GFP_KERNEL);
1206 if (!buf)
1207 return ICE_ERR_NO_MEMORY;
1208
1209 status = ice_aq_query_sched_res(hw, sizeof(*buf), buf, NULL);
1210 if (status)
1211 goto sched_query_out;
1212
1213 hw->num_tx_sched_layers = le16_to_cpu(buf->sched_props.logical_levels);
1214 hw->num_tx_sched_phys_layers =
1215 le16_to_cpu(buf->sched_props.phys_levels);
1216 hw->flattened_layers = buf->sched_props.flattening_bitmap;
1217 hw->max_cgds = buf->sched_props.max_pf_cgds;
1218
1219
1220
1221
1222
1223
1224
1225
1226 for (i = 0; i < hw->num_tx_sched_layers - 1; i++) {
1227 max_sibl = buf->layer_props[i + 1].max_sibl_grp_sz;
1228 hw->max_children[i] = le16_to_cpu(max_sibl);
1229 }
1230
1231 hw->layer_info = devm_kmemdup(ice_hw_to_dev(hw), buf->layer_props,
1232 (hw->num_tx_sched_layers *
1233 sizeof(*hw->layer_info)),
1234 GFP_KERNEL);
1235 if (!hw->layer_info) {
1236 status = ICE_ERR_NO_MEMORY;
1237 goto sched_query_out;
1238 }
1239
1240sched_query_out:
1241 devm_kfree(ice_hw_to_dev(hw), buf);
1242 return status;
1243}
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254static bool
1255ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,
1256 struct ice_sched_node *node)
1257{
1258 u8 i;
1259
1260 for (i = 0; i < base->num_children; i++) {
1261 struct ice_sched_node *child = base->children[i];
1262
1263 if (node == child)
1264 return true;
1265
1266 if (child->tx_sched_layer > node->tx_sched_layer)
1267 return false;
1268
1269
1270
1271
1272 if (ice_sched_find_node_in_subtree(hw, child, node))
1273 return true;
1274 }
1275 return false;
1276}
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289static struct ice_sched_node *
1290ice_sched_get_free_qgrp(struct ice_port_info *pi,
1291 struct ice_sched_node *vsi_node,
1292 struct ice_sched_node *qgrp_node, u8 owner)
1293{
1294 struct ice_sched_node *min_qgrp;
1295 u8 min_children;
1296
1297 if (!qgrp_node)
1298 return qgrp_node;
1299 min_children = qgrp_node->num_children;
1300 if (!min_children)
1301 return qgrp_node;
1302 min_qgrp = qgrp_node;
1303
1304
1305
1306
1307
1308 while (qgrp_node) {
1309
1310 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))
1311 if (qgrp_node->num_children < min_children &&
1312 qgrp_node->owner == owner) {
1313
1314 min_qgrp = qgrp_node;
1315 min_children = min_qgrp->num_children;
1316
1317 if (!min_children)
1318 break;
1319 }
1320 qgrp_node = qgrp_node->sibling;
1321 }
1322 return min_qgrp;
1323}
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334struct ice_sched_node *
1335ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
1336 u8 owner)
1337{
1338 struct ice_sched_node *vsi_node, *qgrp_node;
1339 struct ice_vsi_ctx *vsi_ctx;
1340 u16 max_children;
1341 u8 qgrp_layer;
1342
1343 qgrp_layer = ice_sched_get_qgrp_layer(pi->hw);
1344 max_children = pi->hw->max_children[qgrp_layer];
1345
1346 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
1347 if (!vsi_ctx)
1348 return NULL;
1349 vsi_node = vsi_ctx->sched.vsi_node[tc];
1350
1351 if (!vsi_node)
1352 return NULL;
1353
1354
1355 qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer);
1356 while (qgrp_node) {
1357
1358 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))
1359 if (qgrp_node->num_children < max_children &&
1360 qgrp_node->owner == owner)
1361 break;
1362 qgrp_node = qgrp_node->sibling;
1363 }
1364
1365
1366 return ice_sched_get_free_qgrp(pi, vsi_node, qgrp_node, owner);
1367}
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378static struct ice_sched_node *
1379ice_sched_get_vsi_node(struct ice_hw *hw, struct ice_sched_node *tc_node,
1380 u16 vsi_handle)
1381{
1382 struct ice_sched_node *node;
1383 u8 vsi_layer;
1384
1385 vsi_layer = ice_sched_get_vsi_layer(hw);
1386 node = ice_sched_get_first_node(hw->port_info, tc_node, vsi_layer);
1387
1388
1389 while (node) {
1390 if (node->vsi_handle == vsi_handle)
1391 return node;
1392 node = node->sibling;
1393 }
1394
1395 return node;
1396}
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407static void
1408ice_sched_calc_vsi_child_nodes(struct ice_hw *hw, u16 num_qs, u16 *num_nodes)
1409{
1410 u16 num = num_qs;
1411 u8 i, qgl, vsil;
1412
1413 qgl = ice_sched_get_qgrp_layer(hw);
1414 vsil = ice_sched_get_vsi_layer(hw);
1415
1416
1417 for (i = qgl; i > vsil; i--) {
1418
1419 num = DIV_ROUND_UP(num, hw->max_children[i]);
1420
1421
1422 num_nodes[i] = num ? num : 1;
1423 }
1424}
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437static enum ice_status
1438ice_sched_add_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle,
1439 struct ice_sched_node *tc_node, u16 *num_nodes,
1440 u8 owner)
1441{
1442 struct ice_sched_node *parent, *node;
1443 struct ice_hw *hw = pi->hw;
1444 enum ice_status status;
1445 u32 first_node_teid;
1446 u16 num_added = 0;
1447 u8 i, qgl, vsil;
1448
1449 qgl = ice_sched_get_qgrp_layer(hw);
1450 vsil = ice_sched_get_vsi_layer(hw);
1451 parent = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);
1452 for (i = vsil + 1; i <= qgl; i++) {
1453 if (!parent)
1454 return ICE_ERR_CFG;
1455
1456 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i,
1457 num_nodes[i],
1458 &first_node_teid,
1459 &num_added);
1460 if (status || num_nodes[i] != num_added)
1461 return ICE_ERR_CFG;
1462
1463
1464
1465
1466 if (num_added) {
1467 parent = ice_sched_find_node_by_teid(tc_node,
1468 first_node_teid);
1469 node = parent;
1470 while (node) {
1471 node->owner = owner;
1472 node = node->sibling;
1473 }
1474 } else {
1475 parent = parent->children[0];
1476 }
1477 }
1478
1479 return 0;
1480}
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492static void
1493ice_sched_calc_vsi_support_nodes(struct ice_hw *hw,
1494 struct ice_sched_node *tc_node, u16 *num_nodes)
1495{
1496 struct ice_sched_node *node;
1497 u8 vsil;
1498 int i;
1499
1500 vsil = ice_sched_get_vsi_layer(hw);
1501 for (i = vsil; i >= hw->sw_entry_point_layer; i--)
1502
1503
1504
1505 if (!tc_node->num_children || i == vsil) {
1506 num_nodes[i]++;
1507 } else {
1508
1509
1510
1511 node = ice_sched_get_first_node(hw->port_info, tc_node,
1512 (u8)i);
1513
1514 while (node) {
1515 if (node->num_children < hw->max_children[i])
1516 break;
1517 node = node->sibling;
1518 }
1519
1520
1521
1522
1523
1524 if (node)
1525 break;
1526
1527 num_nodes[i]++;
1528 }
1529}
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541static enum ice_status
1542ice_sched_add_vsi_support_nodes(struct ice_port_info *pi, u16 vsi_handle,
1543 struct ice_sched_node *tc_node, u16 *num_nodes)
1544{
1545 struct ice_sched_node *parent = tc_node;
1546 enum ice_status status;
1547 u32 first_node_teid;
1548 u16 num_added = 0;
1549 u8 i, vsil;
1550
1551 if (!pi)
1552 return ICE_ERR_PARAM;
1553
1554 vsil = ice_sched_get_vsi_layer(pi->hw);
1555 for (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) {
1556 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent,
1557 i, num_nodes[i],
1558 &first_node_teid,
1559 &num_added);
1560 if (status || num_nodes[i] != num_added)
1561 return ICE_ERR_CFG;
1562
1563
1564
1565
1566 if (num_added)
1567 parent = ice_sched_find_node_by_teid(tc_node,
1568 first_node_teid);
1569 else
1570 parent = parent->children[0];
1571
1572 if (!parent)
1573 return ICE_ERR_CFG;
1574
1575 if (i == vsil)
1576 parent->vsi_handle = vsi_handle;
1577 }
1578
1579 return 0;
1580}
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590static enum ice_status
1591ice_sched_add_vsi_to_topo(struct ice_port_info *pi, u16 vsi_handle, u8 tc)
1592{
1593 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };
1594 struct ice_sched_node *tc_node;
1595 struct ice_hw *hw = pi->hw;
1596
1597 tc_node = ice_sched_get_tc_node(pi, tc);
1598 if (!tc_node)
1599 return ICE_ERR_PARAM;
1600
1601
1602 ice_sched_calc_vsi_support_nodes(hw, tc_node, num_nodes);
1603
1604
1605 return ice_sched_add_vsi_support_nodes(pi, vsi_handle, tc_node,
1606 num_nodes);
1607}
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619static enum ice_status
1620ice_sched_update_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle,
1621 u8 tc, u16 new_numqs, u8 owner)
1622{
1623 u16 new_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };
1624 struct ice_sched_node *vsi_node;
1625 struct ice_sched_node *tc_node;
1626 struct ice_vsi_ctx *vsi_ctx;
1627 enum ice_status status = 0;
1628 struct ice_hw *hw = pi->hw;
1629 u16 prev_numqs;
1630
1631 tc_node = ice_sched_get_tc_node(pi, tc);
1632 if (!tc_node)
1633 return ICE_ERR_CFG;
1634
1635 vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);
1636 if (!vsi_node)
1637 return ICE_ERR_CFG;
1638
1639 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);
1640 if (!vsi_ctx)
1641 return ICE_ERR_PARAM;
1642
1643 prev_numqs = vsi_ctx->sched.max_lanq[tc];
1644
1645 if (new_numqs <= prev_numqs)
1646 return status;
1647 status = ice_alloc_lan_q_ctx(hw, vsi_handle, tc, new_numqs);
1648 if (status)
1649 return status;
1650
1651 if (new_numqs)
1652 ice_sched_calc_vsi_child_nodes(hw, new_numqs, new_num_nodes);
1653
1654
1655
1656
1657
1658
1659
1660 status = ice_sched_add_vsi_child_nodes(pi, vsi_handle, tc_node,
1661 new_num_nodes, owner);
1662 if (status)
1663 return status;
1664 vsi_ctx->sched.max_lanq[tc] = new_numqs;
1665
1666 return 0;
1667}
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682enum ice_status
1683ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
1684 u8 owner, bool enable)
1685{
1686 struct ice_sched_node *vsi_node, *tc_node;
1687 struct ice_vsi_ctx *vsi_ctx;
1688 enum ice_status status = 0;
1689 struct ice_hw *hw = pi->hw;
1690
1691 ice_debug(pi->hw, ICE_DBG_SCHED, "add/config VSI %d\n", vsi_handle);
1692 tc_node = ice_sched_get_tc_node(pi, tc);
1693 if (!tc_node)
1694 return ICE_ERR_PARAM;
1695 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);
1696 if (!vsi_ctx)
1697 return ICE_ERR_PARAM;
1698 vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);
1699
1700
1701 if (!enable) {
1702 if (vsi_node && vsi_node->in_use) {
1703 u32 teid = le32_to_cpu(vsi_node->info.node_teid);
1704
1705 status = ice_sched_suspend_resume_elems(hw, 1, &teid,
1706 true);
1707 if (!status)
1708 vsi_node->in_use = false;
1709 }
1710 return status;
1711 }
1712
1713
1714 if (!vsi_node) {
1715 status = ice_sched_add_vsi_to_topo(pi, vsi_handle, tc);
1716 if (status)
1717 return status;
1718
1719 vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);
1720 if (!vsi_node)
1721 return ICE_ERR_CFG;
1722
1723 vsi_ctx->sched.vsi_node[tc] = vsi_node;
1724 vsi_node->in_use = true;
1725
1726
1727
1728
1729 vsi_ctx->sched.max_lanq[tc] = 0;
1730 }
1731
1732
1733 status = ice_sched_update_vsi_child_nodes(pi, vsi_handle, tc, maxqs,
1734 owner);
1735 if (status)
1736 return status;
1737
1738
1739 if (!vsi_node->in_use) {
1740 u32 teid = le32_to_cpu(vsi_node->info.node_teid);
1741
1742 status = ice_sched_suspend_resume_elems(hw, 1, &teid, false);
1743 if (!status)
1744 vsi_node->in_use = true;
1745 }
1746
1747 return status;
1748}
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758static void ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle)
1759{
1760 struct ice_sched_agg_info *agg_info;
1761 struct ice_sched_agg_info *atmp;
1762
1763 list_for_each_entry_safe(agg_info, atmp, &pi->hw->agg_list,
1764 list_entry) {
1765 struct ice_sched_agg_vsi_info *agg_vsi_info;
1766 struct ice_sched_agg_vsi_info *vtmp;
1767
1768 list_for_each_entry_safe(agg_vsi_info, vtmp,
1769 &agg_info->agg_vsi_list, list_entry)
1770 if (agg_vsi_info->vsi_handle == vsi_handle) {
1771 list_del(&agg_vsi_info->list_entry);
1772 devm_kfree(ice_hw_to_dev(pi->hw),
1773 agg_vsi_info);
1774 return;
1775 }
1776 }
1777}
1778
1779
1780
1781
1782
1783
1784
1785static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node)
1786{
1787 u8 i;
1788
1789 for (i = 0; i < node->num_children; i++)
1790 if (ice_sched_is_leaf_node_present(node->children[i]))
1791 return true;
1792
1793 return (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF);
1794}
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805static enum ice_status
1806ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner)
1807{
1808 enum ice_status status = ICE_ERR_PARAM;
1809 struct ice_vsi_ctx *vsi_ctx;
1810 u8 i;
1811
1812 ice_debug(pi->hw, ICE_DBG_SCHED, "removing VSI %d\n", vsi_handle);
1813 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
1814 return status;
1815 mutex_lock(&pi->sched_lock);
1816 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
1817 if (!vsi_ctx)
1818 goto exit_sched_rm_vsi_cfg;
1819
1820 ice_for_each_traffic_class(i) {
1821 struct ice_sched_node *vsi_node, *tc_node;
1822 u8 j = 0;
1823
1824 tc_node = ice_sched_get_tc_node(pi, i);
1825 if (!tc_node)
1826 continue;
1827
1828 vsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle);
1829 if (!vsi_node)
1830 continue;
1831
1832 if (ice_sched_is_leaf_node_present(vsi_node)) {
1833 ice_debug(pi->hw, ICE_DBG_SCHED,
1834 "VSI has leaf nodes in TC %d\n", i);
1835 status = ICE_ERR_IN_USE;
1836 goto exit_sched_rm_vsi_cfg;
1837 }
1838 while (j < vsi_node->num_children) {
1839 if (vsi_node->children[j]->owner == owner) {
1840 ice_free_sched_node(pi, vsi_node->children[j]);
1841
1842
1843
1844
1845 j = 0;
1846 } else {
1847 j++;
1848 }
1849 }
1850
1851 if (!vsi_node->num_children) {
1852 ice_free_sched_node(pi, vsi_node);
1853 vsi_ctx->sched.vsi_node[i] = NULL;
1854
1855
1856 ice_sched_rm_agg_vsi_info(pi, vsi_handle);
1857 }
1858 if (owner == ICE_SCHED_NODE_OWNER_LAN)
1859 vsi_ctx->sched.max_lanq[i] = 0;
1860 }
1861 status = 0;
1862
1863exit_sched_rm_vsi_cfg:
1864 mutex_unlock(&pi->sched_lock);
1865 return status;
1866}
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle)
1877{
1878 return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN);
1879}
1880
1881
1882
1883
1884
1885
1886
1887
1888static void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi)
1889{
1890 u16 ln;
1891
1892 for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
1893 struct ice_aqc_rl_profile_info *rl_prof_elem;
1894 struct ice_aqc_rl_profile_info *rl_prof_tmp;
1895
1896 list_for_each_entry_safe(rl_prof_elem, rl_prof_tmp,
1897 &pi->rl_prof_list[ln], list_entry) {
1898 if (!ice_sched_del_rl_profile(pi->hw, rl_prof_elem))
1899 ice_debug(pi->hw, ICE_DBG_SCHED,
1900 "Removed rl profile\n");
1901 }
1902 }
1903}
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916static enum ice_status
1917ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node,
1918 struct ice_aqc_txsched_elem_data *info)
1919{
1920 struct ice_aqc_txsched_elem_data buf;
1921 enum ice_status status;
1922 u16 elem_cfgd = 0;
1923 u16 num_elems = 1;
1924
1925 buf = *info;
1926
1927 buf.parent_teid = 0;
1928
1929 buf.data.elem_type = 0;
1930
1931 buf.data.flags = 0;
1932
1933
1934
1935 status = ice_aq_cfg_sched_elems(hw, num_elems, &buf, sizeof(buf),
1936 &elem_cfgd, NULL);
1937 if (status || elem_cfgd != num_elems) {
1938 ice_debug(hw, ICE_DBG_SCHED, "Config sched elem error\n");
1939 return ICE_ERR_CFG;
1940 }
1941
1942
1943
1944
1945 node->info.data = info->data;
1946 return status;
1947}
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958static enum ice_status
1959ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node,
1960 enum ice_rl_type rl_type, u16 bw_alloc)
1961{
1962 struct ice_aqc_txsched_elem_data buf;
1963 struct ice_aqc_txsched_elem *data;
1964 enum ice_status status;
1965
1966 buf = node->info;
1967 data = &buf.data;
1968 if (rl_type == ICE_MIN_BW) {
1969 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR;
1970 data->cir_bw.bw_alloc = cpu_to_le16(bw_alloc);
1971 } else if (rl_type == ICE_MAX_BW) {
1972 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR;
1973 data->eir_bw.bw_alloc = cpu_to_le16(bw_alloc);
1974 } else {
1975 return ICE_ERR_PARAM;
1976 }
1977
1978
1979 status = ice_sched_update_elem(hw, node, &buf);
1980 return status;
1981}
1982
1983
1984
1985
1986
1987
1988
1989
1990static void ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw)
1991{
1992 if (bw == ICE_SCHED_DFLT_BW) {
1993 clear_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap);
1994 bw_t_info->cir_bw.bw = 0;
1995 } else {
1996
1997 set_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap);
1998 bw_t_info->cir_bw.bw = bw;
1999 }
2000}
2001
2002
2003
2004
2005
2006
2007
2008
2009static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw)
2010{
2011 if (bw == ICE_SCHED_DFLT_BW) {
2012 clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);
2013 bw_t_info->eir_bw.bw = 0;
2014 } else {
2015
2016
2017
2018
2019 clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);
2020 bw_t_info->shared_bw = 0;
2021
2022 set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);
2023 bw_t_info->eir_bw.bw = bw;
2024 }
2025}
2026
2027
2028
2029
2030
2031
2032
2033
2034static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw)
2035{
2036 if (bw == ICE_SCHED_DFLT_BW) {
2037 clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);
2038 bw_t_info->shared_bw = 0;
2039 } else {
2040
2041
2042
2043
2044 clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);
2045 bw_t_info->eir_bw.bw = 0;
2046
2047 set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);
2048 bw_t_info->shared_bw = bw;
2049 }
2050}
2051
2052
2053
2054
2055
2056
2057
2058static u16 ice_sched_calc_wakeup(s32 bw)
2059{
2060 s64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f;
2061 s32 wakeup_f_int;
2062 u16 wakeup = 0;
2063
2064
2065 bytes_per_sec = div64_long(((s64)bw * 1000), BITS_PER_BYTE);
2066 wakeup_int = div64_long(ICE_RL_PROF_FREQUENCY, bytes_per_sec);
2067 if (wakeup_int > 63) {
2068 wakeup = (u16)((1 << 15) | wakeup_int);
2069 } else {
2070
2071
2072
2073 wakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int;
2074 wakeup_a = div64_long((s64)ICE_RL_PROF_MULTIPLIER *
2075 ICE_RL_PROF_FREQUENCY,
2076 bytes_per_sec);
2077
2078
2079 wakeup_f = wakeup_a - wakeup_b;
2080
2081
2082 if (wakeup_f > div64_long(ICE_RL_PROF_MULTIPLIER, 2))
2083 wakeup_f += 1;
2084
2085 wakeup_f_int = (s32)div64_long(wakeup_f * ICE_RL_PROF_FRACTION,
2086 ICE_RL_PROF_MULTIPLIER);
2087 wakeup |= (u16)(wakeup_int << 9);
2088 wakeup |= (u16)(0x1ff & wakeup_f_int);
2089 }
2090
2091 return wakeup;
2092}
2093
2094
2095
2096
2097
2098
2099
2100
2101static enum ice_status
2102ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile)
2103{
2104 enum ice_status status = ICE_ERR_PARAM;
2105 s64 bytes_per_sec, ts_rate, mv_tmp;
2106 bool found = false;
2107 s32 encode = 0;
2108 s64 mv = 0;
2109 s32 i;
2110
2111
2112 if (bw < ICE_SCHED_MIN_BW || bw > ICE_SCHED_MAX_BW)
2113 return status;
2114
2115
2116 bytes_per_sec = div64_long(((s64)bw * 1000), BITS_PER_BYTE);
2117
2118
2119 for (i = 0; i < 64; i++) {
2120 u64 pow_result = BIT_ULL(i);
2121
2122 ts_rate = div64_long((s64)ICE_RL_PROF_FREQUENCY,
2123 pow_result * ICE_RL_PROF_TS_MULTIPLIER);
2124 if (ts_rate <= 0)
2125 continue;
2126
2127
2128 mv_tmp = div64_long(bytes_per_sec * ICE_RL_PROF_MULTIPLIER,
2129 ts_rate);
2130
2131
2132 mv = round_up_64bit(mv_tmp, ICE_RL_PROF_MULTIPLIER);
2133
2134
2135
2136
2137 if (mv > ICE_RL_PROF_ACCURACY_BYTES) {
2138 encode = i;
2139 found = true;
2140 break;
2141 }
2142 }
2143 if (found) {
2144 u16 wm;
2145
2146 wm = ice_sched_calc_wakeup(bw);
2147 profile->rl_multiply = cpu_to_le16(mv);
2148 profile->wake_up_calc = cpu_to_le16(wm);
2149 profile->rl_encode = cpu_to_le16(encode);
2150 status = 0;
2151 } else {
2152 status = ICE_ERR_DOES_NOT_EXIST;
2153 }
2154
2155 return status;
2156}
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171static struct ice_aqc_rl_profile_info *
2172ice_sched_add_rl_profile(struct ice_port_info *pi,
2173 enum ice_rl_type rl_type, u32 bw, u8 layer_num)
2174{
2175 struct ice_aqc_rl_profile_info *rl_prof_elem;
2176 u16 profiles_added = 0, num_profiles = 1;
2177 struct ice_aqc_rl_profile_elem *buf;
2178 enum ice_status status;
2179 struct ice_hw *hw;
2180 u8 profile_type;
2181
2182 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
2183 return NULL;
2184 switch (rl_type) {
2185 case ICE_MIN_BW:
2186 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR;
2187 break;
2188 case ICE_MAX_BW:
2189 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR;
2190 break;
2191 case ICE_SHARED_BW:
2192 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL;
2193 break;
2194 default:
2195 return NULL;
2196 }
2197
2198 if (!pi)
2199 return NULL;
2200 hw = pi->hw;
2201 list_for_each_entry(rl_prof_elem, &pi->rl_prof_list[layer_num],
2202 list_entry)
2203 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==
2204 profile_type && rl_prof_elem->bw == bw)
2205
2206 return rl_prof_elem;
2207
2208
2209 rl_prof_elem = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*rl_prof_elem),
2210 GFP_KERNEL);
2211
2212 if (!rl_prof_elem)
2213 return NULL;
2214
2215 status = ice_sched_bw_to_rl_profile(bw, &rl_prof_elem->profile);
2216 if (status)
2217 goto exit_add_rl_prof;
2218
2219 rl_prof_elem->bw = bw;
2220
2221 rl_prof_elem->profile.level = layer_num + 1;
2222 rl_prof_elem->profile.flags = profile_type;
2223 rl_prof_elem->profile.max_burst_size = cpu_to_le16(hw->max_burst_size);
2224
2225
2226 buf = &rl_prof_elem->profile;
2227 status = ice_aq_add_rl_profile(hw, num_profiles, buf, sizeof(*buf),
2228 &profiles_added, NULL);
2229 if (status || profiles_added != num_profiles)
2230 goto exit_add_rl_prof;
2231
2232
2233 rl_prof_elem->prof_id_ref = 0;
2234 list_add(&rl_prof_elem->list_entry, &pi->rl_prof_list[layer_num]);
2235 return rl_prof_elem;
2236
2237exit_add_rl_prof:
2238 devm_kfree(ice_hw_to_dev(hw), rl_prof_elem);
2239 return NULL;
2240}
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251static enum ice_status
2252ice_sched_cfg_node_bw_lmt(struct ice_hw *hw, struct ice_sched_node *node,
2253 enum ice_rl_type rl_type, u16 rl_prof_id)
2254{
2255 struct ice_aqc_txsched_elem_data buf;
2256 struct ice_aqc_txsched_elem *data;
2257
2258 buf = node->info;
2259 data = &buf.data;
2260 switch (rl_type) {
2261 case ICE_MIN_BW:
2262 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR;
2263 data->cir_bw.bw_profile_idx = cpu_to_le16(rl_prof_id);
2264 break;
2265 case ICE_MAX_BW:
2266
2267
2268
2269 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED)
2270 return ICE_ERR_CFG;
2271 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR;
2272 data->eir_bw.bw_profile_idx = cpu_to_le16(rl_prof_id);
2273 break;
2274 case ICE_SHARED_BW:
2275
2276 if (rl_prof_id == ICE_SCHED_NO_SHARED_RL_PROF_ID) {
2277
2278 data->valid_sections &= ~ICE_AQC_ELEM_VALID_SHARED;
2279 data->srl_id = 0;
2280
2281
2282 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR;
2283 data->eir_bw.bw_profile_idx =
2284 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
2285 break;
2286 }
2287
2288
2289
2290 if ((data->valid_sections & ICE_AQC_ELEM_VALID_EIR) &&
2291 (le16_to_cpu(data->eir_bw.bw_profile_idx) !=
2292 ICE_SCHED_DFLT_RL_PROF_ID))
2293 return ICE_ERR_CFG;
2294
2295 data->valid_sections &= ~ICE_AQC_ELEM_VALID_EIR;
2296
2297 data->valid_sections |= ICE_AQC_ELEM_VALID_SHARED;
2298 data->srl_id = cpu_to_le16(rl_prof_id);
2299 break;
2300 default:
2301
2302 return ICE_ERR_PARAM;
2303 }
2304
2305
2306 return ice_sched_update_elem(hw, node, &buf);
2307}
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317static u16
2318ice_sched_get_node_rl_prof_id(struct ice_sched_node *node,
2319 enum ice_rl_type rl_type)
2320{
2321 u16 rl_prof_id = ICE_SCHED_INVAL_PROF_ID;
2322 struct ice_aqc_txsched_elem *data;
2323
2324 data = &node->info.data;
2325 switch (rl_type) {
2326 case ICE_MIN_BW:
2327 if (data->valid_sections & ICE_AQC_ELEM_VALID_CIR)
2328 rl_prof_id = le16_to_cpu(data->cir_bw.bw_profile_idx);
2329 break;
2330 case ICE_MAX_BW:
2331 if (data->valid_sections & ICE_AQC_ELEM_VALID_EIR)
2332 rl_prof_id = le16_to_cpu(data->eir_bw.bw_profile_idx);
2333 break;
2334 case ICE_SHARED_BW:
2335 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED)
2336 rl_prof_id = le16_to_cpu(data->srl_id);
2337 break;
2338 default:
2339 break;
2340 }
2341
2342 return rl_prof_id;
2343}
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353static u8
2354ice_sched_get_rl_prof_layer(struct ice_port_info *pi, enum ice_rl_type rl_type,
2355 u8 layer_index)
2356{
2357 struct ice_hw *hw = pi->hw;
2358
2359 if (layer_index >= hw->num_tx_sched_layers)
2360 return ICE_SCHED_INVAL_LAYER_NUM;
2361 switch (rl_type) {
2362 case ICE_MIN_BW:
2363 if (hw->layer_info[layer_index].max_cir_rl_profiles)
2364 return layer_index;
2365 break;
2366 case ICE_MAX_BW:
2367 if (hw->layer_info[layer_index].max_eir_rl_profiles)
2368 return layer_index;
2369 break;
2370 case ICE_SHARED_BW:
2371
2372
2373
2374 if (hw->layer_info[layer_index].max_srl_profiles)
2375 return layer_index;
2376 else if (layer_index < hw->num_tx_sched_layers - 1 &&
2377 hw->layer_info[layer_index + 1].max_srl_profiles)
2378 return layer_index + 1;
2379 else if (layer_index > 0 &&
2380 hw->layer_info[layer_index - 1].max_srl_profiles)
2381 return layer_index - 1;
2382 break;
2383 default:
2384 break;
2385 }
2386 return ICE_SCHED_INVAL_LAYER_NUM;
2387}
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397static struct ice_sched_node *
2398ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer)
2399{
2400 if (srl_layer > node->tx_sched_layer)
2401 return node->children[0];
2402 else if (srl_layer < node->tx_sched_layer)
2403
2404
2405
2406 return node->parent;
2407 else
2408 return node;
2409}
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422static enum ice_status
2423ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type,
2424 u16 profile_id)
2425{
2426 struct ice_aqc_rl_profile_info *rl_prof_elem;
2427 enum ice_status status = 0;
2428
2429 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
2430 return ICE_ERR_PARAM;
2431
2432 list_for_each_entry(rl_prof_elem, &pi->rl_prof_list[layer_num],
2433 list_entry)
2434 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==
2435 profile_type &&
2436 le16_to_cpu(rl_prof_elem->profile.profile_id) ==
2437 profile_id) {
2438 if (rl_prof_elem->prof_id_ref)
2439 rl_prof_elem->prof_id_ref--;
2440
2441
2442 status = ice_sched_del_rl_profile(pi->hw, rl_prof_elem);
2443 if (status && status != ICE_ERR_IN_USE)
2444 ice_debug(pi->hw, ICE_DBG_SCHED,
2445 "Remove rl profile failed\n");
2446 break;
2447 }
2448 if (status == ICE_ERR_IN_USE)
2449 status = 0;
2450 return status;
2451}
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464static enum ice_status
2465ice_sched_set_node_bw_dflt(struct ice_port_info *pi,
2466 struct ice_sched_node *node,
2467 enum ice_rl_type rl_type, u8 layer_num)
2468{
2469 enum ice_status status;
2470 struct ice_hw *hw;
2471 u8 profile_type;
2472 u16 rl_prof_id;
2473 u16 old_id;
2474
2475 hw = pi->hw;
2476 switch (rl_type) {
2477 case ICE_MIN_BW:
2478 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR;
2479 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID;
2480 break;
2481 case ICE_MAX_BW:
2482 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR;
2483 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID;
2484 break;
2485 case ICE_SHARED_BW:
2486 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL;
2487
2488 rl_prof_id = ICE_SCHED_NO_SHARED_RL_PROF_ID;
2489 break;
2490 default:
2491 return ICE_ERR_PARAM;
2492 }
2493
2494 old_id = ice_sched_get_node_rl_prof_id(node, rl_type);
2495
2496 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id);
2497 if (status)
2498 return status;
2499
2500
2501 if (old_id == ICE_SCHED_DFLT_RL_PROF_ID ||
2502 old_id == ICE_SCHED_INVAL_PROF_ID)
2503 return 0;
2504
2505 return ice_sched_rm_rl_profile(pi, layer_num, profile_type, old_id);
2506}
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521static enum ice_status
2522ice_sched_set_eir_srl_excl(struct ice_port_info *pi,
2523 struct ice_sched_node *node,
2524 u8 layer_num, enum ice_rl_type rl_type, u32 bw)
2525{
2526 if (rl_type == ICE_SHARED_BW) {
2527
2528 if (bw == ICE_SCHED_DFLT_BW)
2529
2530
2531
2532
2533 return 0;
2534
2535
2536
2537
2538
2539 return ice_sched_set_node_bw_dflt(pi, node, ICE_MAX_BW,
2540 layer_num);
2541 } else if (rl_type == ICE_MAX_BW &&
2542 node->info.data.valid_sections & ICE_AQC_ELEM_VALID_SHARED) {
2543
2544
2545
2546 return ice_sched_set_node_bw_dflt(pi, node,
2547 ICE_SHARED_BW,
2548 layer_num);
2549 }
2550 return 0;
2551}
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565static enum ice_status
2566ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,
2567 enum ice_rl_type rl_type, u32 bw, u8 layer_num)
2568{
2569 struct ice_aqc_rl_profile_info *rl_prof_info;
2570 enum ice_status status = ICE_ERR_PARAM;
2571 struct ice_hw *hw = pi->hw;
2572 u16 old_id, rl_prof_id;
2573
2574 rl_prof_info = ice_sched_add_rl_profile(pi, rl_type, bw, layer_num);
2575 if (!rl_prof_info)
2576 return status;
2577
2578 rl_prof_id = le16_to_cpu(rl_prof_info->profile.profile_id);
2579
2580
2581 old_id = ice_sched_get_node_rl_prof_id(node, rl_type);
2582
2583 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id);
2584 if (status)
2585 return status;
2586
2587
2588
2589 rl_prof_info->prof_id_ref++;
2590
2591
2592 if ((old_id == ICE_SCHED_DFLT_RL_PROF_ID && rl_type != ICE_SHARED_BW) ||
2593 old_id == ICE_SCHED_INVAL_PROF_ID || old_id == rl_prof_id)
2594 return 0;
2595
2596 return ice_sched_rm_rl_profile(pi, layer_num,
2597 rl_prof_info->profile.flags &
2598 ICE_AQC_RL_PROFILE_TYPE_M, old_id);
2599}
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611static enum ice_status
2612ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,
2613 enum ice_rl_type rl_type, u32 bw)
2614{
2615 struct ice_sched_node *cfg_node = node;
2616 enum ice_status status;
2617
2618 struct ice_hw *hw;
2619 u8 layer_num;
2620
2621 if (!pi)
2622 return ICE_ERR_PARAM;
2623 hw = pi->hw;
2624
2625 ice_sched_rm_unused_rl_prof(pi);
2626 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type,
2627 node->tx_sched_layer);
2628 if (layer_num >= hw->num_tx_sched_layers)
2629 return ICE_ERR_PARAM;
2630
2631 if (rl_type == ICE_SHARED_BW) {
2632
2633 cfg_node = ice_sched_get_srl_node(node, layer_num);
2634 if (!cfg_node)
2635 return ICE_ERR_CFG;
2636 }
2637
2638
2639
2640 status = ice_sched_set_eir_srl_excl(pi, cfg_node, layer_num, rl_type,
2641 bw);
2642 if (status)
2643 return status;
2644 if (bw == ICE_SCHED_DFLT_BW)
2645 return ice_sched_set_node_bw_dflt(pi, cfg_node, rl_type,
2646 layer_num);
2647 return ice_sched_set_node_bw(pi, cfg_node, rl_type, bw, layer_num);
2648}
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660static enum ice_status
2661ice_sched_set_node_bw_dflt_lmt(struct ice_port_info *pi,
2662 struct ice_sched_node *node,
2663 enum ice_rl_type rl_type)
2664{
2665 return ice_sched_set_node_bw_lmt(pi, node, rl_type,
2666 ICE_SCHED_DFLT_BW);
2667}
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678static enum ice_status
2679ice_sched_validate_srl_node(struct ice_sched_node *node, u8 sel_layer)
2680{
2681
2682
2683
2684
2685
2686 if (sel_layer == node->tx_sched_layer ||
2687 ((sel_layer == node->tx_sched_layer + 1) &&
2688 node->num_children == 1) ||
2689 ((sel_layer == node->tx_sched_layer - 1) &&
2690 (node->parent && node->parent->num_children == 1)))
2691 return 0;
2692
2693 return ICE_ERR_CFG;
2694}
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704static enum ice_status
2705ice_sched_save_q_bw(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, u32 bw)
2706{
2707 switch (rl_type) {
2708 case ICE_MIN_BW:
2709 ice_set_clear_cir_bw(&q_ctx->bw_t_info, bw);
2710 break;
2711 case ICE_MAX_BW:
2712 ice_set_clear_eir_bw(&q_ctx->bw_t_info, bw);
2713 break;
2714 case ICE_SHARED_BW:
2715 ice_set_clear_shared_bw(&q_ctx->bw_t_info, bw);
2716 break;
2717 default:
2718 return ICE_ERR_PARAM;
2719 }
2720 return 0;
2721}
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734static enum ice_status
2735ice_sched_set_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
2736 u16 q_handle, enum ice_rl_type rl_type, u32 bw)
2737{
2738 enum ice_status status = ICE_ERR_PARAM;
2739 struct ice_sched_node *node;
2740 struct ice_q_ctx *q_ctx;
2741
2742 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
2743 return ICE_ERR_PARAM;
2744 mutex_lock(&pi->sched_lock);
2745 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle);
2746 if (!q_ctx)
2747 goto exit_q_bw_lmt;
2748 node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid);
2749 if (!node) {
2750 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n");
2751 goto exit_q_bw_lmt;
2752 }
2753
2754
2755 if (node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF)
2756 goto exit_q_bw_lmt;
2757
2758
2759 if (rl_type == ICE_SHARED_BW) {
2760 u8 sel_layer;
2761
2762 sel_layer = ice_sched_get_rl_prof_layer(pi, rl_type,
2763 node->tx_sched_layer);
2764 if (sel_layer >= pi->hw->num_tx_sched_layers) {
2765 status = ICE_ERR_PARAM;
2766 goto exit_q_bw_lmt;
2767 }
2768 status = ice_sched_validate_srl_node(node, sel_layer);
2769 if (status)
2770 goto exit_q_bw_lmt;
2771 }
2772
2773 if (bw == ICE_SCHED_DFLT_BW)
2774 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type);
2775 else
2776 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw);
2777
2778 if (!status)
2779 status = ice_sched_save_q_bw(q_ctx, rl_type, bw);
2780
2781exit_q_bw_lmt:
2782 mutex_unlock(&pi->sched_lock);
2783 return status;
2784}
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797enum ice_status
2798ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
2799 u16 q_handle, enum ice_rl_type rl_type, u32 bw)
2800{
2801 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type,
2802 bw);
2803}
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815enum ice_status
2816ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
2817 u16 q_handle, enum ice_rl_type rl_type)
2818{
2819 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type,
2820 ICE_SCHED_DFLT_BW);
2821}
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes)
2833{
2834 u16 burst_size_to_prog;
2835
2836 if (bytes < ICE_MIN_BURST_SIZE_ALLOWED ||
2837 bytes > ICE_MAX_BURST_SIZE_ALLOWED)
2838 return ICE_ERR_PARAM;
2839 if (ice_round_to_num(bytes, 64) <=
2840 ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY) {
2841
2842
2843 burst_size_to_prog = ICE_64_BYTE_GRANULARITY;
2844
2845 bytes = ice_round_to_num(bytes, 64);
2846
2847 burst_size_to_prog |= (u16)(bytes / 64);
2848 } else {
2849
2850
2851 burst_size_to_prog = ICE_KBYTE_GRANULARITY;
2852
2853 bytes = ice_round_to_num(bytes, 1024);
2854
2855 if (bytes > ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY)
2856 bytes = ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY;
2857
2858 burst_size_to_prog |= (u16)(bytes / 1024);
2859 }
2860 hw->max_burst_size = burst_size_to_prog;
2861 return 0;
2862}
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873static enum ice_status
2874ice_sched_replay_node_prio(struct ice_hw *hw, struct ice_sched_node *node,
2875 u8 priority)
2876{
2877 struct ice_aqc_txsched_elem_data buf;
2878 struct ice_aqc_txsched_elem *data;
2879 enum ice_status status;
2880
2881 buf = node->info;
2882 data = &buf.data;
2883 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;
2884 data->generic = priority;
2885
2886
2887 status = ice_sched_update_elem(hw, node, &buf);
2888 return status;
2889}
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900static enum ice_status
2901ice_sched_replay_node_bw(struct ice_hw *hw, struct ice_sched_node *node,
2902 struct ice_bw_type_info *bw_t_info)
2903{
2904 struct ice_port_info *pi = hw->port_info;
2905 enum ice_status status = ICE_ERR_PARAM;
2906 u16 bw_alloc;
2907
2908 if (!node)
2909 return status;
2910 if (bitmap_empty(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CNT))
2911 return 0;
2912 if (test_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap)) {
2913 status = ice_sched_replay_node_prio(hw, node,
2914 bw_t_info->generic);
2915 if (status)
2916 return status;
2917 }
2918 if (test_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap)) {
2919 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MIN_BW,
2920 bw_t_info->cir_bw.bw);
2921 if (status)
2922 return status;
2923 }
2924 if (test_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap)) {
2925 bw_alloc = bw_t_info->cir_bw.bw_alloc;
2926 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MIN_BW,
2927 bw_alloc);
2928 if (status)
2929 return status;
2930 }
2931 if (test_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap)) {
2932 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MAX_BW,
2933 bw_t_info->eir_bw.bw);
2934 if (status)
2935 return status;
2936 }
2937 if (test_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap)) {
2938 bw_alloc = bw_t_info->eir_bw.bw_alloc;
2939 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MAX_BW,
2940 bw_alloc);
2941 if (status)
2942 return status;
2943 }
2944 if (test_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap))
2945 status = ice_sched_set_node_bw_lmt(pi, node, ICE_SHARED_BW,
2946 bw_t_info->shared_bw);
2947 return status;
2948}
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958enum ice_status
2959ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx)
2960{
2961 struct ice_sched_node *q_node;
2962
2963
2964 q_node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid);
2965 if (!q_node)
2966 return ICE_ERR_PARAM;
2967 return ice_sched_replay_node_bw(pi->hw, q_node, &q_ctx->bw_t_info);
2968}
2969