LXR linux/drivers/net/ethernet/mellanox/mlx5/core/lib/gid.c

   1/*
   2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#include <linux/mlx5/driver.h>
  34#include <linux/etherdevice.h>
  35#include <linux/idr.h>
  36#include "mlx5_core.h"
  37#include "lib/mlx5.h"
  38
  39void mlx5_init_reserved_gids(struct mlx5_core_dev *dev)
  40{
  41        unsigned int tblsz = MLX5_CAP_ROCE(dev, roce_address_table_size);
  42
  43        ida_init(&dev->roce.reserved_gids.ida);
  44        dev->roce.reserved_gids.start = tblsz;
  45        dev->roce.reserved_gids.count = 0;
  46}
  47
  48void mlx5_cleanup_reserved_gids(struct mlx5_core_dev *dev)
  49{
  50        WARN_ON(!ida_is_empty(&dev->roce.reserved_gids.ida));
  51        dev->roce.reserved_gids.start = 0;
  52        dev->roce.reserved_gids.count = 0;
  53        ida_destroy(&dev->roce.reserved_gids.ida);
  54}
  55
  56int mlx5_core_reserve_gids(struct mlx5_core_dev *dev, unsigned int count)
  57{
  58        if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
  59                mlx5_core_err(dev, "Cannot reserve GIDs when interfaces are up\n");
  60                return -EPERM;
  61        }
  62        if (dev->roce.reserved_gids.start < count) {
  63                mlx5_core_warn(dev, "GID table exhausted attempting to reserve %d more GIDs\n",
  64                               count);
  65                return -ENOMEM;
  66        }
  67        if (dev->roce.reserved_gids.count + count > MLX5_MAX_RESERVED_GIDS) {
  68                mlx5_core_warn(dev, "Unable to reserve %d more GIDs\n", count);
  69                return -ENOMEM;
  70        }
  71
  72        dev->roce.reserved_gids.start -= count;
  73        dev->roce.reserved_gids.count += count;
  74        mlx5_core_dbg(dev, "Reserved %u GIDs starting at %u\n",
  75                      dev->roce.reserved_gids.count,
  76                      dev->roce.reserved_gids.start);
  77        return 0;
  78}
  79
  80void mlx5_core_unreserve_gids(struct mlx5_core_dev *dev, unsigned int count)
  81{
  82        WARN(test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state), "Unreserving GIDs when interfaces are up");
  83        WARN(count > dev->roce.reserved_gids.count, "Unreserving %u GIDs when only %u reserved",
  84             count, dev->roce.reserved_gids.count);
  85
  86        dev->roce.reserved_gids.start += count;
  87        dev->roce.reserved_gids.count -= count;
  88        mlx5_core_dbg(dev, "%u GIDs starting at %u left reserved\n",
  89                      dev->roce.reserved_gids.count,
  90                      dev->roce.reserved_gids.start);
  91}
  92
  93int mlx5_core_reserved_gid_alloc(struct mlx5_core_dev *dev, int *gid_index)
  94{
  95        int end = dev->roce.reserved_gids.start +
  96                  dev->roce.reserved_gids.count;
  97        int index = 0;
  98
  99        index = ida_simple_get(&dev->roce.reserved_gids.ida,
 100                               dev->roce.reserved_gids.start, end,
 101                               GFP_KERNEL);
 102        if (index < 0)
 103                return index;
 104
 105        mlx5_core_dbg(dev, "Allocating reserved GID %u\n", index);
 106        *gid_index = index;
 107        return 0;
 108}
 109
 110void mlx5_core_reserved_gid_free(struct mlx5_core_dev *dev, int gid_index)
 111{
 112        mlx5_core_dbg(dev, "Freeing reserved GID %u\n", gid_index);
 113        ida_simple_remove(&dev->roce.reserved_gids.ida, gid_index);
 114}
 115
 116unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev)
 117{
 118        return dev->roce.reserved_gids.count;
 119}
 120EXPORT_SYMBOL_GPL(mlx5_core_reserved_gids_count);
 121
 122int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
 123                           u8 roce_version, u8 roce_l3_type, const u8 *gid,
 124                           const u8 *mac, bool vlan, u16 vlan_id, u8 port_num)
 125{
 126#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 127        u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {};
 128        void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 129        char *addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, in_addr,
 130                                          source_l3_address);
 131        void *addr_mac = MLX5_ADDR_OF(roce_addr_layout, in_addr,
 132                                      source_mac_47_32);
 133        int gidsz = MLX5_FLD_SZ_BYTES(roce_addr_layout, source_l3_address);
 134
 135        if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
 136                return -EINVAL;
 137
 138        if (gid) {
 139                if (vlan) {
 140                        MLX5_SET_RA(in_addr, vlan_valid, 1);
 141                        MLX5_SET_RA(in_addr, vlan_id, vlan_id);
 142                }
 143
 144                ether_addr_copy(addr_mac, mac);
 145                MLX5_SET_RA(in_addr, roce_version, roce_version);
 146                MLX5_SET_RA(in_addr, roce_l3_type, roce_l3_type);
 147                memcpy(addr_l3_addr, gid, gidsz);
 148        }
 149
 150        if (MLX5_CAP_GEN(dev, num_vhca_ports) > 0)
 151                MLX5_SET(set_roce_address_in, in, vhca_port_num, port_num);
 152
 153        MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 154        MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 155        return mlx5_cmd_exec_in(dev, set_roce_address, in);
 156}
 157EXPORT_SYMBOL(mlx5_core_roce_gid_set);
 158