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4#ifndef _IONIC_IF_H_
5#define _IONIC_IF_H_
6
7#define IONIC_DEV_INFO_SIGNATURE 0x44455649
8#define IONIC_DEV_INFO_VERSION 1
9#define IONIC_IFNAMSIZ 16
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12
13
14enum ionic_cmd_opcode {
15 IONIC_CMD_NOP = 0,
16
17
18 IONIC_CMD_IDENTIFY = 1,
19 IONIC_CMD_INIT = 2,
20 IONIC_CMD_RESET = 3,
21 IONIC_CMD_GETATTR = 4,
22 IONIC_CMD_SETATTR = 5,
23
24
25 IONIC_CMD_PORT_IDENTIFY = 10,
26 IONIC_CMD_PORT_INIT = 11,
27 IONIC_CMD_PORT_RESET = 12,
28 IONIC_CMD_PORT_GETATTR = 13,
29 IONIC_CMD_PORT_SETATTR = 14,
30
31
32 IONIC_CMD_LIF_IDENTIFY = 20,
33 IONIC_CMD_LIF_INIT = 21,
34 IONIC_CMD_LIF_RESET = 22,
35 IONIC_CMD_LIF_GETATTR = 23,
36 IONIC_CMD_LIF_SETATTR = 24,
37
38 IONIC_CMD_RX_MODE_SET = 30,
39 IONIC_CMD_RX_FILTER_ADD = 31,
40 IONIC_CMD_RX_FILTER_DEL = 32,
41
42
43 IONIC_CMD_Q_IDENTIFY = 39,
44 IONIC_CMD_Q_INIT = 40,
45 IONIC_CMD_Q_CONTROL = 41,
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47
48 IONIC_CMD_RDMA_RESET_LIF = 50,
49 IONIC_CMD_RDMA_CREATE_EQ = 51,
50 IONIC_CMD_RDMA_CREATE_CQ = 52,
51 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
52
53
54 IONIC_CMD_VF_GETATTR = 60,
55 IONIC_CMD_VF_SETATTR = 61,
56
57
58 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
59 IONIC_CMD_QOS_CLASS_INIT = 241,
60 IONIC_CMD_QOS_CLASS_RESET = 242,
61 IONIC_CMD_QOS_CLASS_UPDATE = 243,
62 IONIC_CMD_QOS_CLEAR_STATS = 244,
63 IONIC_CMD_QOS_RESET = 245,
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65
66 IONIC_CMD_FW_DOWNLOAD = 252,
67 IONIC_CMD_FW_CONTROL = 253,
68 IONIC_CMD_FW_DOWNLOAD_V1 = 254,
69 IONIC_CMD_FW_CONTROL_V1 = 255,
70};
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74
75enum ionic_status_code {
76 IONIC_RC_SUCCESS = 0,
77 IONIC_RC_EVERSION = 1,
78 IONIC_RC_EOPCODE = 2,
79 IONIC_RC_EIO = 3,
80 IONIC_RC_EPERM = 4,
81 IONIC_RC_EQID = 5,
82 IONIC_RC_EQTYPE = 6,
83 IONIC_RC_ENOENT = 7,
84 IONIC_RC_EINTR = 8,
85 IONIC_RC_EAGAIN = 9,
86 IONIC_RC_ENOMEM = 10,
87 IONIC_RC_EFAULT = 11,
88 IONIC_RC_EBUSY = 12,
89 IONIC_RC_EEXIST = 13,
90 IONIC_RC_EINVAL = 14,
91 IONIC_RC_ENOSPC = 15,
92 IONIC_RC_ERANGE = 16,
93 IONIC_RC_BAD_ADDR = 17,
94 IONIC_RC_DEV_CMD = 18,
95 IONIC_RC_ENOSUPP = 19,
96 IONIC_RC_ERROR = 29,
97 IONIC_RC_ERDMA = 30,
98 IONIC_RC_EVFID = 31,
99 IONIC_RC_EBAD_FW = 32,
100};
101
102enum ionic_notifyq_opcode {
103 IONIC_EVENT_LINK_CHANGE = 1,
104 IONIC_EVENT_RESET = 2,
105 IONIC_EVENT_HEARTBEAT = 3,
106 IONIC_EVENT_LOG = 4,
107 IONIC_EVENT_XCVR = 5,
108};
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116struct ionic_admin_cmd {
117 u8 opcode;
118 u8 rsvd;
119 __le16 lif_index;
120 u8 cmd_data[60];
121};
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131struct ionic_admin_comp {
132 u8 status;
133 u8 rsvd;
134 __le16 comp_index;
135 u8 cmd_data[11];
136 u8 color;
137#define IONIC_COMP_COLOR_MASK 0x80
138};
139
140static inline u8 color_match(u8 color, u8 done_color)
141{
142 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
143}
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149struct ionic_nop_cmd {
150 u8 opcode;
151 u8 rsvd[63];
152};
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158struct ionic_nop_comp {
159 u8 status;
160 u8 rsvd[15];
161};
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168struct ionic_dev_init_cmd {
169 u8 opcode;
170 u8 type;
171 u8 rsvd[62];
172};
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178struct ionic_dev_init_comp {
179 u8 status;
180 u8 rsvd[15];
181};
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187struct ionic_dev_reset_cmd {
188 u8 opcode;
189 u8 rsvd[63];
190};
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196struct ionic_dev_reset_comp {
197 u8 status;
198 u8 rsvd[15];
199};
200
201#define IONIC_IDENTITY_VERSION_1 1
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208struct ionic_dev_identify_cmd {
209 u8 opcode;
210 u8 ver;
211 u8 rsvd[62];
212};
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219struct ionic_dev_identify_comp {
220 u8 status;
221 u8 ver;
222 u8 rsvd[14];
223};
224
225enum ionic_os_type {
226 IONIC_OS_TYPE_LINUX = 1,
227 IONIC_OS_TYPE_WIN = 2,
228 IONIC_OS_TYPE_DPDK = 3,
229 IONIC_OS_TYPE_FREEBSD = 4,
230 IONIC_OS_TYPE_IPXE = 5,
231 IONIC_OS_TYPE_ESXI = 6,
232};
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243union ionic_drv_identity {
244 struct {
245 __le32 os_type;
246 __le32 os_dist;
247 char os_dist_str[128];
248 __le32 kernel_ver;
249 char kernel_ver_str[32];
250 char driver_ver_str[32];
251 };
252 __le32 words[478];
253};
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273union ionic_dev_identity {
274 struct {
275 u8 version;
276 u8 type;
277 u8 rsvd[2];
278 u8 nports;
279 u8 rsvd2[3];
280 __le32 nlifs;
281 __le32 nintrs;
282 __le32 ndbpgs_per_lif;
283 __le32 intr_coal_mult;
284 __le32 intr_coal_div;
285 __le32 eq_count;
286 };
287 __le32 words[478];
288};
289
290enum ionic_lif_type {
291 IONIC_LIF_TYPE_CLASSIC = 0,
292 IONIC_LIF_TYPE_MACVLAN = 1,
293 IONIC_LIF_TYPE_NETQUEUE = 2,
294};
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302struct ionic_lif_identify_cmd {
303 u8 opcode;
304 u8 type;
305 u8 ver;
306 u8 rsvd[61];
307};
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314struct ionic_lif_identify_comp {
315 u8 status;
316 u8 ver;
317 u8 rsvd2[14];
318};
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325enum ionic_lif_capability {
326 IONIC_LIF_CAP_ETH = BIT(0),
327 IONIC_LIF_CAP_RDMA = BIT(1),
328};
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339enum ionic_logical_qtype {
340 IONIC_QTYPE_ADMINQ = 0,
341 IONIC_QTYPE_NOTIFYQ = 1,
342 IONIC_QTYPE_RXQ = 2,
343 IONIC_QTYPE_TXQ = 3,
344 IONIC_QTYPE_EQ = 4,
345 IONIC_QTYPE_MAX = 16,
346};
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354struct ionic_lif_logical_qtype {
355 u8 qtype;
356 u8 rsvd[3];
357 __le32 qid_count;
358 __le32 qid_base;
359};
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367enum ionic_lif_state {
368 IONIC_LIF_QUIESCE = 0,
369 IONIC_LIF_ENABLE = 1,
370 IONIC_LIF_DISABLE = 2,
371};
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383union ionic_lif_config {
384 struct {
385 u8 state;
386 u8 rsvd[3];
387 char name[IONIC_IFNAMSIZ];
388 __le32 mtu;
389 u8 mac[6];
390 __le16 vlan;
391 __le64 features;
392 __le32 queue_count[IONIC_QTYPE_MAX];
393 } __packed;
394 __le32 words[64];
395};
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429union ionic_lif_identity {
430 struct {
431 __le64 capabilities;
432
433 struct {
434 u8 version;
435 u8 rsvd[3];
436 __le32 max_ucast_filters;
437 __le32 max_mcast_filters;
438 __le16 rss_ind_tbl_sz;
439 __le32 min_frame_size;
440 __le32 max_frame_size;
441 u8 rsvd2[106];
442 union ionic_lif_config config;
443 } __packed eth;
444
445 struct {
446 u8 version;
447 u8 qp_opcodes;
448 u8 admin_opcodes;
449 u8 rsvd;
450 __le32 npts_per_lif;
451 __le32 nmrs_per_lif;
452 __le32 nahs_per_lif;
453 u8 max_stride;
454 u8 cl_stride;
455 u8 pte_stride;
456 u8 rrq_stride;
457 u8 rsq_stride;
458 u8 dcqcn_profiles;
459 u8 rsvd_dimensions[10];
460 struct ionic_lif_logical_qtype aq_qtype;
461 struct ionic_lif_logical_qtype sq_qtype;
462 struct ionic_lif_logical_qtype rq_qtype;
463 struct ionic_lif_logical_qtype cq_qtype;
464 struct ionic_lif_logical_qtype eq_qtype;
465 } __packed rdma;
466 } __packed;
467 __le32 words[478];
468};
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477struct ionic_lif_init_cmd {
478 u8 opcode;
479 u8 type;
480 __le16 index;
481 __le32 rsvd;
482 __le64 info_pa;
483 u8 rsvd2[48];
484};
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491struct ionic_lif_init_comp {
492 u8 status;
493 u8 rsvd;
494 __le16 hw_index;
495 u8 rsvd2[12];
496};
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505struct ionic_q_identify_cmd {
506 u8 opcode;
507 u8 rsvd;
508 __le16 lif_type;
509 u8 type;
510 u8 ver;
511 u8 rsvd2[58];
512};
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520struct ionic_q_identify_comp {
521 u8 status;
522 u8 rsvd;
523 __le16 comp_index;
524 u8 ver;
525 u8 rsvd2[11];
526};
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539union ionic_q_identity {
540 struct {
541 u8 version;
542 u8 supported;
543 u8 rsvd[6];
544#define IONIC_QIDENT_F_CQ 0x01
545#define IONIC_QIDENT_F_SG 0x02
546#define IONIC_QIDENT_F_EQ 0x04
547#define IONIC_QIDENT_F_CMB 0x08
548 __le64 features;
549 __le16 desc_sz;
550 __le16 comp_sz;
551 __le16 sg_desc_sz;
552 __le16 max_sg_elems;
553 __le16 sg_desc_stride;
554 };
555 __le32 words[478];
556};
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589struct ionic_q_init_cmd {
590 u8 opcode;
591 u8 rsvd;
592 __le16 lif_index;
593 u8 type;
594 u8 ver;
595 u8 rsvd1[2];
596 __le32 index;
597 __le16 pid;
598 __le16 intr_index;
599 __le16 flags;
600#define IONIC_QINIT_F_IRQ 0x01
601#define IONIC_QINIT_F_ENA 0x02
602#define IONIC_QINIT_F_SG 0x04
603#define IONIC_QINIT_F_EQ 0x08
604#define IONIC_QINIT_F_CMB 0x10
605#define IONIC_QINIT_F_DEBUG 0x80
606 u8 cos;
607 u8 ring_size;
608 __le64 ring_base;
609 __le64 cq_ring_base;
610 __le64 sg_ring_base;
611 u8 rsvd2[20];
612} __packed;
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622struct ionic_q_init_comp {
623 u8 status;
624 u8 rsvd;
625 __le16 comp_index;
626 __le32 hw_index;
627 u8 hw_type;
628 u8 rsvd2[6];
629 u8 color;
630};
631
632
633#define IONIC_ADDR_LEN 52
634#define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
635
636enum ionic_txq_desc_opcode {
637 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
638 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
639 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
640 IONIC_TXQ_DESC_OPCODE_TSO = 3,
641};
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754struct ionic_txq_desc {
755 __le64 cmd;
756#define IONIC_TXQ_DESC_OPCODE_MASK 0xf
757#define IONIC_TXQ_DESC_OPCODE_SHIFT 4
758#define IONIC_TXQ_DESC_FLAGS_MASK 0xf
759#define IONIC_TXQ_DESC_FLAGS_SHIFT 0
760#define IONIC_TXQ_DESC_NSGE_MASK 0xf
761#define IONIC_TXQ_DESC_NSGE_SHIFT 8
762#define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
763#define IONIC_TXQ_DESC_ADDR_SHIFT 12
764
765
766#define IONIC_TXQ_DESC_FLAG_VLAN 0x1
767#define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
768
769
770#define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
771#define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
772
773
774#define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
775#define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
776
777 __le16 len;
778 union {
779 __le16 vlan_tci;
780 __le16 hword0;
781 };
782 union {
783 __le16 csum_start;
784 __le16 hdr_len;
785 __le16 hword1;
786 };
787 union {
788 __le16 csum_offset;
789 __le16 mss;
790 __le16 hword2;
791 };
792};
793
794static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
795 u8 nsge, u64 addr)
796{
797 u64 cmd;
798
799 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
800 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
801 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
802 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
803
804 return cmd;
805};
806
807static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
808 u8 *nsge, u64 *addr)
809{
810 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
811 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
812 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
813 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
814};
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821struct ionic_txq_sg_elem {
822 __le64 addr;
823 __le16 len;
824 __le16 rsvd[3];
825};
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831struct ionic_txq_sg_desc {
832#define IONIC_TX_MAX_SG_ELEMS 8
833#define IONIC_TX_SG_DESC_STRIDE 8
834 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
835};
836
837struct ionic_txq_sg_desc_v1 {
838#define IONIC_TX_MAX_SG_ELEMS_V1 15
839#define IONIC_TX_SG_DESC_STRIDE_V1 16
840 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
841};
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849struct ionic_txq_comp {
850 u8 status;
851 u8 rsvd;
852 __le16 comp_index;
853 u8 rsvd2[11];
854 u8 color;
855};
856
857enum ionic_rxq_desc_opcode {
858 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
859 IONIC_RXQ_DESC_OPCODE_SG = 1,
860};
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875struct ionic_rxq_desc {
876 u8 opcode;
877 u8 rsvd[5];
878 __le16 len;
879 __le64 addr;
880};
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887struct ionic_rxq_sg_elem {
888 __le64 addr;
889 __le16 len;
890 __le16 rsvd[3];
891};
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897struct ionic_rxq_sg_desc {
898#define IONIC_RX_MAX_SG_ELEMS 8
899#define IONIC_RX_SG_DESC_STRIDE 8
900 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
901};
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963struct ionic_rxq_comp {
964 u8 status;
965 u8 num_sg_elems;
966 __le16 comp_index;
967 __le32 rss_hash;
968 __le16 csum;
969 __le16 vlan_tci;
970 __le16 len;
971 u8 csum_flags;
972#define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
973#define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
974#define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
975#define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
976#define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
977#define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
978#define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
979#define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
980 u8 pkt_type_color;
981#define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
982};
983
984enum ionic_pkt_type {
985 IONIC_PKT_TYPE_NON_IP = 0x000,
986 IONIC_PKT_TYPE_IPV4 = 0x001,
987 IONIC_PKT_TYPE_IPV4_TCP = 0x003,
988 IONIC_PKT_TYPE_IPV4_UDP = 0x005,
989 IONIC_PKT_TYPE_IPV6 = 0x008,
990 IONIC_PKT_TYPE_IPV6_TCP = 0x018,
991 IONIC_PKT_TYPE_IPV6_UDP = 0x028,
992
993 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
994 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
995 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
996 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
997 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
998 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
999 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
1000};
1001
1002enum ionic_eth_hw_features {
1003 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
1004 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
1005 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
1006 IONIC_ETH_HW_RX_HASH = BIT(3),
1007 IONIC_ETH_HW_RX_CSUM = BIT(4),
1008 IONIC_ETH_HW_TX_SG = BIT(5),
1009 IONIC_ETH_HW_RX_SG = BIT(6),
1010 IONIC_ETH_HW_TX_CSUM = BIT(7),
1011 IONIC_ETH_HW_TSO = BIT(8),
1012 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
1013 IONIC_ETH_HW_TSO_ECN = BIT(10),
1014 IONIC_ETH_HW_TSO_GRE = BIT(11),
1015 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
1016 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
1017 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
1018 IONIC_ETH_HW_TSO_UDP = BIT(15),
1019 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
1020 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17),
1021 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
1022 IONIC_ETH_HW_TSO_GENEVE = BIT(19)
1023};
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1033struct ionic_q_control_cmd {
1034 u8 opcode;
1035 u8 type;
1036 __le16 lif_index;
1037 __le32 index;
1038 u8 oper;
1039 u8 rsvd[55];
1040};
1041
1042typedef struct ionic_admin_comp ionic_q_control_comp;
1043
1044enum q_control_oper {
1045 IONIC_Q_DISABLE = 0,
1046 IONIC_Q_ENABLE = 1,
1047 IONIC_Q_HANG_RESET = 2,
1048};
1049
1050
1051
1052
1053
1054
1055
1056enum ionic_phy_type {
1057 IONIC_PHY_TYPE_NONE = 0,
1058 IONIC_PHY_TYPE_COPPER = 1,
1059 IONIC_PHY_TYPE_FIBER = 2,
1060};
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070enum ionic_xcvr_state {
1071 IONIC_XCVR_STATE_REMOVED = 0,
1072 IONIC_XCVR_STATE_INSERTED = 1,
1073 IONIC_XCVR_STATE_PENDING = 2,
1074 IONIC_XCVR_STATE_SPROM_READ = 3,
1075 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
1076};
1077
1078
1079
1080
1081enum ionic_xcvr_pid {
1082 IONIC_XCVR_PID_UNKNOWN = 0,
1083
1084
1085 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
1086 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
1087 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
1088 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
1089 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
1090
1091
1092 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
1093 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
1094 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
1095 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
1096 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
1097 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1098 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1099 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1100 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1101 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
1102 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
1103 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
1104 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
1105 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
1106 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
1107 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
1108 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
1109 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
1110 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
1111 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
1112 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
1113 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
1114};
1115
1116
1117
1118
1119
1120
1121
1122enum ionic_port_type {
1123 IONIC_PORT_TYPE_NONE = 0,
1124 IONIC_PORT_TYPE_ETH = 1,
1125 IONIC_PORT_TYPE_MGMT = 2,
1126};
1127
1128
1129
1130
1131
1132
1133
1134enum ionic_port_admin_state {
1135 IONIC_PORT_ADMIN_STATE_NONE = 0,
1136 IONIC_PORT_ADMIN_STATE_DOWN = 1,
1137 IONIC_PORT_ADMIN_STATE_UP = 2,
1138};
1139
1140
1141
1142
1143
1144
1145
1146enum ionic_port_oper_status {
1147 IONIC_PORT_OPER_STATUS_NONE = 0,
1148 IONIC_PORT_OPER_STATUS_UP = 1,
1149 IONIC_PORT_OPER_STATUS_DOWN = 2,
1150};
1151
1152
1153
1154
1155
1156
1157
1158enum ionic_port_fec_type {
1159 IONIC_PORT_FEC_TYPE_NONE = 0,
1160 IONIC_PORT_FEC_TYPE_FC = 1,
1161 IONIC_PORT_FEC_TYPE_RS = 2,
1162};
1163
1164
1165
1166
1167
1168
1169
1170enum ionic_port_pause_type {
1171 IONIC_PORT_PAUSE_TYPE_NONE = 0,
1172 IONIC_PORT_PAUSE_TYPE_LINK = 1,
1173 IONIC_PORT_PAUSE_TYPE_PFC = 2,
1174};
1175
1176
1177
1178
1179
1180
1181
1182enum ionic_port_loopback_mode {
1183 IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1184 IONIC_PORT_LOOPBACK_MODE_MAC = 1,
1185 IONIC_PORT_LOOPBACK_MODE_PHY = 2,
1186};
1187
1188
1189
1190
1191
1192
1193
1194
1195struct ionic_xcvr_status {
1196 u8 state;
1197 u8 phy;
1198 __le16 pid;
1199 u8 sprom[256];
1200};
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212union ionic_port_config {
1213 struct {
1214#define IONIC_SPEED_100G 100000
1215#define IONIC_SPEED_50G 50000
1216#define IONIC_SPEED_40G 40000
1217#define IONIC_SPEED_25G 25000
1218#define IONIC_SPEED_10G 10000
1219#define IONIC_SPEED_1G 1000
1220 __le32 speed;
1221 __le32 mtu;
1222 u8 state;
1223 u8 an_enable;
1224 u8 fec_type;
1225#define IONIC_PAUSE_TYPE_MASK 0x0f
1226#define IONIC_PAUSE_FLAGS_MASK 0xf0
1227#define IONIC_PAUSE_F_TX 0x10
1228#define IONIC_PAUSE_F_RX 0x20
1229 u8 pause_type;
1230 u8 loopback_mode;
1231 };
1232 __le32 words[64];
1233};
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244struct ionic_port_status {
1245 __le32 id;
1246 __le32 speed;
1247 u8 status;
1248 __le16 link_down_count;
1249 u8 fec_type;
1250 u8 rsvd[48];
1251 struct ionic_xcvr_status xcvr;
1252} __packed;
1253
1254
1255
1256
1257
1258
1259
1260struct ionic_port_identify_cmd {
1261 u8 opcode;
1262 u8 index;
1263 u8 ver;
1264 u8 rsvd[61];
1265};
1266
1267
1268
1269
1270
1271
1272struct ionic_port_identify_comp {
1273 u8 status;
1274 u8 ver;
1275 u8 rsvd[14];
1276};
1277
1278
1279
1280
1281
1282
1283
1284struct ionic_port_init_cmd {
1285 u8 opcode;
1286 u8 index;
1287 u8 rsvd[6];
1288 __le64 info_pa;
1289 u8 rsvd2[48];
1290};
1291
1292
1293
1294
1295
1296struct ionic_port_init_comp {
1297 u8 status;
1298 u8 rsvd[15];
1299};
1300
1301
1302
1303
1304
1305
1306struct ionic_port_reset_cmd {
1307 u8 opcode;
1308 u8 index;
1309 u8 rsvd[62];
1310};
1311
1312
1313
1314
1315
1316struct ionic_port_reset_comp {
1317 u8 status;
1318 u8 rsvd[15];
1319};
1320
1321
1322
1323
1324
1325enum ionic_stats_ctl_cmd {
1326 IONIC_STATS_CTL_RESET = 0,
1327};
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340enum ionic_port_attr {
1341 IONIC_PORT_ATTR_STATE = 0,
1342 IONIC_PORT_ATTR_SPEED = 1,
1343 IONIC_PORT_ATTR_MTU = 2,
1344 IONIC_PORT_ATTR_AUTONEG = 3,
1345 IONIC_PORT_ATTR_FEC = 4,
1346 IONIC_PORT_ATTR_PAUSE = 5,
1347 IONIC_PORT_ATTR_LOOPBACK = 6,
1348 IONIC_PORT_ATTR_STATS_CTRL = 7,
1349};
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365struct ionic_port_setattr_cmd {
1366 u8 opcode;
1367 u8 index;
1368 u8 attr;
1369 u8 rsvd;
1370 union {
1371 u8 state;
1372 __le32 speed;
1373 __le32 mtu;
1374 u8 an_enable;
1375 u8 fec_type;
1376 u8 pause_type;
1377 u8 loopback_mode;
1378 u8 stats_ctl;
1379 u8 rsvd2[60];
1380 };
1381};
1382
1383
1384
1385
1386
1387
1388struct ionic_port_setattr_comp {
1389 u8 status;
1390 u8 rsvd[14];
1391 u8 color;
1392};
1393
1394
1395
1396
1397
1398
1399
1400struct ionic_port_getattr_cmd {
1401 u8 opcode;
1402 u8 index;
1403 u8 attr;
1404 u8 rsvd[61];
1405};
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419struct ionic_port_getattr_comp {
1420 u8 status;
1421 u8 rsvd[3];
1422 union {
1423 u8 state;
1424 __le32 speed;
1425 __le32 mtu;
1426 u8 an_enable;
1427 u8 fec_type;
1428 u8 pause_type;
1429 u8 loopback_mode;
1430 u8 rsvd2[11];
1431 } __packed;
1432 u8 color;
1433};
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443struct ionic_lif_status {
1444 __le64 eid;
1445 u8 port_num;
1446 u8 rsvd;
1447 __le16 link_status;
1448 __le32 link_speed;
1449 __le16 link_down_count;
1450 u8 rsvd2[46];
1451};
1452
1453
1454
1455
1456
1457
1458struct ionic_lif_reset_cmd {
1459 u8 opcode;
1460 u8 rsvd;
1461 __le16 index;
1462 __le32 rsvd2[15];
1463};
1464
1465typedef struct ionic_admin_comp ionic_lif_reset_comp;
1466
1467enum ionic_dev_state {
1468 IONIC_DEV_DISABLE = 0,
1469 IONIC_DEV_ENABLE = 1,
1470 IONIC_DEV_HANG_RESET = 2,
1471};
1472
1473
1474
1475
1476
1477
1478
1479enum ionic_dev_attr {
1480 IONIC_DEV_ATTR_STATE = 0,
1481 IONIC_DEV_ATTR_NAME = 1,
1482 IONIC_DEV_ATTR_FEATURES = 2,
1483};
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493struct ionic_dev_setattr_cmd {
1494 u8 opcode;
1495 u8 attr;
1496 __le16 rsvd;
1497 union {
1498 u8 state;
1499 char name[IONIC_IFNAMSIZ];
1500 __le64 features;
1501 u8 rsvd2[60];
1502 } __packed;
1503};
1504
1505
1506
1507
1508
1509
1510
1511struct ionic_dev_setattr_comp {
1512 u8 status;
1513 u8 rsvd[3];
1514 union {
1515 __le64 features;
1516 u8 rsvd2[11];
1517 } __packed;
1518 u8 color;
1519};
1520
1521
1522
1523
1524
1525
1526struct ionic_dev_getattr_cmd {
1527 u8 opcode;
1528 u8 attr;
1529 u8 rsvd[62];
1530};
1531
1532
1533
1534
1535
1536
1537
1538struct ionic_dev_getattr_comp {
1539 u8 status;
1540 u8 rsvd[3];
1541 union {
1542 __le64 features;
1543 u8 rsvd2[11];
1544 } __packed;
1545 u8 color;
1546};
1547
1548
1549
1550
1551#define IONIC_RSS_HASH_KEY_SIZE 40
1552
1553enum ionic_rss_hash_types {
1554 IONIC_RSS_TYPE_IPV4 = BIT(0),
1555 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1556 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1557 IONIC_RSS_TYPE_IPV6 = BIT(3),
1558 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1559 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1560};
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572enum ionic_lif_attr {
1573 IONIC_LIF_ATTR_STATE = 0,
1574 IONIC_LIF_ATTR_NAME = 1,
1575 IONIC_LIF_ATTR_MTU = 2,
1576 IONIC_LIF_ATTR_MAC = 3,
1577 IONIC_LIF_ATTR_FEATURES = 4,
1578 IONIC_LIF_ATTR_RSS = 5,
1579 IONIC_LIF_ATTR_STATS_CTRL = 6,
1580};
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598struct ionic_lif_setattr_cmd {
1599 u8 opcode;
1600 u8 attr;
1601 __le16 index;
1602 union {
1603 u8 state;
1604 char name[IONIC_IFNAMSIZ];
1605 __le32 mtu;
1606 u8 mac[6];
1607 __le64 features;
1608 struct {
1609 __le16 types;
1610 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1611 u8 rsvd[6];
1612 __le64 addr;
1613 } rss;
1614 u8 stats_ctl;
1615 u8 rsvd[60];
1616 } __packed;
1617};
1618
1619
1620
1621
1622
1623
1624
1625
1626struct ionic_lif_setattr_comp {
1627 u8 status;
1628 u8 rsvd;
1629 __le16 comp_index;
1630 union {
1631 __le64 features;
1632 u8 rsvd2[11];
1633 } __packed;
1634 u8 color;
1635};
1636
1637
1638
1639
1640
1641
1642
1643struct ionic_lif_getattr_cmd {
1644 u8 opcode;
1645 u8 attr;
1646 __le16 index;
1647 u8 rsvd[60];
1648};
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661struct ionic_lif_getattr_comp {
1662 u8 status;
1663 u8 rsvd;
1664 __le16 comp_index;
1665 union {
1666 u8 state;
1667 __le32 mtu;
1668 u8 mac[6];
1669 __le64 features;
1670 u8 rsvd2[11];
1671 } __packed;
1672 u8 color;
1673};
1674
1675enum ionic_rx_mode {
1676 IONIC_RX_MODE_F_UNICAST = BIT(0),
1677 IONIC_RX_MODE_F_MULTICAST = BIT(1),
1678 IONIC_RX_MODE_F_BROADCAST = BIT(2),
1679 IONIC_RX_MODE_F_PROMISC = BIT(3),
1680 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
1681 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
1682};
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696struct ionic_rx_mode_set_cmd {
1697 u8 opcode;
1698 u8 rsvd;
1699 __le16 lif_index;
1700 __le16 rx_mode;
1701 __le16 rsvd2[29];
1702};
1703
1704typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1705
1706enum ionic_rx_filter_match_type {
1707 IONIC_RX_FILTER_MATCH_VLAN = 0,
1708 IONIC_RX_FILTER_MATCH_MAC,
1709 IONIC_RX_FILTER_MATCH_MAC_VLAN,
1710};
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727struct ionic_rx_filter_add_cmd {
1728 u8 opcode;
1729 u8 qtype;
1730 __le16 lif_index;
1731 __le32 qid;
1732 __le16 match;
1733 union {
1734 struct {
1735 __le16 vlan;
1736 } vlan;
1737 struct {
1738 u8 addr[6];
1739 } mac;
1740 struct {
1741 __le16 vlan;
1742 u8 addr[6];
1743 } mac_vlan;
1744 u8 rsvd[54];
1745 };
1746};
1747
1748
1749
1750
1751
1752
1753
1754
1755struct ionic_rx_filter_add_comp {
1756 u8 status;
1757 u8 rsvd;
1758 __le16 comp_index;
1759 __le32 filter_id;
1760 u8 rsvd2[7];
1761 u8 color;
1762};
1763
1764
1765
1766
1767
1768
1769
1770struct ionic_rx_filter_del_cmd {
1771 u8 opcode;
1772 u8 rsvd;
1773 __le16 lif_index;
1774 __le32 filter_id;
1775 u8 rsvd2[56];
1776};
1777
1778typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1779
1780enum ionic_vf_attr {
1781 IONIC_VF_ATTR_SPOOFCHK = 1,
1782 IONIC_VF_ATTR_TRUST = 2,
1783 IONIC_VF_ATTR_MAC = 3,
1784 IONIC_VF_ATTR_LINKSTATE = 4,
1785 IONIC_VF_ATTR_VLAN = 5,
1786 IONIC_VF_ATTR_RATE = 6,
1787 IONIC_VF_ATTR_STATSADDR = 7,
1788};
1789
1790
1791
1792
1793
1794
1795
1796enum ionic_vf_link_status {
1797 IONIC_VF_LINK_STATUS_AUTO = 0,
1798 IONIC_VF_LINK_STATUS_UP = 1,
1799 IONIC_VF_LINK_STATUS_DOWN = 2,
1800};
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815struct ionic_vf_setattr_cmd {
1816 u8 opcode;
1817 u8 attr;
1818 __le16 vf_index;
1819 union {
1820 u8 macaddr[6];
1821 __le16 vlanid;
1822 __le32 maxrate;
1823 u8 spoofchk;
1824 u8 trust;
1825 u8 linkstate;
1826 __le64 stats_pa;
1827 u8 pad[60];
1828 } __packed;
1829};
1830
1831struct ionic_vf_setattr_comp {
1832 u8 status;
1833 u8 attr;
1834 __le16 vf_index;
1835 __le16 comp_index;
1836 u8 rsvd[9];
1837 u8 color;
1838};
1839
1840
1841
1842
1843
1844
1845
1846struct ionic_vf_getattr_cmd {
1847 u8 opcode;
1848 u8 attr;
1849 __le16 vf_index;
1850 u8 rsvd[60];
1851};
1852
1853struct ionic_vf_getattr_comp {
1854 u8 status;
1855 u8 attr;
1856 __le16 vf_index;
1857 union {
1858 u8 macaddr[6];
1859 __le16 vlanid;
1860 __le32 maxrate;
1861 u8 spoofchk;
1862 u8 trust;
1863 u8 linkstate;
1864 __le64 stats_pa;
1865 u8 pad[11];
1866 } __packed;
1867 u8 color;
1868};
1869
1870
1871
1872
1873
1874
1875
1876struct ionic_qos_identify_cmd {
1877 u8 opcode;
1878 u8 ver;
1879 u8 rsvd[62];
1880};
1881
1882
1883
1884
1885
1886
1887struct ionic_qos_identify_comp {
1888 u8 status;
1889 u8 ver;
1890 u8 rsvd[14];
1891};
1892
1893#define IONIC_QOS_TC_MAX 8
1894#define IONIC_QOS_ALL_TC 0xFF
1895
1896#define IONIC_QOS_CLASS_MAX 7
1897#define IONIC_QOS_PCP_MAX 8
1898#define IONIC_QOS_CLASS_NAME_SZ 32
1899#define IONIC_QOS_DSCP_MAX 64
1900#define IONIC_QOS_ALL_PCP 0xFF
1901#define IONIC_DSCP_BLOCK_SIZE 8
1902
1903
1904
1905
1906enum ionic_qos_class {
1907 IONIC_QOS_CLASS_DEFAULT = 0,
1908 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
1909 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
1910 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
1911 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
1912 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
1913 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
1914};
1915
1916
1917
1918
1919
1920
1921
1922enum ionic_qos_class_type {
1923 IONIC_QOS_CLASS_TYPE_NONE = 0,
1924 IONIC_QOS_CLASS_TYPE_PCP = 1,
1925 IONIC_QOS_CLASS_TYPE_DSCP = 2,
1926};
1927
1928
1929
1930
1931
1932
1933enum ionic_qos_sched_type {
1934 IONIC_QOS_SCHED_TYPE_STRICT = 0,
1935 IONIC_QOS_SCHED_TYPE_DWRR = 1,
1936};
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960union ionic_qos_config {
1961 struct {
1962#define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
1963#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
1964
1965#define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
1966#define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
1967
1968#define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
1969 u8 flags;
1970 u8 sched_type;
1971 u8 class_type;
1972 u8 pause_type;
1973 char name[IONIC_QOS_CLASS_NAME_SZ];
1974 __le32 mtu;
1975
1976 u8 pfc_cos;
1977
1978 union {
1979 u8 dwrr_weight;
1980 __le64 strict_rlmt;
1981 };
1982
1983
1984 union {
1985 u8 rw_dot1q_pcp;
1986 u8 rw_ip_dscp;
1987 };
1988
1989 union {
1990 u8 dot1q_pcp;
1991 struct {
1992 u8 ndscp;
1993 u8 ip_dscp[IONIC_QOS_DSCP_MAX];
1994 };
1995 };
1996 };
1997 __le32 words[64];
1998};
1999
2000
2001
2002
2003
2004
2005
2006
2007union ionic_qos_identity {
2008 struct {
2009 u8 version;
2010 u8 type;
2011 u8 rsvd[62];
2012 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2013 };
2014 __le32 words[478];
2015};
2016
2017
2018
2019
2020
2021
2022
2023struct ionic_qos_init_cmd {
2024 u8 opcode;
2025 u8 group;
2026 u8 rsvd[6];
2027 __le64 info_pa;
2028 u8 rsvd1[48];
2029};
2030
2031typedef struct ionic_admin_comp ionic_qos_init_comp;
2032
2033
2034
2035
2036
2037
2038struct ionic_qos_reset_cmd {
2039 u8 opcode;
2040 u8 group;
2041 u8 rsvd[62];
2042};
2043
2044
2045
2046
2047
2048struct ionic_qos_clear_stats_cmd {
2049 u8 opcode;
2050 u8 group_bitmap;
2051 u8 rsvd[62];
2052};
2053
2054typedef struct ionic_admin_comp ionic_qos_reset_comp;
2055
2056
2057
2058
2059
2060
2061
2062
2063struct ionic_fw_download_cmd {
2064 u8 opcode;
2065 u8 rsvd[3];
2066 __le32 offset;
2067 __le64 addr;
2068 __le32 length;
2069};
2070
2071typedef struct ionic_admin_comp ionic_fw_download_comp;
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083enum ionic_fw_control_oper {
2084 IONIC_FW_RESET = 0,
2085 IONIC_FW_INSTALL = 1,
2086 IONIC_FW_ACTIVATE = 2,
2087 IONIC_FW_INSTALL_ASYNC = 3,
2088 IONIC_FW_INSTALL_STATUS = 4,
2089 IONIC_FW_ACTIVATE_ASYNC = 5,
2090 IONIC_FW_ACTIVATE_STATUS = 6,
2091 IONIC_FW_UPDATE_CLEANUP = 7,
2092};
2093
2094
2095
2096
2097
2098
2099
2100struct ionic_fw_control_cmd {
2101 u8 opcode;
2102 u8 rsvd[3];
2103 u8 oper;
2104 u8 slot;
2105 u8 rsvd1[58];
2106};
2107
2108
2109
2110
2111
2112
2113
2114
2115struct ionic_fw_control_comp {
2116 u8 status;
2117 u8 rsvd;
2118 __le16 comp_index;
2119 u8 slot;
2120 u8 rsvd1[10];
2121 u8 color;
2122};
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137struct ionic_rdma_reset_cmd {
2138 u8 opcode;
2139 u8 rsvd;
2140 __le16 lif_index;
2141 u8 rsvd2[60];
2142};
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172struct ionic_rdma_queue_cmd {
2173 u8 opcode;
2174 u8 rsvd;
2175 __le16 lif_index;
2176 __le32 qid_ver;
2177 __le32 cid;
2178 __le16 dbid;
2179 u8 depth_log2;
2180 u8 stride_log2;
2181 __le64 dma_addr;
2182 u8 rsvd2[40];
2183};
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198struct ionic_notifyq_event {
2199 __le64 eid;
2200 __le16 ecode;
2201 u8 data[54];
2202};
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213struct ionic_link_change_event {
2214 __le64 eid;
2215 __le16 ecode;
2216 __le16 link_status;
2217 __le32 link_speed;
2218 u8 rsvd[48];
2219};
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231struct ionic_reset_event {
2232 __le64 eid;
2233 __le16 ecode;
2234 u8 reset_code;
2235 u8 state;
2236 u8 rsvd[52];
2237};
2238
2239
2240
2241
2242
2243
2244struct ionic_heartbeat_event {
2245 __le64 eid;
2246 __le16 ecode;
2247 u8 rsvd[54];
2248};
2249
2250
2251
2252
2253
2254
2255
2256struct ionic_log_event {
2257 __le64 eid;
2258 __le16 ecode;
2259 u8 data[54];
2260};
2261
2262
2263
2264
2265
2266
2267struct ionic_xcvr_event {
2268 __le64 eid;
2269 __le16 ecode;
2270 u8 rsvd[54];
2271};
2272
2273
2274
2275
2276struct ionic_port_stats {
2277 __le64 frames_rx_ok;
2278 __le64 frames_rx_all;
2279 __le64 frames_rx_bad_fcs;
2280 __le64 frames_rx_bad_all;
2281 __le64 octets_rx_ok;
2282 __le64 octets_rx_all;
2283 __le64 frames_rx_unicast;
2284 __le64 frames_rx_multicast;
2285 __le64 frames_rx_broadcast;
2286 __le64 frames_rx_pause;
2287 __le64 frames_rx_bad_length;
2288 __le64 frames_rx_undersized;
2289 __le64 frames_rx_oversized;
2290 __le64 frames_rx_fragments;
2291 __le64 frames_rx_jabber;
2292 __le64 frames_rx_pripause;
2293 __le64 frames_rx_stomped_crc;
2294 __le64 frames_rx_too_long;
2295 __le64 frames_rx_vlan_good;
2296 __le64 frames_rx_dropped;
2297 __le64 frames_rx_less_than_64b;
2298 __le64 frames_rx_64b;
2299 __le64 frames_rx_65b_127b;
2300 __le64 frames_rx_128b_255b;
2301 __le64 frames_rx_256b_511b;
2302 __le64 frames_rx_512b_1023b;
2303 __le64 frames_rx_1024b_1518b;
2304 __le64 frames_rx_1519b_2047b;
2305 __le64 frames_rx_2048b_4095b;
2306 __le64 frames_rx_4096b_8191b;
2307 __le64 frames_rx_8192b_9215b;
2308 __le64 frames_rx_other;
2309 __le64 frames_tx_ok;
2310 __le64 frames_tx_all;
2311 __le64 frames_tx_bad;
2312 __le64 octets_tx_ok;
2313 __le64 octets_tx_total;
2314 __le64 frames_tx_unicast;
2315 __le64 frames_tx_multicast;
2316 __le64 frames_tx_broadcast;
2317 __le64 frames_tx_pause;
2318 __le64 frames_tx_pripause;
2319 __le64 frames_tx_vlan;
2320 __le64 frames_tx_less_than_64b;
2321 __le64 frames_tx_64b;
2322 __le64 frames_tx_65b_127b;
2323 __le64 frames_tx_128b_255b;
2324 __le64 frames_tx_256b_511b;
2325 __le64 frames_tx_512b_1023b;
2326 __le64 frames_tx_1024b_1518b;
2327 __le64 frames_tx_1519b_2047b;
2328 __le64 frames_tx_2048b_4095b;
2329 __le64 frames_tx_4096b_8191b;
2330 __le64 frames_tx_8192b_9215b;
2331 __le64 frames_tx_other;
2332 __le64 frames_tx_pri_0;
2333 __le64 frames_tx_pri_1;
2334 __le64 frames_tx_pri_2;
2335 __le64 frames_tx_pri_3;
2336 __le64 frames_tx_pri_4;
2337 __le64 frames_tx_pri_5;
2338 __le64 frames_tx_pri_6;
2339 __le64 frames_tx_pri_7;
2340 __le64 frames_rx_pri_0;
2341 __le64 frames_rx_pri_1;
2342 __le64 frames_rx_pri_2;
2343 __le64 frames_rx_pri_3;
2344 __le64 frames_rx_pri_4;
2345 __le64 frames_rx_pri_5;
2346 __le64 frames_rx_pri_6;
2347 __le64 frames_rx_pri_7;
2348 __le64 tx_pripause_0_1us_count;
2349 __le64 tx_pripause_1_1us_count;
2350 __le64 tx_pripause_2_1us_count;
2351 __le64 tx_pripause_3_1us_count;
2352 __le64 tx_pripause_4_1us_count;
2353 __le64 tx_pripause_5_1us_count;
2354 __le64 tx_pripause_6_1us_count;
2355 __le64 tx_pripause_7_1us_count;
2356 __le64 rx_pripause_0_1us_count;
2357 __le64 rx_pripause_1_1us_count;
2358 __le64 rx_pripause_2_1us_count;
2359 __le64 rx_pripause_3_1us_count;
2360 __le64 rx_pripause_4_1us_count;
2361 __le64 rx_pripause_5_1us_count;
2362 __le64 rx_pripause_6_1us_count;
2363 __le64 rx_pripause_7_1us_count;
2364 __le64 rx_pause_1us_count;
2365 __le64 frames_tx_truncated;
2366};
2367
2368struct ionic_mgmt_port_stats {
2369 __le64 frames_rx_ok;
2370 __le64 frames_rx_all;
2371 __le64 frames_rx_bad_fcs;
2372 __le64 frames_rx_bad_all;
2373 __le64 octets_rx_ok;
2374 __le64 octets_rx_all;
2375 __le64 frames_rx_unicast;
2376 __le64 frames_rx_multicast;
2377 __le64 frames_rx_broadcast;
2378 __le64 frames_rx_pause;
2379 __le64 frames_rx_bad_length;
2380 __le64 frames_rx_undersized;
2381 __le64 frames_rx_oversized;
2382 __le64 frames_rx_fragments;
2383 __le64 frames_rx_jabber;
2384 __le64 frames_rx_64b;
2385 __le64 frames_rx_65b_127b;
2386 __le64 frames_rx_128b_255b;
2387 __le64 frames_rx_256b_511b;
2388 __le64 frames_rx_512b_1023b;
2389 __le64 frames_rx_1024b_1518b;
2390 __le64 frames_rx_gt_1518b;
2391 __le64 frames_rx_fifo_full;
2392 __le64 frames_tx_ok;
2393 __le64 frames_tx_all;
2394 __le64 frames_tx_bad;
2395 __le64 octets_tx_ok;
2396 __le64 octets_tx_total;
2397 __le64 frames_tx_unicast;
2398 __le64 frames_tx_multicast;
2399 __le64 frames_tx_broadcast;
2400 __le64 frames_tx_pause;
2401};
2402
2403enum ionic_pb_buffer_drop_stats {
2404 IONIC_BUFFER_INTRINSIC_DROP = 0,
2405 IONIC_BUFFER_DISCARDED,
2406 IONIC_BUFFER_ADMITTED,
2407 IONIC_BUFFER_OUT_OF_CELLS_DROP,
2408 IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
2409 IONIC_BUFFER_OUT_OF_CREDIT_DROP,
2410 IONIC_BUFFER_TRUNCATION_DROP,
2411 IONIC_BUFFER_PORT_DISABLED_DROP,
2412 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
2413 IONIC_BUFFER_SPAN_TAIL_DROP,
2414 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
2415 IONIC_BUFFER_ENQUEUE_ERROR_DROP,
2416 IONIC_BUFFER_INVALID_PORT_DROP,
2417 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
2418 IONIC_BUFFER_DROP_MAX,
2419};
2420
2421enum ionic_oflow_drop_stats {
2422 IONIC_OFLOW_OCCUPANCY_DROP,
2423 IONIC_OFLOW_EMERGENCY_STOP_DROP,
2424 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,
2425 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,
2426 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP,
2427 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP,
2428 IONIC_OFLOW_DROP_MAX,
2429};
2430
2431
2432
2433
2434
2435struct ionic_port_pb_stats {
2436 __le64 sop_count_in;
2437 __le64 eop_count_in;
2438 __le64 sop_count_out;
2439 __le64 eop_count_out;
2440 __le64 drop_counts[IONIC_BUFFER_DROP_MAX];
2441 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2442 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
2443 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
2444 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];
2445 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];
2446 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];
2447 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];
2448 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];
2449 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];
2450 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];
2451 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2452};
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468union ionic_port_identity {
2469 struct {
2470 u8 version;
2471 u8 type;
2472 u8 num_lanes;
2473 u8 autoneg;
2474 __le32 min_frame_size;
2475 __le32 max_frame_size;
2476 u8 fec_type[4];
2477 u8 pause_type[2];
2478 u8 loopback_mode[2];
2479 __le32 speeds[16];
2480 u8 rsvd2[44];
2481 union ionic_port_config config;
2482 };
2483 __le32 words[478];
2484};
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494struct ionic_port_info {
2495 union ionic_port_config config;
2496 struct ionic_port_status status;
2497 union {
2498 struct ionic_port_stats stats;
2499 struct ionic_mgmt_port_stats mgmt_stats;
2500 };
2501
2502 u8 rsvd[760];
2503 struct ionic_port_pb_stats pb_stats;
2504};
2505
2506
2507
2508
2509struct ionic_lif_stats {
2510
2511 __le64 rx_ucast_bytes;
2512 __le64 rx_ucast_packets;
2513 __le64 rx_mcast_bytes;
2514 __le64 rx_mcast_packets;
2515 __le64 rx_bcast_bytes;
2516 __le64 rx_bcast_packets;
2517 __le64 rsvd0;
2518 __le64 rsvd1;
2519
2520 __le64 rx_ucast_drop_bytes;
2521 __le64 rx_ucast_drop_packets;
2522 __le64 rx_mcast_drop_bytes;
2523 __le64 rx_mcast_drop_packets;
2524 __le64 rx_bcast_drop_bytes;
2525 __le64 rx_bcast_drop_packets;
2526 __le64 rx_dma_error;
2527 __le64 rsvd2;
2528
2529 __le64 tx_ucast_bytes;
2530 __le64 tx_ucast_packets;
2531 __le64 tx_mcast_bytes;
2532 __le64 tx_mcast_packets;
2533 __le64 tx_bcast_bytes;
2534 __le64 tx_bcast_packets;
2535 __le64 rsvd3;
2536 __le64 rsvd4;
2537
2538 __le64 tx_ucast_drop_bytes;
2539 __le64 tx_ucast_drop_packets;
2540 __le64 tx_mcast_drop_bytes;
2541 __le64 tx_mcast_drop_packets;
2542 __le64 tx_bcast_drop_bytes;
2543 __le64 tx_bcast_drop_packets;
2544 __le64 tx_dma_error;
2545 __le64 rsvd5;
2546
2547 __le64 rx_queue_disabled;
2548 __le64 rx_queue_empty;
2549 __le64 rx_queue_error;
2550 __le64 rx_desc_fetch_error;
2551 __le64 rx_desc_data_error;
2552 __le64 rsvd6;
2553 __le64 rsvd7;
2554 __le64 rsvd8;
2555
2556 __le64 tx_queue_disabled;
2557 __le64 tx_queue_error;
2558 __le64 tx_desc_fetch_error;
2559 __le64 tx_desc_data_error;
2560 __le64 tx_queue_empty;
2561 __le64 rsvd10;
2562 __le64 rsvd11;
2563 __le64 rsvd12;
2564
2565
2566 __le64 tx_rdma_ucast_bytes;
2567 __le64 tx_rdma_ucast_packets;
2568 __le64 tx_rdma_mcast_bytes;
2569 __le64 tx_rdma_mcast_packets;
2570 __le64 tx_rdma_cnp_packets;
2571 __le64 rsvd13;
2572 __le64 rsvd14;
2573 __le64 rsvd15;
2574
2575
2576 __le64 rx_rdma_ucast_bytes;
2577 __le64 rx_rdma_ucast_packets;
2578 __le64 rx_rdma_mcast_bytes;
2579 __le64 rx_rdma_mcast_packets;
2580 __le64 rx_rdma_cnp_packets;
2581 __le64 rx_rdma_ecn_packets;
2582 __le64 rsvd16;
2583 __le64 rsvd17;
2584
2585 __le64 rsvd18;
2586 __le64 rsvd19;
2587 __le64 rsvd20;
2588 __le64 rsvd21;
2589 __le64 rsvd22;
2590 __le64 rsvd23;
2591 __le64 rsvd24;
2592 __le64 rsvd25;
2593
2594 __le64 rsvd26;
2595 __le64 rsvd27;
2596 __le64 rsvd28;
2597 __le64 rsvd29;
2598 __le64 rsvd30;
2599 __le64 rsvd31;
2600 __le64 rsvd32;
2601 __le64 rsvd33;
2602
2603 __le64 rsvd34;
2604 __le64 rsvd35;
2605 __le64 rsvd36;
2606 __le64 rsvd37;
2607 __le64 rsvd38;
2608 __le64 rsvd39;
2609 __le64 rsvd40;
2610 __le64 rsvd41;
2611
2612 __le64 rsvd42;
2613 __le64 rsvd43;
2614 __le64 rsvd44;
2615 __le64 rsvd45;
2616 __le64 rsvd46;
2617 __le64 rsvd47;
2618 __le64 rsvd48;
2619 __le64 rsvd49;
2620
2621
2622 __le64 rdma_req_rx_pkt_seq_err;
2623 __le64 rdma_req_rx_rnr_retry_err;
2624 __le64 rdma_req_rx_remote_access_err;
2625 __le64 rdma_req_rx_remote_inv_req_err;
2626 __le64 rdma_req_rx_remote_oper_err;
2627 __le64 rdma_req_rx_implied_nak_seq_err;
2628 __le64 rdma_req_rx_cqe_err;
2629 __le64 rdma_req_rx_cqe_flush_err;
2630
2631 __le64 rdma_req_rx_dup_responses;
2632 __le64 rdma_req_rx_invalid_packets;
2633 __le64 rdma_req_tx_local_access_err;
2634 __le64 rdma_req_tx_local_oper_err;
2635 __le64 rdma_req_tx_memory_mgmt_err;
2636 __le64 rsvd52;
2637 __le64 rsvd53;
2638 __le64 rsvd54;
2639
2640
2641 __le64 rdma_resp_rx_dup_requests;
2642 __le64 rdma_resp_rx_out_of_buffer;
2643 __le64 rdma_resp_rx_out_of_seq_pkts;
2644 __le64 rdma_resp_rx_cqe_err;
2645 __le64 rdma_resp_rx_cqe_flush_err;
2646 __le64 rdma_resp_rx_local_len_err;
2647 __le64 rdma_resp_rx_inv_request_err;
2648 __le64 rdma_resp_rx_local_qp_oper_err;
2649
2650 __le64 rdma_resp_rx_out_of_atomic_resource;
2651 __le64 rdma_resp_tx_pkt_seq_err;
2652 __le64 rdma_resp_tx_remote_inv_req_err;
2653 __le64 rdma_resp_tx_remote_access_err;
2654 __le64 rdma_resp_tx_remote_oper_err;
2655 __le64 rdma_resp_tx_rnr_retry_err;
2656 __le64 rsvd57;
2657 __le64 rsvd58;
2658};
2659
2660
2661
2662
2663
2664
2665
2666struct ionic_lif_info {
2667 union ionic_lif_config config;
2668 struct ionic_lif_status status;
2669 struct ionic_lif_stats stats;
2670};
2671
2672union ionic_dev_cmd {
2673 u32 words[16];
2674 struct ionic_admin_cmd cmd;
2675 struct ionic_nop_cmd nop;
2676
2677 struct ionic_dev_identify_cmd identify;
2678 struct ionic_dev_init_cmd init;
2679 struct ionic_dev_reset_cmd reset;
2680 struct ionic_dev_getattr_cmd getattr;
2681 struct ionic_dev_setattr_cmd setattr;
2682
2683 struct ionic_port_identify_cmd port_identify;
2684 struct ionic_port_init_cmd port_init;
2685 struct ionic_port_reset_cmd port_reset;
2686 struct ionic_port_getattr_cmd port_getattr;
2687 struct ionic_port_setattr_cmd port_setattr;
2688
2689 struct ionic_vf_setattr_cmd vf_setattr;
2690 struct ionic_vf_getattr_cmd vf_getattr;
2691
2692 struct ionic_lif_identify_cmd lif_identify;
2693 struct ionic_lif_init_cmd lif_init;
2694 struct ionic_lif_reset_cmd lif_reset;
2695
2696 struct ionic_qos_identify_cmd qos_identify;
2697 struct ionic_qos_init_cmd qos_init;
2698 struct ionic_qos_reset_cmd qos_reset;
2699 struct ionic_qos_clear_stats_cmd qos_clear_stats;
2700
2701 struct ionic_q_identify_cmd q_identify;
2702 struct ionic_q_init_cmd q_init;
2703 struct ionic_q_control_cmd q_control;
2704
2705 struct ionic_fw_download_cmd fw_download;
2706 struct ionic_fw_control_cmd fw_control;
2707};
2708
2709union ionic_dev_cmd_comp {
2710 u32 words[4];
2711 u8 status;
2712 struct ionic_admin_comp comp;
2713 struct ionic_nop_comp nop;
2714
2715 struct ionic_dev_identify_comp identify;
2716 struct ionic_dev_init_comp init;
2717 struct ionic_dev_reset_comp reset;
2718 struct ionic_dev_getattr_comp getattr;
2719 struct ionic_dev_setattr_comp setattr;
2720
2721 struct ionic_port_identify_comp port_identify;
2722 struct ionic_port_init_comp port_init;
2723 struct ionic_port_reset_comp port_reset;
2724 struct ionic_port_getattr_comp port_getattr;
2725 struct ionic_port_setattr_comp port_setattr;
2726
2727 struct ionic_vf_setattr_comp vf_setattr;
2728 struct ionic_vf_getattr_comp vf_getattr;
2729
2730 struct ionic_lif_identify_comp lif_identify;
2731 struct ionic_lif_init_comp lif_init;
2732 ionic_lif_reset_comp lif_reset;
2733
2734 struct ionic_qos_identify_comp qos_identify;
2735 ionic_qos_init_comp qos_init;
2736 ionic_qos_reset_comp qos_reset;
2737
2738 struct ionic_q_identify_comp q_identify;
2739 struct ionic_q_init_comp q_init;
2740
2741 ionic_fw_download_comp fw_download;
2742 struct ionic_fw_control_comp fw_control;
2743};
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756union ionic_dev_info_regs {
2757#define IONIC_DEVINFO_FWVERS_BUFLEN 32
2758#define IONIC_DEVINFO_SERIAL_BUFLEN 32
2759 struct {
2760 u32 signature;
2761 u8 version;
2762 u8 asic_type;
2763 u8 asic_rev;
2764#define IONIC_FW_STS_F_RUNNING 0x1
2765 u8 fw_status;
2766 u32 fw_heartbeat;
2767 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
2768 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
2769 };
2770 u32 words[512];
2771};
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783union ionic_dev_cmd_regs {
2784 struct {
2785 u32 doorbell;
2786 u32 done;
2787 union ionic_dev_cmd cmd;
2788 union ionic_dev_cmd_comp comp;
2789 u8 rsvd[48];
2790 u32 data[478];
2791 } __packed;
2792 u32 words[512];
2793};
2794
2795
2796
2797
2798
2799
2800union ionic_dev_regs {
2801 struct {
2802 union ionic_dev_info_regs info;
2803 union ionic_dev_cmd_regs devcmd;
2804 } __packed;
2805 __le32 words[1024];
2806};
2807
2808union ionic_adminq_cmd {
2809 struct ionic_admin_cmd cmd;
2810 struct ionic_nop_cmd nop;
2811 struct ionic_q_identify_cmd q_identify;
2812 struct ionic_q_init_cmd q_init;
2813 struct ionic_q_control_cmd q_control;
2814 struct ionic_lif_setattr_cmd lif_setattr;
2815 struct ionic_lif_getattr_cmd lif_getattr;
2816 struct ionic_rx_mode_set_cmd rx_mode_set;
2817 struct ionic_rx_filter_add_cmd rx_filter_add;
2818 struct ionic_rx_filter_del_cmd rx_filter_del;
2819 struct ionic_rdma_reset_cmd rdma_reset;
2820 struct ionic_rdma_queue_cmd rdma_queue;
2821 struct ionic_fw_download_cmd fw_download;
2822 struct ionic_fw_control_cmd fw_control;
2823};
2824
2825union ionic_adminq_comp {
2826 struct ionic_admin_comp comp;
2827 struct ionic_nop_comp nop;
2828 struct ionic_q_identify_comp q_identify;
2829 struct ionic_q_init_comp q_init;
2830 struct ionic_lif_setattr_comp lif_setattr;
2831 struct ionic_lif_getattr_comp lif_getattr;
2832 struct ionic_rx_filter_add_comp rx_filter_add;
2833 struct ionic_fw_control_comp fw_control;
2834};
2835
2836#define IONIC_BARS_MAX 6
2837#define IONIC_PCI_BAR_DBELL 1
2838
2839
2840#define IONIC_BAR0_SIZE 0x8000
2841
2842#define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
2843#define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
2844#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
2845#define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
2846#define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
2847#define IONIC_DEV_CMD_DONE 0x00000001
2848
2849#define IONIC_ASIC_TYPE_CAPRI 0
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863struct ionic_doorbell {
2864 __le16 p_index;
2865 u8 ring;
2866 u8 qid_lo;
2867 __le16 qid_hi;
2868 u16 rsvd2;
2869};
2870
2871struct ionic_intr_status {
2872 u32 status[2];
2873};
2874
2875struct ionic_notifyq_cmd {
2876 __le32 data;
2877};
2878
2879union ionic_notifyq_comp {
2880 struct ionic_notifyq_event event;
2881 struct ionic_link_change_event link_change;
2882 struct ionic_reset_event reset;
2883 struct ionic_heartbeat_event heartbeat;
2884 struct ionic_log_event log;
2885};
2886
2887
2888struct ionic_identity {
2889 union ionic_drv_identity drv;
2890 union ionic_dev_identity dev;
2891 union ionic_lif_identity lif;
2892 union ionic_port_identity port;
2893 union ionic_qos_identity qos;
2894 union ionic_q_identity txq;
2895};
2896
2897#endif
2898