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7#ifndef _QED_INT_H
8#define _QED_INT_H
9
10#include <linux/types.h>
11#include <linux/slab.h>
12#include "qed.h"
13
14
15#define IGU_PF_CONF_FUNC_EN (0x1 << 0)
16#define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1)
17#define IGU_PF_CONF_INT_LINE_EN (0x1 << 2)
18#define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3)
19#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)
20#define IGU_PF_CONF_SIMD_MODE (0x1 << 5)
21
22#define IGU_VF_CONF_FUNC_EN (0x1 << 0)
23#define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1)
24#define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4)
25#define IGU_VF_CONF_PARENT_MASK (0xF)
26#define IGU_VF_CONF_PARENT_SHIFT 5
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29
30enum igu_ctrl_cmd {
31 IGU_CTRL_CMD_TYPE_RD,
32 IGU_CTRL_CMD_TYPE_WR,
33 MAX_IGU_CTRL_CMD
34};
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38struct igu_ctrl_reg {
39 u32 ctrl_data;
40#define IGU_CTRL_REG_FID_MASK 0xFFFF
41#define IGU_CTRL_REG_FID_SHIFT 0
42#define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF
43#define IGU_CTRL_REG_PXP_ADDR_SHIFT 16
44#define IGU_CTRL_REG_RESERVED_MASK 0x1
45#define IGU_CTRL_REG_RESERVED_SHIFT 28
46#define IGU_CTRL_REG_TYPE_MASK 0x1
47#define IGU_CTRL_REG_TYPE_SHIFT 31
48};
49
50enum qed_coalescing_fsm {
51 QED_COAL_RX_STATE_MACHINE,
52 QED_COAL_TX_STATE_MACHINE
53};
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62void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
63 struct qed_ptt *p_ptt,
64 enum qed_int_mode int_mode);
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72void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
73 struct qed_ptt *p_ptt);
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83u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
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85#define QED_SP_SB_ID 0xffff
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102int qed_int_sb_init(struct qed_hwfn *p_hwfn,
103 struct qed_ptt *p_ptt,
104 struct qed_sb_info *sb_info,
105 void *sb_virt_addr,
106 dma_addr_t sb_phy_addr,
107 u16 sb_id);
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115void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
116 struct qed_ptt *p_ptt,
117 struct qed_sb_info *sb_info);
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132int qed_int_sb_release(struct qed_hwfn *p_hwfn,
133 struct qed_sb_info *sb_info,
134 u16 sb_id);
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143void qed_int_sp_dpc(struct tasklet_struct *t);
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154void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
155 struct qed_sb_cnt_info *p_sb_cnt_info);
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165void qed_int_disable_post_isr_release(struct qed_dev *cdev);
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176void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable);
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186int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
187
188#define QED_CAU_DEF_RX_TIMER_RES 0
189#define QED_CAU_DEF_TX_TIMER_RES 0
190
191#define QED_SB_ATT_IDX 0x0001
192#define QED_SB_EVENT_MASK 0x0003
193
194#define SB_ALIGNED_SIZE(p_hwfn) \
195 ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
196
197#define QED_SB_INVALID_IDX 0xffff
198
199struct qed_igu_block {
200 u8 status;
201#define QED_IGU_STATUS_FREE 0x01
202#define QED_IGU_STATUS_VALID 0x02
203#define QED_IGU_STATUS_PF 0x04
204#define QED_IGU_STATUS_DSB 0x08
205
206 u8 vector_number;
207 u8 function_id;
208 u8 is_pf;
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211 u16 igu_sb_id;
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213 struct qed_sb_info *sb_info;
214};
215
216struct qed_igu_info {
217 struct qed_igu_block entry[MAX_TOT_SB_PER_PATH];
218 u16 igu_dsb_id;
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220 struct qed_sb_cnt_info usage;
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222 bool b_allow_pf_vf_change;
223};
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231int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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241u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
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251struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn,
252 bool b_is_pf);
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254void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
255 struct qed_ptt *p_ptt,
256 bool b_set,
257 bool b_slowpath);
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259void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
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272int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
273 struct qed_ptt *p_ptt);
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275typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
276 void *cookie);
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297int qed_int_register_cb(struct qed_hwfn *p_hwfn,
298 qed_int_comp_cb_t comp_cb,
299 void *cookie,
300 u8 *sb_idx,
301 __le16 **p_fw_cons);
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314int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
315 u8 pi);
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324u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
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336void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
337 struct qed_ptt *p_ptt,
338 u16 igu_sb_id,
339 u16 opaque,
340 bool b_set);
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353void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
354 struct qed_ptt *p_ptt,
355 dma_addr_t sb_phys,
356 u16 igu_sb_id,
357 u16 vf_number,
358 u8 vf_valid);
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368int qed_int_alloc(struct qed_hwfn *p_hwfn,
369 struct qed_ptt *p_ptt);
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376void qed_int_free(struct qed_hwfn *p_hwfn);
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384void qed_int_setup(struct qed_hwfn *p_hwfn,
385 struct qed_ptt *p_ptt);
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396int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
397 enum qed_int_mode int_mode);
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408void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
409 struct cau_sb_entry *p_sb_entry,
410 u8 pf_id,
411 u16 vf_number,
412 u8 vf_valid);
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414int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
415 u8 timer_res, u16 sb_id, bool tx);
416
417#define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev))
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419int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
420 bool hw_init);
421
422#endif
423