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13#include <linux/crc32.h>
14#include <linux/slab.h>
15#include <linux/ethtool.h>
16#include <linux/io.h>
17#include <net/dsa.h>
18#include "stmmac.h"
19#include "stmmac_pcs.h"
20#include "dwmac4.h"
21#include "dwmac5.h"
22
23static void dwmac4_core_init(struct mac_device_info *hw,
24 struct net_device *dev)
25{
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + GMAC_CONFIG);
28
29 value |= GMAC_CORE_INIT;
30
31 if (hw->ps) {
32 value |= GMAC_CONFIG_TE;
33
34 value &= hw->link.speed_mask;
35 switch (hw->ps) {
36 case SPEED_1000:
37 value |= hw->link.speed1000;
38 break;
39 case SPEED_100:
40 value |= hw->link.speed100;
41 break;
42 case SPEED_10:
43 value |= hw->link.speed10;
44 break;
45 }
46 }
47
48 writel(value, ioaddr + GMAC_CONFIG);
49
50
51 value = GMAC_INT_DEFAULT_ENABLE;
52
53 if (hw->pcs)
54 value |= GMAC_PCS_IRQ_DEFAULT;
55
56 writel(value, ioaddr + GMAC_INT_EN);
57}
58
59static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
60 u8 mode, u32 queue)
61{
62 void __iomem *ioaddr = hw->pcsr;
63 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
64
65 value &= GMAC_RX_QUEUE_CLEAR(queue);
66 if (mode == MTL_QUEUE_AVB)
67 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
68 else if (mode == MTL_QUEUE_DCB)
69 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
70
71 writel(value, ioaddr + GMAC_RXQ_CTRL0);
72}
73
74static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
75 u32 prio, u32 queue)
76{
77 void __iomem *ioaddr = hw->pcsr;
78 u32 base_register;
79 u32 value;
80
81 base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
82 if (queue >= 4)
83 queue -= 4;
84
85 value = readl(ioaddr + base_register);
86
87 value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
88 value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
89 GMAC_RXQCTRL_PSRQX_MASK(queue);
90 writel(value, ioaddr + base_register);
91}
92
93static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
94 u32 prio, u32 queue)
95{
96 void __iomem *ioaddr = hw->pcsr;
97 u32 base_register;
98 u32 value;
99
100 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
101 if (queue >= 4)
102 queue -= 4;
103
104 value = readl(ioaddr + base_register);
105
106 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
107 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
108 GMAC_TXQCTRL_PSTQX_MASK(queue);
109
110 writel(value, ioaddr + base_register);
111}
112
113static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
114 u8 packet, u32 queue)
115{
116 void __iomem *ioaddr = hw->pcsr;
117 u32 value;
118
119 static const struct stmmac_rx_routing route_possibilities[] = {
120 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
121 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
122 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
123 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
124 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
125 };
126
127 value = readl(ioaddr + GMAC_RXQ_CTRL1);
128
129
130 value &= ~route_possibilities[packet - 1].reg_mask;
131 value |= (queue << route_possibilities[packet-1].reg_shift) &
132 route_possibilities[packet - 1].reg_mask;
133
134
135 if (packet == PACKET_AVCPQ) {
136 value &= ~GMAC_RXQCTRL_TACPQE;
137 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
138 } else if (packet == PACKET_MCBCQ) {
139 value &= ~GMAC_RXQCTRL_MCBCQEN;
140 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
141 }
142
143 writel(value, ioaddr + GMAC_RXQ_CTRL1);
144}
145
146static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
147 u32 rx_alg)
148{
149 void __iomem *ioaddr = hw->pcsr;
150 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
151
152 value &= ~MTL_OPERATION_RAA;
153 switch (rx_alg) {
154 case MTL_RX_ALGORITHM_SP:
155 value |= MTL_OPERATION_RAA_SP;
156 break;
157 case MTL_RX_ALGORITHM_WSP:
158 value |= MTL_OPERATION_RAA_WSP;
159 break;
160 default:
161 break;
162 }
163
164 writel(value, ioaddr + MTL_OPERATION_MODE);
165}
166
167static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
168 u32 tx_alg)
169{
170 void __iomem *ioaddr = hw->pcsr;
171 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
172
173 value &= ~MTL_OPERATION_SCHALG_MASK;
174 switch (tx_alg) {
175 case MTL_TX_ALGORITHM_WRR:
176 value |= MTL_OPERATION_SCHALG_WRR;
177 break;
178 case MTL_TX_ALGORITHM_WFQ:
179 value |= MTL_OPERATION_SCHALG_WFQ;
180 break;
181 case MTL_TX_ALGORITHM_DWRR:
182 value |= MTL_OPERATION_SCHALG_DWRR;
183 break;
184 case MTL_TX_ALGORITHM_SP:
185 value |= MTL_OPERATION_SCHALG_SP;
186 break;
187 default:
188 break;
189 }
190
191 writel(value, ioaddr + MTL_OPERATION_MODE);
192}
193
194static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
195 u32 weight, u32 queue)
196{
197 void __iomem *ioaddr = hw->pcsr;
198 u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
199
200 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
201 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
202 writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
203}
204
205static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
206{
207 void __iomem *ioaddr = hw->pcsr;
208 u32 value;
209
210 if (queue < 4)
211 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
212 else
213 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
214
215 if (queue == 0 || queue == 4) {
216 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
217 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
218 } else {
219 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
220 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
221 }
222
223 if (queue < 4)
224 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
225 else
226 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
227}
228
229static void dwmac4_config_cbs(struct mac_device_info *hw,
230 u32 send_slope, u32 idle_slope,
231 u32 high_credit, u32 low_credit, u32 queue)
232{
233 void __iomem *ioaddr = hw->pcsr;
234 u32 value;
235
236 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
237 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
238 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
239 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
240 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
241
242
243 value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
244 value |= MTL_ETS_CTRL_AVALG;
245 value |= MTL_ETS_CTRL_CC;
246 writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
247
248
249 value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
250 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
251 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
252 writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
253
254
255 dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
256
257
258 value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
259 value &= ~MTL_HIGH_CRED_HC_MASK;
260 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
261 writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
262
263
264 value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
265 value &= ~MTL_HIGH_CRED_LC_MASK;
266 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
267 writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
268}
269
270static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
271{
272 void __iomem *ioaddr = hw->pcsr;
273 int i;
274
275 for (i = 0; i < GMAC_REG_NUM; i++)
276 reg_space[i] = readl(ioaddr + i * 4);
277}
278
279static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
280{
281 void __iomem *ioaddr = hw->pcsr;
282 u32 value = readl(ioaddr + GMAC_CONFIG);
283
284 if (hw->rx_csum)
285 value |= GMAC_CONFIG_IPC;
286 else
287 value &= ~GMAC_CONFIG_IPC;
288
289 writel(value, ioaddr + GMAC_CONFIG);
290
291 value = readl(ioaddr + GMAC_CONFIG);
292
293 return !!(value & GMAC_CONFIG_IPC);
294}
295
296static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
297{
298 void __iomem *ioaddr = hw->pcsr;
299 unsigned int pmt = 0;
300 u32 config;
301
302 if (mode & WAKE_MAGIC) {
303 pr_debug("GMAC: WOL Magic frame\n");
304 pmt |= power_down | magic_pkt_en;
305 }
306 if (mode & WAKE_UCAST) {
307 pr_debug("GMAC: WOL on global unicast\n");
308 pmt |= power_down | global_unicast | wake_up_frame_en;
309 }
310
311 if (pmt) {
312
313 config = readl(ioaddr + GMAC_CONFIG);
314 config |= GMAC_CONFIG_RE;
315 writel(config, ioaddr + GMAC_CONFIG);
316 }
317 writel(pmt, ioaddr + GMAC_PMT);
318}
319
320static void dwmac4_set_umac_addr(struct mac_device_info *hw,
321 unsigned char *addr, unsigned int reg_n)
322{
323 void __iomem *ioaddr = hw->pcsr;
324
325 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
326 GMAC_ADDR_LOW(reg_n));
327}
328
329static void dwmac4_get_umac_addr(struct mac_device_info *hw,
330 unsigned char *addr, unsigned int reg_n)
331{
332 void __iomem *ioaddr = hw->pcsr;
333
334 stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
335 GMAC_ADDR_LOW(reg_n));
336}
337
338static void dwmac4_set_eee_mode(struct mac_device_info *hw,
339 bool en_tx_lpi_clockgating)
340{
341 void __iomem *ioaddr = hw->pcsr;
342 u32 value;
343
344
345
346
347
348 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
349 value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
350
351 if (en_tx_lpi_clockgating)
352 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
353
354 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
355}
356
357static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
358{
359 void __iomem *ioaddr = hw->pcsr;
360 u32 value;
361
362 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
363 value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
364 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
365}
366
367static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
368{
369 void __iomem *ioaddr = hw->pcsr;
370 u32 value;
371
372 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
373
374 if (link)
375 value |= GMAC4_LPI_CTRL_STATUS_PLS;
376 else
377 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
378
379 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
380}
381
382static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
383{
384 void __iomem *ioaddr = hw->pcsr;
385 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
386
387
388
389
390
391
392
393
394 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
395}
396
397static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
398{
399 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
400 u32 val;
401
402 val = readl(ioaddr + GMAC_VLAN_TAG);
403 val &= ~GMAC_VLAN_TAG_VID;
404 val |= GMAC_VLAN_TAG_ETV | vid;
405
406 writel(val, ioaddr + GMAC_VLAN_TAG);
407}
408
409static int dwmac4_write_vlan_filter(struct net_device *dev,
410 struct mac_device_info *hw,
411 u8 index, u32 data)
412{
413 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
414 int i, timeout = 10;
415 u32 val;
416
417 if (index >= hw->num_vlan)
418 return -EINVAL;
419
420 writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
421
422 val = readl(ioaddr + GMAC_VLAN_TAG);
423 val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
424 GMAC_VLAN_TAG_CTRL_CT |
425 GMAC_VLAN_TAG_CTRL_OB);
426 val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
427
428 writel(val, ioaddr + GMAC_VLAN_TAG);
429
430 for (i = 0; i < timeout; i++) {
431 val = readl(ioaddr + GMAC_VLAN_TAG);
432 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
433 return 0;
434 udelay(1);
435 }
436
437 netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
438
439 return -EBUSY;
440}
441
442static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
443 struct mac_device_info *hw,
444 __be16 proto, u16 vid)
445{
446 int index = -1;
447 u32 val = 0;
448 int i, ret;
449
450 if (vid > 4095)
451 return -EINVAL;
452
453 if (hw->promisc) {
454 netdev_err(dev,
455 "Adding VLAN in promisc mode not supported\n");
456 return -EPERM;
457 }
458
459
460 if (hw->num_vlan == 1) {
461
462 if (vid == 0) {
463 netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
464 return -EPERM;
465 }
466
467 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
468 netdev_err(dev, "Only single VLAN ID supported\n");
469 return -EPERM;
470 }
471
472 hw->vlan_filter[0] = vid;
473 dwmac4_write_single_vlan(dev, vid);
474
475 return 0;
476 }
477
478
479 val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
480
481 for (i = 0; i < hw->num_vlan; i++) {
482 if (hw->vlan_filter[i] == val)
483 return 0;
484 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
485 index = i;
486 }
487
488 if (index == -1) {
489 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
490 hw->num_vlan);
491 return -EPERM;
492 }
493
494 ret = dwmac4_write_vlan_filter(dev, hw, index, val);
495
496 if (!ret)
497 hw->vlan_filter[index] = val;
498
499 return ret;
500}
501
502static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
503 struct mac_device_info *hw,
504 __be16 proto, u16 vid)
505{
506 int i, ret = 0;
507
508 if (hw->promisc) {
509 netdev_err(dev,
510 "Deleting VLAN in promisc mode not supported\n");
511 return -EPERM;
512 }
513
514
515 if (hw->num_vlan == 1) {
516 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
517 hw->vlan_filter[0] = 0;
518 dwmac4_write_single_vlan(dev, 0);
519 }
520 return 0;
521 }
522
523
524 for (i = 0; i < hw->num_vlan; i++) {
525 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
526 ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
527
528 if (!ret)
529 hw->vlan_filter[i] = 0;
530 else
531 return ret;
532 }
533 }
534
535 return ret;
536}
537
538static void dwmac4_vlan_promisc_enable(struct net_device *dev,
539 struct mac_device_info *hw)
540{
541 void __iomem *ioaddr = hw->pcsr;
542 u32 value;
543 u32 hash;
544 u32 val;
545 int i;
546
547
548 if (hw->num_vlan == 1) {
549 dwmac4_write_single_vlan(dev, 0);
550 return;
551 }
552
553
554 for (i = 0; i < hw->num_vlan; i++) {
555 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
556 val = hw->vlan_filter[i] & ~GMAC_VLAN_TAG_DATA_VEN;
557 dwmac4_write_vlan_filter(dev, hw, i, val);
558 }
559 }
560
561 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
562 if (hash & GMAC_VLAN_VLHT) {
563 value = readl(ioaddr + GMAC_VLAN_TAG);
564 if (value & GMAC_VLAN_VTHM) {
565 value &= ~GMAC_VLAN_VTHM;
566 writel(value, ioaddr + GMAC_VLAN_TAG);
567 }
568 }
569}
570
571static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
572 struct mac_device_info *hw)
573{
574 void __iomem *ioaddr = hw->pcsr;
575 u32 value;
576 u32 hash;
577 u32 val;
578 int i;
579
580
581 if (hw->num_vlan == 1) {
582 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
583 return;
584 }
585
586
587 for (i = 0; i < hw->num_vlan; i++) {
588 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
589 val = hw->vlan_filter[i];
590 dwmac4_write_vlan_filter(dev, hw, i, val);
591 }
592 }
593
594 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
595 if (hash & GMAC_VLAN_VLHT) {
596 value = readl(ioaddr + GMAC_VLAN_TAG);
597 value |= GMAC_VLAN_VTHM;
598 writel(value, ioaddr + GMAC_VLAN_TAG);
599 }
600}
601
602static void dwmac4_set_filter(struct mac_device_info *hw,
603 struct net_device *dev)
604{
605 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
606 int numhashregs = (hw->multicast_filter_bins >> 5);
607 int mcbitslog2 = hw->mcast_bits_log2;
608 unsigned int value;
609 u32 mc_filter[8];
610 int i;
611
612 memset(mc_filter, 0, sizeof(mc_filter));
613
614 value = readl(ioaddr + GMAC_PACKET_FILTER);
615 value &= ~GMAC_PACKET_FILTER_HMC;
616 value &= ~GMAC_PACKET_FILTER_HPF;
617 value &= ~GMAC_PACKET_FILTER_PCF;
618 value &= ~GMAC_PACKET_FILTER_PM;
619 value &= ~GMAC_PACKET_FILTER_PR;
620 if (dev->flags & IFF_PROMISC) {
621
622 if (hw->vlan_fail_q_en) {
623 value = readl(ioaddr + GMAC_RXQ_CTRL4);
624 value &= ~GMAC_RXQCTRL_VFFQ_MASK;
625 value |= GMAC_RXQCTRL_VFFQE |
626 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
627 writel(value, ioaddr + GMAC_RXQ_CTRL4);
628 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
629 } else {
630 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
631 }
632
633 } else if ((dev->flags & IFF_ALLMULTI) ||
634 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
635
636 value |= GMAC_PACKET_FILTER_PM;
637
638 memset(mc_filter, 0xff, sizeof(mc_filter));
639 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
640 struct netdev_hw_addr *ha;
641
642
643 value |= GMAC_PACKET_FILTER_HMC;
644
645 netdev_for_each_mc_addr(ha, dev) {
646
647
648
649
650
651 u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
652 ETH_ALEN)) >> (32 - mcbitslog2);
653
654
655
656
657 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
658 }
659 }
660
661 for (i = 0; i < numhashregs; i++)
662 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
663
664 value |= GMAC_PACKET_FILTER_HPF;
665
666
667 if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
668
669
670
671 value |= GMAC_PACKET_FILTER_PR;
672 } else {
673 struct netdev_hw_addr *ha;
674 int reg = 1;
675
676 netdev_for_each_uc_addr(ha, dev) {
677 dwmac4_set_umac_addr(hw, ha->addr, reg);
678 reg++;
679 }
680
681 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
682 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
683 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
684 reg++;
685 }
686 }
687
688
689 if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
690 value |= GMAC_PACKET_FILTER_VTFE;
691
692 writel(value, ioaddr + GMAC_PACKET_FILTER);
693
694 if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) {
695 if (!hw->promisc) {
696 hw->promisc = 1;
697 dwmac4_vlan_promisc_enable(dev, hw);
698 }
699 } else {
700 if (hw->promisc) {
701 hw->promisc = 0;
702 dwmac4_restore_hw_vlan_rx_fltr(dev, hw);
703 }
704 }
705}
706
707static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
708 unsigned int fc, unsigned int pause_time,
709 u32 tx_cnt)
710{
711 void __iomem *ioaddr = hw->pcsr;
712 unsigned int flow = 0;
713 u32 queue = 0;
714
715 pr_debug("GMAC Flow-Control:\n");
716 if (fc & FLOW_RX) {
717 pr_debug("\tReceive Flow-Control ON\n");
718 flow |= GMAC_RX_FLOW_CTRL_RFE;
719 }
720 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
721
722 if (fc & FLOW_TX) {
723 pr_debug("\tTransmit Flow-Control ON\n");
724
725 if (duplex)
726 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
727
728 for (queue = 0; queue < tx_cnt; queue++) {
729 flow = GMAC_TX_FLOW_CTRL_TFE;
730
731 if (duplex)
732 flow |=
733 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
734
735 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
736 }
737 } else {
738 for (queue = 0; queue < tx_cnt; queue++)
739 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
740 }
741}
742
743static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
744 bool loopback)
745{
746 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
747}
748
749static void dwmac4_rane(void __iomem *ioaddr, bool restart)
750{
751 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
752}
753
754static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
755{
756 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
757}
758
759
760static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
761{
762 u32 status;
763
764 status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
765 x->irq_rgmii_n++;
766
767
768 if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
769 int speed_value;
770
771 x->pcs_link = 1;
772
773 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
774 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
775 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
776 x->pcs_speed = SPEED_1000;
777 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
778 x->pcs_speed = SPEED_100;
779 else
780 x->pcs_speed = SPEED_10;
781
782 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
783
784 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
785 x->pcs_duplex ? "Full" : "Half");
786 } else {
787 x->pcs_link = 0;
788 pr_info("Link is Down\n");
789 }
790}
791
792static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
793{
794 void __iomem *ioaddr = hw->pcsr;
795 u32 mtl_int_qx_status;
796 int ret = 0;
797
798 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
799
800
801 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
802
803 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
804
805 if (status & MTL_RX_OVERFLOW_INT) {
806
807 writel(status | MTL_RX_OVERFLOW_INT,
808 ioaddr + MTL_CHAN_INT_CTRL(chan));
809 ret = CORE_IRQ_MTL_RX_OVERFLOW;
810 }
811 }
812
813 return ret;
814}
815
816static int dwmac4_irq_status(struct mac_device_info *hw,
817 struct stmmac_extra_stats *x)
818{
819 void __iomem *ioaddr = hw->pcsr;
820 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
821 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
822 int ret = 0;
823
824
825 intr_status &= intr_enable;
826
827
828 if ((intr_status & mmc_tx_irq))
829 x->mmc_tx_irq_n++;
830 if (unlikely(intr_status & mmc_rx_irq))
831 x->mmc_rx_irq_n++;
832 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
833 x->mmc_rx_csum_offload_irq_n++;
834
835 if (unlikely(intr_status & pmt_irq)) {
836 readl(ioaddr + GMAC_PMT);
837 x->irq_receive_pmt_irq_n++;
838 }
839
840
841 if (intr_status & lpi_irq) {
842
843 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
844
845 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
846 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
847 x->irq_tx_path_in_lpi_mode_n++;
848 }
849 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
850 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
851 x->irq_tx_path_exit_lpi_mode_n++;
852 }
853 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
854 x->irq_rx_path_in_lpi_mode_n++;
855 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
856 x->irq_rx_path_exit_lpi_mode_n++;
857 }
858
859 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
860 if (intr_status & PCS_RGSMIIIS_IRQ)
861 dwmac4_phystatus(ioaddr, x);
862
863 return ret;
864}
865
866static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
867 u32 rx_queues, u32 tx_queues)
868{
869 u32 value;
870 u32 queue;
871
872 for (queue = 0; queue < tx_queues; queue++) {
873 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
874
875 if (value & MTL_DEBUG_TXSTSFSTS)
876 x->mtl_tx_status_fifo_full++;
877 if (value & MTL_DEBUG_TXFSTS)
878 x->mtl_tx_fifo_not_empty++;
879 if (value & MTL_DEBUG_TWCSTS)
880 x->mmtl_fifo_ctrl++;
881 if (value & MTL_DEBUG_TRCSTS_MASK) {
882 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
883 >> MTL_DEBUG_TRCSTS_SHIFT;
884 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
885 x->mtl_tx_fifo_read_ctrl_write++;
886 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
887 x->mtl_tx_fifo_read_ctrl_wait++;
888 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
889 x->mtl_tx_fifo_read_ctrl_read++;
890 else
891 x->mtl_tx_fifo_read_ctrl_idle++;
892 }
893 if (value & MTL_DEBUG_TXPAUSED)
894 x->mac_tx_in_pause++;
895 }
896
897 for (queue = 0; queue < rx_queues; queue++) {
898 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
899
900 if (value & MTL_DEBUG_RXFSTS_MASK) {
901 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
902 >> MTL_DEBUG_RRCSTS_SHIFT;
903
904 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
905 x->mtl_rx_fifo_fill_level_full++;
906 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
907 x->mtl_rx_fifo_fill_above_thresh++;
908 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
909 x->mtl_rx_fifo_fill_below_thresh++;
910 else
911 x->mtl_rx_fifo_fill_level_empty++;
912 }
913 if (value & MTL_DEBUG_RRCSTS_MASK) {
914 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
915 MTL_DEBUG_RRCSTS_SHIFT;
916
917 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
918 x->mtl_rx_fifo_read_ctrl_flush++;
919 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
920 x->mtl_rx_fifo_read_ctrl_read_data++;
921 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
922 x->mtl_rx_fifo_read_ctrl_status++;
923 else
924 x->mtl_rx_fifo_read_ctrl_idle++;
925 }
926 if (value & MTL_DEBUG_RWCSTS)
927 x->mtl_rx_fifo_ctrl_active++;
928 }
929
930
931 value = readl(ioaddr + GMAC_DEBUG);
932
933 if (value & GMAC_DEBUG_TFCSTS_MASK) {
934 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
935 >> GMAC_DEBUG_TFCSTS_SHIFT;
936
937 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
938 x->mac_tx_frame_ctrl_xfer++;
939 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
940 x->mac_tx_frame_ctrl_pause++;
941 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
942 x->mac_tx_frame_ctrl_wait++;
943 else
944 x->mac_tx_frame_ctrl_idle++;
945 }
946 if (value & GMAC_DEBUG_TPESTS)
947 x->mac_gmii_tx_proto_engine++;
948 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
949 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
950 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
951 if (value & GMAC_DEBUG_RPESTS)
952 x->mac_gmii_rx_proto_engine++;
953}
954
955static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
956{
957 u32 value = readl(ioaddr + GMAC_CONFIG);
958
959 if (enable)
960 value |= GMAC_CONFIG_LM;
961 else
962 value &= ~GMAC_CONFIG_LM;
963
964 writel(value, ioaddr + GMAC_CONFIG);
965}
966
967static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
968 __le16 perfect_match, bool is_double)
969{
970 void __iomem *ioaddr = hw->pcsr;
971 u32 value;
972
973 writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
974
975 value = readl(ioaddr + GMAC_VLAN_TAG);
976
977 if (hash) {
978 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
979 if (is_double) {
980 value |= GMAC_VLAN_EDVLP;
981 value |= GMAC_VLAN_ESVL;
982 value |= GMAC_VLAN_DOVLTC;
983 }
984
985 writel(value, ioaddr + GMAC_VLAN_TAG);
986 } else if (perfect_match) {
987 u32 value = GMAC_VLAN_ETV;
988
989 if (is_double) {
990 value |= GMAC_VLAN_EDVLP;
991 value |= GMAC_VLAN_ESVL;
992 value |= GMAC_VLAN_DOVLTC;
993 }
994
995 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
996 } else {
997 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
998 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
999 value &= ~GMAC_VLAN_DOVLTC;
1000 value &= ~GMAC_VLAN_VID;
1001
1002 writel(value, ioaddr + GMAC_VLAN_TAG);
1003 }
1004}
1005
1006static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
1007{
1008 u32 value = readl(ioaddr + GMAC_CONFIG);
1009
1010 value &= ~GMAC_CONFIG_SARC;
1011 value |= val << GMAC_CONFIG_SARC_SHIFT;
1012
1013 writel(value, ioaddr + GMAC_CONFIG);
1014}
1015
1016static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
1017{
1018 void __iomem *ioaddr = hw->pcsr;
1019 u32 value;
1020
1021 value = readl(ioaddr + GMAC_VLAN_INCL);
1022 value |= GMAC_VLAN_VLTI;
1023 value |= GMAC_VLAN_CSVL;
1024 value &= ~GMAC_VLAN_VLC;
1025 value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
1026 writel(value, ioaddr + GMAC_VLAN_INCL);
1027}
1028
1029static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1030 u32 addr)
1031{
1032 void __iomem *ioaddr = hw->pcsr;
1033 u32 value;
1034
1035 writel(addr, ioaddr + GMAC_ARP_ADDR);
1036
1037 value = readl(ioaddr + GMAC_CONFIG);
1038 if (en)
1039 value |= GMAC_CONFIG_ARPEN;
1040 else
1041 value &= ~GMAC_CONFIG_ARPEN;
1042 writel(value, ioaddr + GMAC_CONFIG);
1043}
1044
1045static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1046 bool en, bool ipv6, bool sa, bool inv,
1047 u32 match)
1048{
1049 void __iomem *ioaddr = hw->pcsr;
1050 u32 value;
1051
1052 value = readl(ioaddr + GMAC_PACKET_FILTER);
1053 value |= GMAC_PACKET_FILTER_IPFE;
1054 writel(value, ioaddr + GMAC_PACKET_FILTER);
1055
1056 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1057
1058
1059 if (ipv6) {
1060 value |= GMAC_L3PEN0;
1061 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1062 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1063 if (sa) {
1064 value |= GMAC_L3SAM0;
1065 if (inv)
1066 value |= GMAC_L3SAIM0;
1067 } else {
1068 value |= GMAC_L3DAM0;
1069 if (inv)
1070 value |= GMAC_L3DAIM0;
1071 }
1072 } else {
1073 value &= ~GMAC_L3PEN0;
1074 if (sa) {
1075 value |= GMAC_L3SAM0;
1076 if (inv)
1077 value |= GMAC_L3SAIM0;
1078 } else {
1079 value |= GMAC_L3DAM0;
1080 if (inv)
1081 value |= GMAC_L3DAIM0;
1082 }
1083 }
1084
1085 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1086
1087 if (sa) {
1088 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1089 } else {
1090 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1091 }
1092
1093 if (!en)
1094 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1095
1096 return 0;
1097}
1098
1099static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1100 bool en, bool udp, bool sa, bool inv,
1101 u32 match)
1102{
1103 void __iomem *ioaddr = hw->pcsr;
1104 u32 value;
1105
1106 value = readl(ioaddr + GMAC_PACKET_FILTER);
1107 value |= GMAC_PACKET_FILTER_IPFE;
1108 writel(value, ioaddr + GMAC_PACKET_FILTER);
1109
1110 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1111 if (udp) {
1112 value |= GMAC_L4PEN0;
1113 } else {
1114 value &= ~GMAC_L4PEN0;
1115 }
1116
1117 value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1118 value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1119 if (sa) {
1120 value |= GMAC_L4SPM0;
1121 if (inv)
1122 value |= GMAC_L4SPIM0;
1123 } else {
1124 value |= GMAC_L4DPM0;
1125 if (inv)
1126 value |= GMAC_L4DPIM0;
1127 }
1128
1129 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1130
1131 if (sa) {
1132 value = match & GMAC_L4SP0;
1133 } else {
1134 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1135 }
1136
1137 writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1138
1139 if (!en)
1140 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1141
1142 return 0;
1143}
1144
1145const struct stmmac_ops dwmac4_ops = {
1146 .core_init = dwmac4_core_init,
1147 .set_mac = stmmac_set_mac,
1148 .rx_ipc = dwmac4_rx_ipc_enable,
1149 .rx_queue_enable = dwmac4_rx_queue_enable,
1150 .rx_queue_prio = dwmac4_rx_queue_priority,
1151 .tx_queue_prio = dwmac4_tx_queue_priority,
1152 .rx_queue_routing = dwmac4_rx_queue_routing,
1153 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1154 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1155 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1156 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1157 .config_cbs = dwmac4_config_cbs,
1158 .dump_regs = dwmac4_dump_regs,
1159 .host_irq_status = dwmac4_irq_status,
1160 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1161 .flow_ctrl = dwmac4_flow_ctrl,
1162 .pmt = dwmac4_pmt,
1163 .set_umac_addr = dwmac4_set_umac_addr,
1164 .get_umac_addr = dwmac4_get_umac_addr,
1165 .set_eee_mode = dwmac4_set_eee_mode,
1166 .reset_eee_mode = dwmac4_reset_eee_mode,
1167 .set_eee_timer = dwmac4_set_eee_timer,
1168 .set_eee_pls = dwmac4_set_eee_pls,
1169 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1170 .pcs_rane = dwmac4_rane,
1171 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1172 .debug = dwmac4_debug,
1173 .set_filter = dwmac4_set_filter,
1174 .set_mac_loopback = dwmac4_set_mac_loopback,
1175 .update_vlan_hash = dwmac4_update_vlan_hash,
1176 .sarc_configure = dwmac4_sarc_configure,
1177 .enable_vlan = dwmac4_enable_vlan,
1178 .set_arp_offload = dwmac4_set_arp_offload,
1179 .config_l3_filter = dwmac4_config_l3_filter,
1180 .config_l4_filter = dwmac4_config_l4_filter,
1181 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1182 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1183 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1184};
1185
1186const struct stmmac_ops dwmac410_ops = {
1187 .core_init = dwmac4_core_init,
1188 .set_mac = stmmac_dwmac4_set_mac,
1189 .rx_ipc = dwmac4_rx_ipc_enable,
1190 .rx_queue_enable = dwmac4_rx_queue_enable,
1191 .rx_queue_prio = dwmac4_rx_queue_priority,
1192 .tx_queue_prio = dwmac4_tx_queue_priority,
1193 .rx_queue_routing = dwmac4_rx_queue_routing,
1194 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1195 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1196 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1197 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1198 .config_cbs = dwmac4_config_cbs,
1199 .dump_regs = dwmac4_dump_regs,
1200 .host_irq_status = dwmac4_irq_status,
1201 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1202 .flow_ctrl = dwmac4_flow_ctrl,
1203 .pmt = dwmac4_pmt,
1204 .set_umac_addr = dwmac4_set_umac_addr,
1205 .get_umac_addr = dwmac4_get_umac_addr,
1206 .set_eee_mode = dwmac4_set_eee_mode,
1207 .reset_eee_mode = dwmac4_reset_eee_mode,
1208 .set_eee_timer = dwmac4_set_eee_timer,
1209 .set_eee_pls = dwmac4_set_eee_pls,
1210 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1211 .pcs_rane = dwmac4_rane,
1212 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1213 .debug = dwmac4_debug,
1214 .set_filter = dwmac4_set_filter,
1215 .flex_pps_config = dwmac5_flex_pps_config,
1216 .set_mac_loopback = dwmac4_set_mac_loopback,
1217 .update_vlan_hash = dwmac4_update_vlan_hash,
1218 .sarc_configure = dwmac4_sarc_configure,
1219 .enable_vlan = dwmac4_enable_vlan,
1220 .set_arp_offload = dwmac4_set_arp_offload,
1221 .config_l3_filter = dwmac4_config_l3_filter,
1222 .config_l4_filter = dwmac4_config_l4_filter,
1223 .est_configure = dwmac5_est_configure,
1224 .fpe_configure = dwmac5_fpe_configure,
1225 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1226 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1227 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1228};
1229
1230const struct stmmac_ops dwmac510_ops = {
1231 .core_init = dwmac4_core_init,
1232 .set_mac = stmmac_dwmac4_set_mac,
1233 .rx_ipc = dwmac4_rx_ipc_enable,
1234 .rx_queue_enable = dwmac4_rx_queue_enable,
1235 .rx_queue_prio = dwmac4_rx_queue_priority,
1236 .tx_queue_prio = dwmac4_tx_queue_priority,
1237 .rx_queue_routing = dwmac4_rx_queue_routing,
1238 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1239 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1240 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1241 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1242 .config_cbs = dwmac4_config_cbs,
1243 .dump_regs = dwmac4_dump_regs,
1244 .host_irq_status = dwmac4_irq_status,
1245 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1246 .flow_ctrl = dwmac4_flow_ctrl,
1247 .pmt = dwmac4_pmt,
1248 .set_umac_addr = dwmac4_set_umac_addr,
1249 .get_umac_addr = dwmac4_get_umac_addr,
1250 .set_eee_mode = dwmac4_set_eee_mode,
1251 .reset_eee_mode = dwmac4_reset_eee_mode,
1252 .set_eee_timer = dwmac4_set_eee_timer,
1253 .set_eee_pls = dwmac4_set_eee_pls,
1254 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1255 .pcs_rane = dwmac4_rane,
1256 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1257 .debug = dwmac4_debug,
1258 .set_filter = dwmac4_set_filter,
1259 .safety_feat_config = dwmac5_safety_feat_config,
1260 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1261 .safety_feat_dump = dwmac5_safety_feat_dump,
1262 .rxp_config = dwmac5_rxp_config,
1263 .flex_pps_config = dwmac5_flex_pps_config,
1264 .set_mac_loopback = dwmac4_set_mac_loopback,
1265 .update_vlan_hash = dwmac4_update_vlan_hash,
1266 .sarc_configure = dwmac4_sarc_configure,
1267 .enable_vlan = dwmac4_enable_vlan,
1268 .set_arp_offload = dwmac4_set_arp_offload,
1269 .config_l3_filter = dwmac4_config_l3_filter,
1270 .config_l4_filter = dwmac4_config_l4_filter,
1271 .est_configure = dwmac5_est_configure,
1272 .fpe_configure = dwmac5_fpe_configure,
1273 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1274 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1275 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1276};
1277
1278static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1279{
1280 u32 val, num_vlan;
1281
1282 val = readl(ioaddr + GMAC_HW_FEATURE3);
1283 switch (val & GMAC_HW_FEAT_NRVF) {
1284 case 0:
1285 num_vlan = 1;
1286 break;
1287 case 1:
1288 num_vlan = 4;
1289 break;
1290 case 2:
1291 num_vlan = 8;
1292 break;
1293 case 3:
1294 num_vlan = 16;
1295 break;
1296 case 4:
1297 num_vlan = 24;
1298 break;
1299 case 5:
1300 num_vlan = 32;
1301 break;
1302 default:
1303 num_vlan = 1;
1304 }
1305
1306 return num_vlan;
1307}
1308
1309int dwmac4_setup(struct stmmac_priv *priv)
1310{
1311 struct mac_device_info *mac = priv->hw;
1312
1313 dev_info(priv->device, "\tDWMAC4/5\n");
1314
1315 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1316 mac->pcsr = priv->ioaddr;
1317 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1318 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1319 mac->mcast_bits_log2 = 0;
1320
1321 if (mac->multicast_filter_bins)
1322 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1323
1324 mac->link.duplex = GMAC_CONFIG_DM;
1325 mac->link.speed10 = GMAC_CONFIG_PS;
1326 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1327 mac->link.speed1000 = 0;
1328 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1329 mac->mii.addr = GMAC_MDIO_ADDR;
1330 mac->mii.data = GMAC_MDIO_DATA;
1331 mac->mii.addr_shift = 21;
1332 mac->mii.addr_mask = GENMASK(25, 21);
1333 mac->mii.reg_shift = 16;
1334 mac->mii.reg_mask = GENMASK(20, 16);
1335 mac->mii.clk_csr_shift = 8;
1336 mac->mii.clk_csr_mask = GENMASK(11, 8);
1337 mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1338
1339 return 0;
1340}
1341
