LXR linux/drivers/ptp/ptp

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
   4 *
   5 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
   6 */
   7#ifndef PTP_IDT82P33_H
   8#define PTP_IDT82P33_H
   9
  10#include <linux/ktime.h>
  11#include <linux/workqueue.h>
  12
  13
  14/* Register Map - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf */
  15#define PAGE_NUM (8)
  16#define _ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
  17#define _PAGE(addr) (((addr) >> 0x7) & 0x7)
  18#define _OFFSET(addr)  ((addr) & 0x7f)
  19
  20#define DPLL1_TOD_CNFG 0x134
  21#define DPLL2_TOD_CNFG 0x1B4
  22
  23#define DPLL1_TOD_STS 0x10B
  24#define DPLL2_TOD_STS 0x18B
  25
  26#define DPLL1_TOD_TRIGGER 0x115
  27#define DPLL2_TOD_TRIGGER 0x195
  28
  29#define DPLL1_OPERATING_MODE_CNFG 0x120
  30#define DPLL2_OPERATING_MODE_CNFG 0x1A0
  31
  32#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
  33#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
  34
  35#define DPLL1_PHASE_OFFSET_CNFG 0x143
  36#define DPLL2_PHASE_OFFSET_CNFG 0x1C3
  37
  38#define DPLL1_SYNC_EDGE_CNFG 0X140
  39#define DPLL2_SYNC_EDGE_CNFG 0X1C0
  40
  41#define DPLL1_INPUT_MODE_CNFG 0X116
  42#define DPLL2_INPUT_MODE_CNFG 0X196
  43
  44#define OUT_MUX_CNFG(outn) _ADDR(0x6, (0xC * (outn)))
  45
  46#define PAGE_ADDR 0x7F
  47/* Register Map end */
  48
  49/* Register definitions - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf*/
  50#define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
  51#define SYNC_TOD BIT(1)
  52#define PH_OFFSET_EN BIT(7)
  53#define SQUELCH_ENABLE BIT(5)
  54
  55/* Bit definitions for the DPLL_MODE register */
  56#define PLL_MODE_SHIFT                    (0)
  57#define PLL_MODE_MASK                     (0x1F)
  58
  59enum pll_mode {
  60        PLL_MODE_MIN = 0,
  61        PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
  62        PLL_MODE_FORCE_FREERUN = 1,
  63        PLL_MODE_FORCE_HOLDOVER = 2,
  64        PLL_MODE_FORCE_LOCKED = 4,
  65        PLL_MODE_FORCE_PRE_LOCKED2 = 5,
  66        PLL_MODE_FORCE_PRE_LOCKED = 6,
  67        PLL_MODE_FORCE_LOST_PHASE = 7,
  68        PLL_MODE_DCO = 10,
  69        PLL_MODE_WPH = 18,
  70        PLL_MODE_MAX = PLL_MODE_WPH,
  71};
  72
  73enum hw_tod_trig_sel {
  74        HW_TOD_TRIG_SEL_MIN = 0,
  75        HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
  76        HW_TOD_TRIG_SEL_SYNC_SEL = 1,
  77        HW_TOD_TRIG_SEL_IN12 = 2,
  78        HW_TOD_TRIG_SEL_IN13 = 3,
  79        HW_TOD_TRIG_SEL_IN14 = 4,
  80        HW_TOD_TRIG_SEL_TOD_PPS = 5,
  81        HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
  82        HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
  83        HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
  84        HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
  85        HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
  86        WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
  87};
  88
  89/* Register bit definitions end */
  90#define FW_FILENAME     "idt82p33xxx.bin"
  91#define MAX_PHC_PLL (2)
  92#define TOD_BYTE_COUNT (10)
  93#define MAX_MEASURMENT_COUNT (5)
  94#define SNAP_THRESHOLD_NS (150000)
  95#define SYNC_TOD_TIMEOUT_SEC (5)
  96
  97#define PLLMASK_ADDR_HI 0xFF
  98#define PLLMASK_ADDR_LO 0xA5
  99
 100#define PLL0_OUTMASK_ADDR_HI    0xFF
 101#define PLL0_OUTMASK_ADDR_LO    0xB0
 102
 103#define PLL1_OUTMASK_ADDR_HI    0xFF
 104#define PLL1_OUTMASK_ADDR_LO    0xB2
 105
 106#define PLL2_OUTMASK_ADDR_HI    0xFF
 107#define PLL2_OUTMASK_ADDR_LO    0xB4
 108
 109#define PLL3_OUTMASK_ADDR_HI    0xFF
 110#define PLL3_OUTMASK_ADDR_LO    0xB6
 111
 112#define DEFAULT_PLL_MASK        (0x01)
 113#define DEFAULT_OUTPUT_MASK_PLL0        (0xc0)
 114#define DEFAULT_OUTPUT_MASK_PLL1        DEFAULT_OUTPUT_MASK_PLL0
 115
 116/* PTP Hardware Clock interface */
 117struct idt82p33_channel {
 118        struct ptp_clock_info   caps;
 119        struct ptp_clock        *ptp_clock;
 120        struct idt82p33 *idt82p33;
 121        enum pll_mode   pll_mode;
 122        /* task to turn off SYNC_TOD bit after pps sync */
 123        struct delayed_work     sync_tod_work;
 124        bool                    sync_tod_on;
 125        s32                     current_freq_ppb;
 126        u8                      output_mask;
 127        u16                     dpll_tod_cnfg;
 128        u16                     dpll_tod_trigger;
 129        u16                     dpll_tod_sts;
 130        u16                     dpll_mode_cnfg;
 131        u16                     dpll_freq_cnfg;
 132        u16                     dpll_phase_cnfg;
 133        u16                     dpll_sync_cnfg;
 134        u16                     dpll_input_mode_cnfg;
 135};
 136
 137struct idt82p33 {
 138        struct idt82p33_channel channel[MAX_PHC_PLL];
 139        struct i2c_client       *client;
 140        u8      page_offset;
 141        u8      pll_mask;
 142        ktime_t start_time;
 143        int calculate_overhead_flag;
 144        s64 tod_write_overhead_ns;
 145        /* Protects I2C read/modify/write registers from concurrent access */
 146        struct mutex    reg_lock;
 147};
 148
 149/* firmware interface */
 150struct idt82p33_fwrc {
 151        u8 hiaddr;
 152        u8 loaddr;
 153        u8 value;
 154        u8 reserved;
 155} __packed;
 156
 157/**
 158 * @brief Maximum absolute value for write phase offset in femtoseconds
 159 */
 160#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
 161
 162/** @brief Phase offset resolution
 163 *
 164 *  DPLL phase offset = 10^15 fs / ( System Clock  * 2^13)
 165 *                    = 10^15 fs / ( 1638400000 * 2^23)
 166 *                    = 74.5058059692382 fs
 167 */
 168#define IDT_T0DPLL_PHASE_RESOL 74506
 169
 170
 171#endif /* PTP_IDT82P33_H */
 172