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11#include <linux/clk.h>
12#include <linux/console.h>
13#include <linux/delay.h>
14#include <linux/dma-direction.h>
15#include <linux/dmaengine.h>
16#include <linux/dma-mapping.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/pm_wakeirq.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
29#include <linux/spinlock.h>
30#include <linux/sysrq.h>
31#include <linux/tty_flip.h>
32#include <linux/tty.h>
33
34#include "serial_mctrl_gpio.h"
35#include "stm32-usart.h"
36
37static void stm32_stop_tx(struct uart_port *port);
38static void stm32_transmit_chars(struct uart_port *port);
39
40static inline struct stm32_port *to_stm32_port(struct uart_port *port)
41{
42 return container_of(port, struct stm32_port, port);
43}
44
45static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
46{
47 u32 val;
48
49 val = readl_relaxed(port->membase + reg);
50 val |= bits;
51 writel_relaxed(val, port->membase + reg);
52}
53
54static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
55{
56 u32 val;
57
58 val = readl_relaxed(port->membase + reg);
59 val &= ~bits;
60 writel_relaxed(val, port->membase + reg);
61}
62
63static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
64 u32 delay_DDE, u32 baud)
65{
66 u32 rs485_deat_dedt;
67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
68 bool over8;
69
70 *cr3 |= USART_CR3_DEM;
71 over8 = *cr1 & USART_CR1_OVER8;
72
73 if (over8)
74 rs485_deat_dedt = delay_ADE * baud * 8;
75 else
76 rs485_deat_dedt = delay_ADE * baud * 16;
77
78 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
79 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
80 rs485_deat_dedt_max : rs485_deat_dedt;
81 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
82 USART_CR1_DEAT_MASK;
83 *cr1 |= rs485_deat_dedt;
84
85 if (over8)
86 rs485_deat_dedt = delay_DDE * baud * 8;
87 else
88 rs485_deat_dedt = delay_DDE * baud * 16;
89
90 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
91 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
92 rs485_deat_dedt_max : rs485_deat_dedt;
93 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
94 USART_CR1_DEDT_MASK;
95 *cr1 |= rs485_deat_dedt;
96}
97
98static int stm32_config_rs485(struct uart_port *port,
99 struct serial_rs485 *rs485conf)
100{
101 struct stm32_port *stm32_port = to_stm32_port(port);
102 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
103 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
104 u32 usartdiv, baud, cr1, cr3;
105 bool over8;
106
107 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
108
109 port->rs485 = *rs485conf;
110
111 rs485conf->flags |= SER_RS485_RX_DURING_TX;
112
113 if (rs485conf->flags & SER_RS485_ENABLED) {
114 cr1 = readl_relaxed(port->membase + ofs->cr1);
115 cr3 = readl_relaxed(port->membase + ofs->cr3);
116 usartdiv = readl_relaxed(port->membase + ofs->brr);
117 usartdiv = usartdiv & GENMASK(15, 0);
118 over8 = cr1 & USART_CR1_OVER8;
119
120 if (over8)
121 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
122 << USART_BRR_04_R_SHIFT;
123
124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
125 stm32_config_reg_rs485(&cr1, &cr3,
126 rs485conf->delay_rts_before_send,
127 rs485conf->delay_rts_after_send, baud);
128
129 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
130 cr3 &= ~USART_CR3_DEP;
131 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
132 } else {
133 cr3 |= USART_CR3_DEP;
134 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
135 }
136
137 writel_relaxed(cr3, port->membase + ofs->cr3);
138 writel_relaxed(cr1, port->membase + ofs->cr1);
139 } else {
140 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
141 stm32_clr_bits(port, ofs->cr1,
142 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
143 }
144
145 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
146
147 return 0;
148}
149
150static int stm32_init_rs485(struct uart_port *port,
151 struct platform_device *pdev)
152{
153 struct serial_rs485 *rs485conf = &port->rs485;
154
155 rs485conf->flags = 0;
156 rs485conf->delay_rts_before_send = 0;
157 rs485conf->delay_rts_after_send = 0;
158
159 if (!pdev->dev.of_node)
160 return -ENODEV;
161
162 return uart_get_rs485_mode(port);
163}
164
165static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
166 bool threaded)
167{
168 struct stm32_port *stm32_port = to_stm32_port(port);
169 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
170 enum dma_status status;
171 struct dma_tx_state state;
172
173 *sr = readl_relaxed(port->membase + ofs->isr);
174
175 if (threaded && stm32_port->rx_ch) {
176 status = dmaengine_tx_status(stm32_port->rx_ch,
177 stm32_port->rx_ch->cookie,
178 &state);
179 if ((status == DMA_IN_PROGRESS) &&
180 (*last_res != state.residue))
181 return 1;
182 else
183 return 0;
184 } else if (*sr & USART_SR_RXNE) {
185 return 1;
186 }
187 return 0;
188}
189
190static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
191 int *last_res)
192{
193 struct stm32_port *stm32_port = to_stm32_port(port);
194 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
195 unsigned long c;
196
197 if (stm32_port->rx_ch) {
198 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
199 if ((*last_res) == 0)
200 *last_res = RX_BUF_L;
201 } else {
202 c = readl_relaxed(port->membase + ofs->rdr);
203
204 c &= stm32_port->rdr_mask;
205 }
206
207 return c;
208}
209
210static void stm32_receive_chars(struct uart_port *port, bool threaded)
211{
212 struct tty_port *tport = &port->state->port;
213 struct stm32_port *stm32_port = to_stm32_port(port);
214 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
215 unsigned long c;
216 u32 sr;
217 char flag;
218
219 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
220 pm_wakeup_event(tport->tty->dev, 0);
221
222 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
223 sr |= USART_SR_DUMMY_RX;
224 flag = TTY_NORMAL;
225
226
227
228
229
230
231
232
233
234
235
236
237 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
238 writel_relaxed(sr & USART_SR_ERR_MASK,
239 port->membase + ofs->icr);
240
241 c = stm32_get_char(port, &sr, &stm32_port->last_res);
242 port->icount.rx++;
243 if (sr & USART_SR_ERR_MASK) {
244 if (sr & USART_SR_ORE) {
245 port->icount.overrun++;
246 } else if (sr & USART_SR_PE) {
247 port->icount.parity++;
248 } else if (sr & USART_SR_FE) {
249
250 if (!c) {
251 port->icount.brk++;
252 if (uart_handle_break(port))
253 continue;
254 } else {
255 port->icount.frame++;
256 }
257 }
258
259 sr &= port->read_status_mask;
260
261 if (sr & USART_SR_PE) {
262 flag = TTY_PARITY;
263 } else if (sr & USART_SR_FE) {
264 if (!c)
265 flag = TTY_BREAK;
266 else
267 flag = TTY_FRAME;
268 }
269 }
270
271 if (uart_handle_sysrq_char(port, c))
272 continue;
273 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
274 }
275
276 spin_unlock(&port->lock);
277 tty_flip_buffer_push(tport);
278 spin_lock(&port->lock);
279}
280
281static void stm32_tx_dma_complete(void *arg)
282{
283 struct uart_port *port = arg;
284 struct stm32_port *stm32port = to_stm32_port(port);
285 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
286
287 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
288 stm32port->tx_dma_busy = false;
289
290
291 stm32_transmit_chars(port);
292}
293
294static void stm32_tx_interrupt_enable(struct uart_port *port)
295{
296 struct stm32_port *stm32_port = to_stm32_port(port);
297 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
298
299
300
301
302
303 if (stm32_port->fifoen)
304 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
305 else
306 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
307}
308
309static void stm32_tx_interrupt_disable(struct uart_port *port)
310{
311 struct stm32_port *stm32_port = to_stm32_port(port);
312 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
313
314 if (stm32_port->fifoen)
315 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
316 else
317 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
318}
319
320static void stm32_transmit_chars_pio(struct uart_port *port)
321{
322 struct stm32_port *stm32_port = to_stm32_port(port);
323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
324 struct circ_buf *xmit = &port->state->xmit;
325
326 if (stm32_port->tx_dma_busy) {
327 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
328 stm32_port->tx_dma_busy = false;
329 }
330
331 while (!uart_circ_empty(xmit)) {
332
333 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
334 break;
335 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
336 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
337 port->icount.tx++;
338 }
339
340
341 if (uart_circ_empty(xmit))
342 stm32_tx_interrupt_disable(port);
343 else
344 stm32_tx_interrupt_enable(port);
345}
346
347static void stm32_transmit_chars_dma(struct uart_port *port)
348{
349 struct stm32_port *stm32port = to_stm32_port(port);
350 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
351 struct circ_buf *xmit = &port->state->xmit;
352 struct dma_async_tx_descriptor *desc = NULL;
353 dma_cookie_t cookie;
354 unsigned int count, i;
355
356 if (stm32port->tx_dma_busy)
357 return;
358
359 stm32port->tx_dma_busy = true;
360
361 count = uart_circ_chars_pending(xmit);
362
363 if (count > TX_BUF_L)
364 count = TX_BUF_L;
365
366 if (xmit->tail < xmit->head) {
367 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
368 } else {
369 size_t one = UART_XMIT_SIZE - xmit->tail;
370 size_t two;
371
372 if (one > count)
373 one = count;
374 two = count - one;
375
376 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
377 if (two)
378 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
379 }
380
381 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
382 stm32port->tx_dma_buf,
383 count,
384 DMA_MEM_TO_DEV,
385 DMA_PREP_INTERRUPT);
386
387 if (!desc) {
388 for (i = count; i > 0; i--)
389 stm32_transmit_chars_pio(port);
390 return;
391 }
392
393 desc->callback = stm32_tx_dma_complete;
394 desc->callback_param = port;
395
396
397 cookie = dmaengine_submit(desc);
398
399
400 dma_async_issue_pending(stm32port->tx_ch);
401
402 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
403
404 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
405 port->icount.tx += count;
406}
407
408static void stm32_transmit_chars(struct uart_port *port)
409{
410 struct stm32_port *stm32_port = to_stm32_port(port);
411 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
412 struct circ_buf *xmit = &port->state->xmit;
413
414 if (port->x_char) {
415 if (stm32_port->tx_dma_busy)
416 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
417 writel_relaxed(port->x_char, port->membase + ofs->tdr);
418 port->x_char = 0;
419 port->icount.tx++;
420 if (stm32_port->tx_dma_busy)
421 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
422 return;
423 }
424
425 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
426 stm32_tx_interrupt_disable(port);
427 return;
428 }
429
430 if (ofs->icr == UNDEF_REG)
431 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
432 else
433 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
434
435 if (stm32_port->tx_ch)
436 stm32_transmit_chars_dma(port);
437 else
438 stm32_transmit_chars_pio(port);
439
440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
441 uart_write_wakeup(port);
442
443 if (uart_circ_empty(xmit))
444 stm32_tx_interrupt_disable(port);
445}
446
447static irqreturn_t stm32_interrupt(int irq, void *ptr)
448{
449 struct uart_port *port = ptr;
450 struct stm32_port *stm32_port = to_stm32_port(port);
451 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
452 u32 sr;
453
454 spin_lock(&port->lock);
455
456 sr = readl_relaxed(port->membase + ofs->isr);
457
458 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
459 writel_relaxed(USART_ICR_RTOCF,
460 port->membase + ofs->icr);
461
462 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
463 writel_relaxed(USART_ICR_WUCF,
464 port->membase + ofs->icr);
465
466 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
467 stm32_receive_chars(port, false);
468
469 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
470 stm32_transmit_chars(port);
471
472 spin_unlock(&port->lock);
473
474 if (stm32_port->rx_ch)
475 return IRQ_WAKE_THREAD;
476 else
477 return IRQ_HANDLED;
478}
479
480static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
481{
482 struct uart_port *port = ptr;
483 struct stm32_port *stm32_port = to_stm32_port(port);
484
485 spin_lock(&port->lock);
486
487 if (stm32_port->rx_ch)
488 stm32_receive_chars(port, true);
489
490 spin_unlock(&port->lock);
491
492 return IRQ_HANDLED;
493}
494
495static unsigned int stm32_tx_empty(struct uart_port *port)
496{
497 struct stm32_port *stm32_port = to_stm32_port(port);
498 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
499
500 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
501}
502
503static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
504{
505 struct stm32_port *stm32_port = to_stm32_port(port);
506 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
507
508 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
509 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
510 else
511 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
512
513 mctrl_gpio_set(stm32_port->gpios, mctrl);
514}
515
516static unsigned int stm32_get_mctrl(struct uart_port *port)
517{
518 struct stm32_port *stm32_port = to_stm32_port(port);
519 unsigned int ret;
520
521
522 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
523
524 return mctrl_gpio_get(stm32_port->gpios, &ret);
525}
526
527static void stm32_enable_ms(struct uart_port *port)
528{
529 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
530}
531
532static void stm32_disable_ms(struct uart_port *port)
533{
534 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
535}
536
537
538static void stm32_stop_tx(struct uart_port *port)
539{
540 struct stm32_port *stm32_port = to_stm32_port(port);
541 struct serial_rs485 *rs485conf = &port->rs485;
542
543 stm32_tx_interrupt_disable(port);
544
545 if (rs485conf->flags & SER_RS485_ENABLED) {
546 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
547 mctrl_gpio_set(stm32_port->gpios,
548 stm32_port->port.mctrl & ~TIOCM_RTS);
549 } else {
550 mctrl_gpio_set(stm32_port->gpios,
551 stm32_port->port.mctrl | TIOCM_RTS);
552 }
553 }
554}
555
556
557static void stm32_start_tx(struct uart_port *port)
558{
559 struct stm32_port *stm32_port = to_stm32_port(port);
560 struct serial_rs485 *rs485conf = &port->rs485;
561 struct circ_buf *xmit = &port->state->xmit;
562
563 if (uart_circ_empty(xmit))
564 return;
565
566 if (rs485conf->flags & SER_RS485_ENABLED) {
567 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
568 mctrl_gpio_set(stm32_port->gpios,
569 stm32_port->port.mctrl | TIOCM_RTS);
570 } else {
571 mctrl_gpio_set(stm32_port->gpios,
572 stm32_port->port.mctrl & ~TIOCM_RTS);
573 }
574 }
575
576 stm32_transmit_chars(port);
577}
578
579
580static void stm32_throttle(struct uart_port *port)
581{
582 struct stm32_port *stm32_port = to_stm32_port(port);
583 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
584 unsigned long flags;
585
586 spin_lock_irqsave(&port->lock, flags);
587 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
588 if (stm32_port->cr3_irq)
589 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
590
591 spin_unlock_irqrestore(&port->lock, flags);
592}
593
594
595static void stm32_unthrottle(struct uart_port *port)
596{
597 struct stm32_port *stm32_port = to_stm32_port(port);
598 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
599 unsigned long flags;
600
601 spin_lock_irqsave(&port->lock, flags);
602 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
603 if (stm32_port->cr3_irq)
604 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
605
606 spin_unlock_irqrestore(&port->lock, flags);
607}
608
609
610static void stm32_stop_rx(struct uart_port *port)
611{
612 struct stm32_port *stm32_port = to_stm32_port(port);
613 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
614
615 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
616 if (stm32_port->cr3_irq)
617 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
618
619}
620
621
622static void stm32_break_ctl(struct uart_port *port, int break_state)
623{
624}
625
626static int stm32_startup(struct uart_port *port)
627{
628 struct stm32_port *stm32_port = to_stm32_port(port);
629 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
630 const char *name = to_platform_device(port->dev)->name;
631 u32 val;
632 int ret;
633
634 ret = request_threaded_irq(port->irq, stm32_interrupt,
635 stm32_threaded_interrupt,
636 IRQF_NO_SUSPEND, name, port);
637 if (ret)
638 return ret;
639
640
641 if (ofs->rqr != UNDEF_REG)
642 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
643
644
645 if (stm32_port->fifoen) {
646 val = readl_relaxed(port->membase + ofs->cr3);
647 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
648 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
649 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
650 writel_relaxed(val, port->membase + ofs->cr3);
651 }
652
653
654 val = stm32_port->cr1_irq | USART_CR1_RE;
655 if (stm32_port->fifoen)
656 val |= USART_CR1_FIFOEN;
657 stm32_set_bits(port, ofs->cr1, val);
658
659 return 0;
660}
661
662static void stm32_shutdown(struct uart_port *port)
663{
664 struct stm32_port *stm32_port = to_stm32_port(port);
665 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
666 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
667 u32 val, isr;
668 int ret;
669
670
671 stm32_disable_ms(port);
672
673 val = USART_CR1_TXEIE | USART_CR1_TE;
674 val |= stm32_port->cr1_irq | USART_CR1_RE;
675 val |= BIT(cfg->uart_enable_bit);
676 if (stm32_port->fifoen)
677 val |= USART_CR1_FIFOEN;
678
679 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
680 isr, (isr & USART_SR_TC),
681 10, 100000);
682
683 if (ret)
684 dev_err(port->dev, "transmission complete not set\n");
685
686 stm32_clr_bits(port, ofs->cr1, val);
687
688 free_irq(port->irq, port);
689}
690
691static unsigned int stm32_get_databits(struct ktermios *termios)
692{
693 unsigned int bits;
694
695 tcflag_t cflag = termios->c_cflag;
696
697 switch (cflag & CSIZE) {
698
699
700
701
702
703 case CS5:
704 bits = 5;
705 break;
706 case CS6:
707 bits = 6;
708 break;
709 case CS7:
710 bits = 7;
711 break;
712
713 default:
714 bits = 8;
715 break;
716 }
717
718 return bits;
719}
720
721static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
722 struct ktermios *old)
723{
724 struct stm32_port *stm32_port = to_stm32_port(port);
725 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
726 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
727 struct serial_rs485 *rs485conf = &port->rs485;
728 unsigned int baud, bits;
729 u32 usartdiv, mantissa, fraction, oversampling;
730 tcflag_t cflag = termios->c_cflag;
731 u32 cr1, cr2, cr3;
732 unsigned long flags;
733
734 if (!stm32_port->hw_flow_control)
735 cflag &= ~CRTSCTS;
736
737 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
738
739 spin_lock_irqsave(&port->lock, flags);
740
741
742 writel_relaxed(0, port->membase + ofs->cr1);
743
744
745 if (ofs->rqr != UNDEF_REG)
746 stm32_set_bits(port, ofs->rqr,
747 USART_RQR_TXFRQ | USART_RQR_RXFRQ);
748
749 cr1 = USART_CR1_TE | USART_CR1_RE;
750 if (stm32_port->fifoen)
751 cr1 |= USART_CR1_FIFOEN;
752 cr2 = 0;
753 cr3 = readl_relaxed(port->membase + ofs->cr3);
754 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
755 | USART_CR3_TXFTCFG_MASK;
756
757 if (cflag & CSTOPB)
758 cr2 |= USART_CR2_STOP_2B;
759
760 bits = stm32_get_databits(termios);
761 stm32_port->rdr_mask = (BIT(bits) - 1);
762
763 if (cflag & PARENB) {
764 bits++;
765 cr1 |= USART_CR1_PCE;
766 }
767
768
769
770
771
772
773
774
775 if (bits == 9)
776 cr1 |= USART_CR1_M0;
777 else if ((bits == 7) && cfg->has_7bits_data)
778 cr1 |= USART_CR1_M1;
779 else if (bits != 8)
780 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
781 , bits);
782
783 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
784 stm32_port->fifoen)) {
785 if (cflag & CSTOPB)
786 bits = bits + 3;
787 else
788 bits = bits + 2;
789
790
791 stm32_port->cr1_irq = USART_CR1_RTOIE;
792 writel_relaxed(bits, port->membase + ofs->rtor);
793 cr2 |= USART_CR2_RTOEN;
794
795 if (!stm32_port->rx_ch)
796 stm32_port->cr3_irq = USART_CR3_RXFTIE;
797 }
798
799 cr1 |= stm32_port->cr1_irq;
800 cr3 |= stm32_port->cr3_irq;
801
802 if (cflag & PARODD)
803 cr1 |= USART_CR1_PS;
804
805 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
806 if (cflag & CRTSCTS) {
807 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
808 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
809 }
810
811
812 if (UART_ENABLE_MS(port, termios->c_cflag))
813 stm32_enable_ms(port);
814 else
815 stm32_disable_ms(port);
816
817 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
818
819
820
821
822
823
824
825 if (usartdiv < 16) {
826 oversampling = 8;
827 cr1 |= USART_CR1_OVER8;
828 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
829 } else {
830 oversampling = 16;
831 cr1 &= ~USART_CR1_OVER8;
832 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
833 }
834
835 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
836 fraction = usartdiv % oversampling;
837 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
838
839 uart_update_timeout(port, cflag, baud);
840
841 port->read_status_mask = USART_SR_ORE;
842 if (termios->c_iflag & INPCK)
843 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
844 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
845 port->read_status_mask |= USART_SR_FE;
846
847
848 port->ignore_status_mask = 0;
849 if (termios->c_iflag & IGNPAR)
850 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
851 if (termios->c_iflag & IGNBRK) {
852 port->ignore_status_mask |= USART_SR_FE;
853
854
855
856
857 if (termios->c_iflag & IGNPAR)
858 port->ignore_status_mask |= USART_SR_ORE;
859 }
860
861
862 if ((termios->c_cflag & CREAD) == 0)
863 port->ignore_status_mask |= USART_SR_DUMMY_RX;
864
865 if (stm32_port->rx_ch)
866 cr3 |= USART_CR3_DMAR;
867
868 if (rs485conf->flags & SER_RS485_ENABLED) {
869 stm32_config_reg_rs485(&cr1, &cr3,
870 rs485conf->delay_rts_before_send,
871 rs485conf->delay_rts_after_send, baud);
872 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
873 cr3 &= ~USART_CR3_DEP;
874 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
875 } else {
876 cr3 |= USART_CR3_DEP;
877 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
878 }
879
880 } else {
881 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
882 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
883 }
884
885 writel_relaxed(cr3, port->membase + ofs->cr3);
886 writel_relaxed(cr2, port->membase + ofs->cr2);
887 writel_relaxed(cr1, port->membase + ofs->cr1);
888
889 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
890 spin_unlock_irqrestore(&port->lock, flags);
891}
892
893static const char *stm32_type(struct uart_port *port)
894{
895 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
896}
897
898static void stm32_release_port(struct uart_port *port)
899{
900}
901
902static int stm32_request_port(struct uart_port *port)
903{
904 return 0;
905}
906
907static void stm32_config_port(struct uart_port *port, int flags)
908{
909 if (flags & UART_CONFIG_TYPE)
910 port->type = PORT_STM32;
911}
912
913static int
914stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
915{
916
917 return -EINVAL;
918}
919
920static void stm32_pm(struct uart_port *port, unsigned int state,
921 unsigned int oldstate)
922{
923 struct stm32_port *stm32port = container_of(port,
924 struct stm32_port, port);
925 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
926 struct stm32_usart_config *cfg = &stm32port->info->cfg;
927 unsigned long flags = 0;
928
929 switch (state) {
930 case UART_PM_STATE_ON:
931 pm_runtime_get_sync(port->dev);
932 break;
933 case UART_PM_STATE_OFF:
934 spin_lock_irqsave(&port->lock, flags);
935 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
936 spin_unlock_irqrestore(&port->lock, flags);
937 pm_runtime_put_sync(port->dev);
938 break;
939 }
940}
941
942static const struct uart_ops stm32_uart_ops = {
943 .tx_empty = stm32_tx_empty,
944 .set_mctrl = stm32_set_mctrl,
945 .get_mctrl = stm32_get_mctrl,
946 .stop_tx = stm32_stop_tx,
947 .start_tx = stm32_start_tx,
948 .throttle = stm32_throttle,
949 .unthrottle = stm32_unthrottle,
950 .stop_rx = stm32_stop_rx,
951 .enable_ms = stm32_enable_ms,
952 .break_ctl = stm32_break_ctl,
953 .startup = stm32_startup,
954 .shutdown = stm32_shutdown,
955 .set_termios = stm32_set_termios,
956 .pm = stm32_pm,
957 .type = stm32_type,
958 .release_port = stm32_release_port,
959 .request_port = stm32_request_port,
960 .config_port = stm32_config_port,
961 .verify_port = stm32_verify_port,
962};
963
964static int stm32_init_port(struct stm32_port *stm32port,
965 struct platform_device *pdev)
966{
967 struct uart_port *port = &stm32port->port;
968 struct resource *res;
969 int ret;
970
971 port->iotype = UPIO_MEM;
972 port->flags = UPF_BOOT_AUTOCONF;
973 port->ops = &stm32_uart_ops;
974 port->dev = &pdev->dev;
975 port->fifosize = stm32port->info->cfg.fifosize;
976 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
977
978 ret = platform_get_irq(pdev, 0);
979 if (ret <= 0)
980 return ret ? : -ENODEV;
981 port->irq = ret;
982
983 port->rs485_config = stm32_config_rs485;
984
985 ret = stm32_init_rs485(port, pdev);
986 if (ret)
987 return ret;
988
989 if (stm32port->info->cfg.has_wakeup) {
990 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
991 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
992 return stm32port->wakeirq ? : -ENODEV;
993 }
994
995 stm32port->fifoen = stm32port->info->cfg.has_fifo;
996
997 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
998 port->membase = devm_ioremap_resource(&pdev->dev, res);
999 if (IS_ERR(port->membase))
1000 return PTR_ERR(port->membase);
1001 port->mapbase = res->start;
1002
1003 spin_lock_init(&port->lock);
1004
1005 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1006 if (IS_ERR(stm32port->clk))
1007 return PTR_ERR(stm32port->clk);
1008
1009
1010 ret = clk_prepare_enable(stm32port->clk);
1011 if (ret)
1012 return ret;
1013
1014 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1015 if (!stm32port->port.uartclk) {
1016 ret = -EINVAL;
1017 goto err_clk;
1018 }
1019
1020 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1021 if (IS_ERR(stm32port->gpios)) {
1022 ret = PTR_ERR(stm32port->gpios);
1023 goto err_clk;
1024 }
1025
1026
1027 if (stm32port->hw_flow_control) {
1028 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1029 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1030 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1031 ret = -EINVAL;
1032 goto err_clk;
1033 }
1034 }
1035
1036 return ret;
1037
1038err_clk:
1039 clk_disable_unprepare(stm32port->clk);
1040
1041 return ret;
1042}
1043
1044static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
1045{
1046 struct device_node *np = pdev->dev.of_node;
1047 int id;
1048
1049 if (!np)
1050 return NULL;
1051
1052 id = of_alias_get_id(np, "serial");
1053 if (id < 0) {
1054 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1055 return NULL;
1056 }
1057
1058 if (WARN_ON(id >= STM32_MAX_PORTS))
1059 return NULL;
1060
1061 stm32_ports[id].hw_flow_control =
1062 of_property_read_bool (np, "st,hw-flow-ctrl") ||
1063 of_property_read_bool (np, "uart-has-rtscts");
1064 stm32_ports[id].port.line = id;
1065 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1066 stm32_ports[id].cr3_irq = 0;
1067 stm32_ports[id].last_res = RX_BUF_L;
1068 return &stm32_ports[id];
1069}
1070
1071#ifdef CONFIG_OF
1072static const struct of_device_id stm32_match[] = {
1073 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1074 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1075 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1076 {},
1077};
1078
1079MODULE_DEVICE_TABLE(of, stm32_match);
1080#endif
1081
1082static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
1083 struct platform_device *pdev)
1084{
1085 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1086 struct uart_port *port = &stm32port->port;
1087 struct device *dev = &pdev->dev;
1088 struct dma_slave_config config;
1089 struct dma_async_tx_descriptor *desc = NULL;
1090 dma_cookie_t cookie;
1091 int ret;
1092
1093
1094 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1095 if (!stm32port->rx_ch) {
1096 dev_info(dev, "rx dma alloc failed\n");
1097 return -ENODEV;
1098 }
1099 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1100 &stm32port->rx_dma_buf,
1101 GFP_KERNEL);
1102 if (!stm32port->rx_buf) {
1103 ret = -ENOMEM;
1104 goto alloc_err;
1105 }
1106
1107
1108 memset(&config, 0, sizeof(config));
1109 config.src_addr = port->mapbase + ofs->rdr;
1110 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1111
1112 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1113 if (ret < 0) {
1114 dev_err(dev, "rx dma channel config failed\n");
1115 ret = -ENODEV;
1116 goto config_err;
1117 }
1118
1119
1120 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1121 stm32port->rx_dma_buf,
1122 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1123 DMA_PREP_INTERRUPT);
1124 if (!desc) {
1125 dev_err(dev, "rx dma prep cyclic failed\n");
1126 ret = -ENODEV;
1127 goto config_err;
1128 }
1129
1130
1131 desc->callback = NULL;
1132 desc->callback_param = NULL;
1133
1134
1135 cookie = dmaengine_submit(desc);
1136
1137
1138 dma_async_issue_pending(stm32port->rx_ch);
1139
1140 return 0;
1141
1142config_err:
1143 dma_free_coherent(&pdev->dev,
1144 RX_BUF_L, stm32port->rx_buf,
1145 stm32port->rx_dma_buf);
1146
1147alloc_err:
1148 dma_release_channel(stm32port->rx_ch);
1149 stm32port->rx_ch = NULL;
1150
1151 return ret;
1152}
1153
1154static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1155 struct platform_device *pdev)
1156{
1157 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1158 struct uart_port *port = &stm32port->port;
1159 struct device *dev = &pdev->dev;
1160 struct dma_slave_config config;
1161 int ret;
1162
1163 stm32port->tx_dma_busy = false;
1164
1165
1166 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1167 if (!stm32port->tx_ch) {
1168 dev_info(dev, "tx dma alloc failed\n");
1169 return -ENODEV;
1170 }
1171 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1172 &stm32port->tx_dma_buf,
1173 GFP_KERNEL);
1174 if (!stm32port->tx_buf) {
1175 ret = -ENOMEM;
1176 goto alloc_err;
1177 }
1178
1179
1180 memset(&config, 0, sizeof(config));
1181 config.dst_addr = port->mapbase + ofs->tdr;
1182 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1183
1184 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1185 if (ret < 0) {
1186 dev_err(dev, "tx dma channel config failed\n");
1187 ret = -ENODEV;
1188 goto config_err;
1189 }
1190
1191 return 0;
1192
1193config_err:
1194 dma_free_coherent(&pdev->dev,
1195 TX_BUF_L, stm32port->tx_buf,
1196 stm32port->tx_dma_buf);
1197
1198alloc_err:
1199 dma_release_channel(stm32port->tx_ch);
1200 stm32port->tx_ch = NULL;
1201
1202 return ret;
1203}
1204
1205static int stm32_serial_probe(struct platform_device *pdev)
1206{
1207 const struct of_device_id *match;
1208 struct stm32_port *stm32port;
1209 int ret;
1210
1211 stm32port = stm32_of_get_stm32_port(pdev);
1212 if (!stm32port)
1213 return -ENODEV;
1214
1215 match = of_match_device(stm32_match, &pdev->dev);
1216 if (match && match->data)
1217 stm32port->info = (struct stm32_usart_info *)match->data;
1218 else
1219 return -EINVAL;
1220
1221 ret = stm32_init_port(stm32port, pdev);
1222 if (ret)
1223 return ret;
1224
1225 if (stm32port->wakeirq > 0) {
1226 ret = device_init_wakeup(&pdev->dev, true);
1227 if (ret)
1228 goto err_uninit;
1229
1230 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1231 stm32port->wakeirq);
1232 if (ret)
1233 goto err_nowup;
1234
1235 device_set_wakeup_enable(&pdev->dev, false);
1236 }
1237
1238 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1239 if (ret)
1240 goto err_wirq;
1241
1242 ret = stm32_of_dma_rx_probe(stm32port, pdev);
1243 if (ret)
1244 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1245
1246 ret = stm32_of_dma_tx_probe(stm32port, pdev);
1247 if (ret)
1248 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1249
1250 platform_set_drvdata(pdev, &stm32port->port);
1251
1252 pm_runtime_get_noresume(&pdev->dev);
1253 pm_runtime_set_active(&pdev->dev);
1254 pm_runtime_enable(&pdev->dev);
1255 pm_runtime_put_sync(&pdev->dev);
1256
1257 return 0;
1258
1259err_wirq:
1260 if (stm32port->wakeirq > 0)
1261 dev_pm_clear_wake_irq(&pdev->dev);
1262
1263err_nowup:
1264 if (stm32port->wakeirq > 0)
1265 device_init_wakeup(&pdev->dev, false);
1266
1267err_uninit:
1268 clk_disable_unprepare(stm32port->clk);
1269
1270 return ret;
1271}
1272
1273static int stm32_serial_remove(struct platform_device *pdev)
1274{
1275 struct uart_port *port = platform_get_drvdata(pdev);
1276 struct stm32_port *stm32_port = to_stm32_port(port);
1277 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1278 int err;
1279
1280 pm_runtime_get_sync(&pdev->dev);
1281
1282 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1283
1284 if (stm32_port->rx_ch)
1285 dma_release_channel(stm32_port->rx_ch);
1286
1287 if (stm32_port->rx_dma_buf)
1288 dma_free_coherent(&pdev->dev,
1289 RX_BUF_L, stm32_port->rx_buf,
1290 stm32_port->rx_dma_buf);
1291
1292 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1293
1294 if (stm32_port->tx_ch)
1295 dma_release_channel(stm32_port->tx_ch);
1296
1297 if (stm32_port->tx_dma_buf)
1298 dma_free_coherent(&pdev->dev,
1299 TX_BUF_L, stm32_port->tx_buf,
1300 stm32_port->tx_dma_buf);
1301
1302 if (stm32_port->wakeirq > 0) {
1303 dev_pm_clear_wake_irq(&pdev->dev);
1304 device_init_wakeup(&pdev->dev, false);
1305 }
1306
1307 clk_disable_unprepare(stm32_port->clk);
1308
1309 err = uart_remove_one_port(&stm32_usart_driver, port);
1310
1311 pm_runtime_disable(&pdev->dev);
1312 pm_runtime_put_noidle(&pdev->dev);
1313
1314 return err;
1315}
1316
1317
1318#ifdef CONFIG_SERIAL_STM32_CONSOLE
1319static void stm32_console_putchar(struct uart_port *port, int ch)
1320{
1321 struct stm32_port *stm32_port = to_stm32_port(port);
1322 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1323
1324 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1325 cpu_relax();
1326
1327 writel_relaxed(ch, port->membase + ofs->tdr);
1328}
1329
1330static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1331{
1332 struct uart_port *port = &stm32_ports[co->index].port;
1333 struct stm32_port *stm32_port = to_stm32_port(port);
1334 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1335 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1336 unsigned long flags;
1337 u32 old_cr1, new_cr1;
1338 int locked = 1;
1339
1340 local_irq_save(flags);
1341 if (port->sysrq)
1342 locked = 0;
1343 else if (oops_in_progress)
1344 locked = spin_trylock(&port->lock);
1345 else
1346 spin_lock(&port->lock);
1347
1348
1349 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1350 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1351 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1352 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1353
1354 uart_console_write(port, s, cnt, stm32_console_putchar);
1355
1356
1357 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1358
1359 if (locked)
1360 spin_unlock(&port->lock);
1361 local_irq_restore(flags);
1362}
1363
1364static int stm32_console_setup(struct console *co, char *options)
1365{
1366 struct stm32_port *stm32port;
1367 int baud = 9600;
1368 int bits = 8;
1369 int parity = 'n';
1370 int flow = 'n';
1371
1372 if (co->index >= STM32_MAX_PORTS)
1373 return -ENODEV;
1374
1375 stm32port = &stm32_ports[co->index];
1376
1377
1378
1379
1380
1381
1382
1383 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1384 return -ENXIO;
1385
1386 if (options)
1387 uart_parse_options(options, &baud, &parity, &bits, &flow);
1388
1389 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1390}
1391
1392static struct console stm32_console = {
1393 .name = STM32_SERIAL_NAME,
1394 .device = uart_console_device,
1395 .write = stm32_console_write,
1396 .setup = stm32_console_setup,
1397 .flags = CON_PRINTBUFFER,
1398 .index = -1,
1399 .data = &stm32_usart_driver,
1400};
1401
1402#define STM32_SERIAL_CONSOLE (&stm32_console)
1403
1404#else
1405#define STM32_SERIAL_CONSOLE NULL
1406#endif
1407
1408static struct uart_driver stm32_usart_driver = {
1409 .driver_name = DRIVER_NAME,
1410 .dev_name = STM32_SERIAL_NAME,
1411 .major = 0,
1412 .minor = 0,
1413 .nr = STM32_MAX_PORTS,
1414 .cons = STM32_SERIAL_CONSOLE,
1415};
1416
1417static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port,
1418 bool enable)
1419{
1420 struct stm32_port *stm32_port = to_stm32_port(port);
1421 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1422 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1423 u32 val;
1424
1425 if (stm32_port->wakeirq <= 0)
1426 return;
1427
1428 if (enable) {
1429 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1430 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1431 val = readl_relaxed(port->membase + ofs->cr3);
1432 val &= ~USART_CR3_WUS_MASK;
1433
1434 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1435 writel_relaxed(val, port->membase + ofs->cr3);
1436 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1437 } else {
1438 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1439 }
1440}
1441
1442static int __maybe_unused stm32_serial_suspend(struct device *dev)
1443{
1444 struct uart_port *port = dev_get_drvdata(dev);
1445
1446 uart_suspend_port(&stm32_usart_driver, port);
1447
1448 if (device_may_wakeup(dev))
1449 stm32_serial_enable_wakeup(port, true);
1450 else
1451 stm32_serial_enable_wakeup(port, false);
1452
1453
1454
1455
1456
1457
1458
1459 if (console_suspend_enabled || !uart_console(port)) {
1460 if (device_may_wakeup(dev))
1461 pinctrl_pm_select_idle_state(dev);
1462 else
1463 pinctrl_pm_select_sleep_state(dev);
1464 }
1465
1466 return 0;
1467}
1468
1469static int __maybe_unused stm32_serial_resume(struct device *dev)
1470{
1471 struct uart_port *port = dev_get_drvdata(dev);
1472
1473 pinctrl_pm_select_default_state(dev);
1474
1475 if (device_may_wakeup(dev))
1476 stm32_serial_enable_wakeup(port, false);
1477
1478 return uart_resume_port(&stm32_usart_driver, port);
1479}
1480
1481static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev)
1482{
1483 struct uart_port *port = dev_get_drvdata(dev);
1484 struct stm32_port *stm32port = container_of(port,
1485 struct stm32_port, port);
1486
1487 clk_disable_unprepare(stm32port->clk);
1488
1489 return 0;
1490}
1491
1492static int __maybe_unused stm32_serial_runtime_resume(struct device *dev)
1493{
1494 struct uart_port *port = dev_get_drvdata(dev);
1495 struct stm32_port *stm32port = container_of(port,
1496 struct stm32_port, port);
1497
1498 return clk_prepare_enable(stm32port->clk);
1499}
1500
1501static const struct dev_pm_ops stm32_serial_pm_ops = {
1502 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend,
1503 stm32_serial_runtime_resume, NULL)
1504 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1505};
1506
1507static struct platform_driver stm32_serial_driver = {
1508 .probe = stm32_serial_probe,
1509 .remove = stm32_serial_remove,
1510 .driver = {
1511 .name = DRIVER_NAME,
1512 .pm = &stm32_serial_pm_ops,
1513 .of_match_table = of_match_ptr(stm32_match),
1514 },
1515};
1516
1517static int __init usart_init(void)
1518{
1519 static char banner[] __initdata = "STM32 USART driver initialized";
1520 int ret;
1521
1522 pr_info("%s\n", banner);
1523
1524 ret = uart_register_driver(&stm32_usart_driver);
1525 if (ret)
1526 return ret;
1527
1528 ret = platform_driver_register(&stm32_serial_driver);
1529 if (ret)
1530 uart_unregister_driver(&stm32_usart_driver);
1531
1532 return ret;
1533}
1534
1535static void __exit usart_exit(void)
1536{
1537 platform_driver_unregister(&stm32_serial_driver);
1538 uart_unregister_driver(&stm32_usart_driver);
1539}
1540
1541module_init(usart_init);
1542module_exit(usart_exit);
1543
1544MODULE_ALIAS("platform:" DRIVER_NAME);
1545MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1546MODULE_LICENSE("GPL v2");
1547
