LXR linux/drivers/watchdog/stm32

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for STM32 Independent Watchdog
   4 *
   5 * Copyright (C) STMicroelectronics 2017
   6 * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   7 *
   8 * This driver is based on tegra_wdt.c
   9 *
  10 */
  11
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/interrupt.h>
  15#include <linux/io.h>
  16#include <linux/iopoll.h>
  17#include <linux/kernel.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/of_device.h>
  21#include <linux/platform_device.h>
  22#include <linux/watchdog.h>
  23
  24/* IWDG registers */
  25#define IWDG_KR         0x00 /* Key register */
  26#define IWDG_PR         0x04 /* Prescaler Register */
  27#define IWDG_RLR        0x08 /* ReLoad Register */
  28#define IWDG_SR         0x0C /* Status Register */
  29#define IWDG_WINR       0x10 /* Windows Register */
  30
  31/* IWDG_KR register bit mask */
  32#define KR_KEY_RELOAD   0xAAAA /* reload counter enable */
  33#define KR_KEY_ENABLE   0xCCCC /* peripheral enable */
  34#define KR_KEY_EWA      0x5555 /* write access enable */
  35#define KR_KEY_DWA      0x0000 /* write access disable */
  36
  37/* IWDG_PR register */
  38#define PR_SHIFT        2
  39#define PR_MIN          BIT(PR_SHIFT)
  40
  41/* IWDG_RLR register values */
  42#define RLR_MIN         0x2             /* min value recommended */
  43#define RLR_MAX         GENMASK(11, 0)  /* max value of reload register */
  44
  45/* IWDG_SR register bit mask */
  46#define SR_PVU  BIT(0) /* Watchdog prescaler value update */
  47#define SR_RVU  BIT(1) /* Watchdog counter reload value update */
  48
  49/* set timeout to 100000 us */
  50#define TIMEOUT_US      100000
  51#define SLEEP_US        1000
  52
  53struct stm32_iwdg_data {
  54        bool has_pclk;
  55        u32 max_prescaler;
  56};
  57
  58static const struct stm32_iwdg_data stm32_iwdg_data = {
  59        .has_pclk = false,
  60        .max_prescaler = 256,
  61};
  62
  63static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
  64        .has_pclk = true,
  65        .max_prescaler = 1024,
  66};
  67
  68struct stm32_iwdg {
  69        struct watchdog_device  wdd;
  70        const struct stm32_iwdg_data *data;
  71        void __iomem            *regs;
  72        struct clk              *clk_lsi;
  73        struct clk              *clk_pclk;
  74        unsigned int            rate;
  75};
  76
  77static inline u32 reg_read(void __iomem *base, u32 reg)
  78{
  79        return readl_relaxed(base + reg);
  80}
  81
  82static inline void reg_write(void __iomem *base, u32 reg, u32 val)
  83{
  84        writel_relaxed(val, base + reg);
  85}
  86
  87static int stm32_iwdg_start(struct watchdog_device *wdd)
  88{
  89        struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
  90        u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
  91        int ret;
  92
  93        dev_dbg(wdd->parent, "%s\n", __func__);
  94
  95        tout = clamp_t(unsigned int, wdd->timeout,
  96                       wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
  97
  98        presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
  99
 100        /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
 101        presc = roundup_pow_of_two(presc);
 102        iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
 103        iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
 104
 105        /* enable write access */
 106        reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
 107
 108        /* set prescaler & reload registers */
 109        reg_write(wdt->regs, IWDG_PR, iwdg_pr);
 110        reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
 111        reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
 112
 113        /* wait for the registers to be updated (max 100ms) */
 114        ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
 115                                         !(iwdg_sr & (SR_PVU | SR_RVU)),
 116                                         SLEEP_US, TIMEOUT_US);
 117        if (ret) {
 118                dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
 119                return ret;
 120        }
 121
 122        /* reload watchdog */
 123        reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
 124
 125        return 0;
 126}
 127
 128static int stm32_iwdg_ping(struct watchdog_device *wdd)
 129{
 130        struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
 131
 132        dev_dbg(wdd->parent, "%s\n", __func__);
 133
 134        /* reload watchdog */
 135        reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
 136
 137        return 0;
 138}
 139
 140static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
 141                                  unsigned int timeout)
 142{
 143        dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
 144
 145        wdd->timeout = timeout;
 146
 147        if (watchdog_active(wdd))
 148                return stm32_iwdg_start(wdd);
 149
 150        return 0;
 151}
 152
 153static void stm32_clk_disable_unprepare(void *data)
 154{
 155        clk_disable_unprepare(data);
 156}
 157
 158static int stm32_iwdg_clk_init(struct platform_device *pdev,
 159                               struct stm32_iwdg *wdt)
 160{
 161        struct device *dev = &pdev->dev;
 162        u32 ret;
 163
 164        wdt->clk_lsi = devm_clk_get(dev, "lsi");
 165        if (IS_ERR(wdt->clk_lsi)) {
 166                dev_err(dev, "Unable to get lsi clock\n");
 167                return PTR_ERR(wdt->clk_lsi);
 168        }
 169
 170        /* optional peripheral clock */
 171        if (wdt->data->has_pclk) {
 172                wdt->clk_pclk = devm_clk_get(dev, "pclk");
 173                if (IS_ERR(wdt->clk_pclk)) {
 174                        dev_err(dev, "Unable to get pclk clock\n");
 175                        return PTR_ERR(wdt->clk_pclk);
 176                }
 177
 178                ret = clk_prepare_enable(wdt->clk_pclk);
 179                if (ret) {
 180                        dev_err(dev, "Unable to prepare pclk clock\n");
 181                        return ret;
 182                }
 183                ret = devm_add_action_or_reset(dev,
 184                                               stm32_clk_disable_unprepare,
 185                                               wdt->clk_pclk);
 186                if (ret)
 187                        return ret;
 188        }
 189
 190        ret = clk_prepare_enable(wdt->clk_lsi);
 191        if (ret) {
 192                dev_err(dev, "Unable to prepare lsi clock\n");
 193                return ret;
 194        }
 195        ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
 196                                       wdt->clk_lsi);
 197        if (ret)
 198                return ret;
 199
 200        wdt->rate = clk_get_rate(wdt->clk_lsi);
 201
 202        return 0;
 203}
 204
 205static const struct watchdog_info stm32_iwdg_info = {
 206        .options        = WDIOF_SETTIMEOUT |
 207                          WDIOF_MAGICCLOSE |
 208                          WDIOF_KEEPALIVEPING,
 209        .identity       = "STM32 Independent Watchdog",
 210};
 211
 212static const struct watchdog_ops stm32_iwdg_ops = {
 213        .owner          = THIS_MODULE,
 214        .start          = stm32_iwdg_start,
 215        .ping           = stm32_iwdg_ping,
 216        .set_timeout    = stm32_iwdg_set_timeout,
 217};
 218
 219static const struct of_device_id stm32_iwdg_of_match[] = {
 220        { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
 221        { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
 222        { /* end node */ }
 223};
 224MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
 225
 226static int stm32_iwdg_probe(struct platform_device *pdev)
 227{
 228        struct device *dev = &pdev->dev;
 229        struct watchdog_device *wdd;
 230        struct stm32_iwdg *wdt;
 231        int ret;
 232
 233        wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 234        if (!wdt)
 235                return -ENOMEM;
 236
 237        wdt->data = of_device_get_match_data(&pdev->dev);
 238        if (!wdt->data)
 239                return -ENODEV;
 240
 241        /* This is the timer base. */
 242        wdt->regs = devm_platform_ioremap_resource(pdev, 0);
 243        if (IS_ERR(wdt->regs)) {
 244                dev_err(dev, "Could not get resource\n");
 245                return PTR_ERR(wdt->regs);
 246        }
 247
 248        ret = stm32_iwdg_clk_init(pdev, wdt);
 249        if (ret)
 250                return ret;
 251
 252        /* Initialize struct watchdog_device. */
 253        wdd = &wdt->wdd;
 254        wdd->parent = dev;
 255        wdd->info = &stm32_iwdg_info;
 256        wdd->ops = &stm32_iwdg_ops;
 257        wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
 258        wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
 259                                    1000) / wdt->rate;
 260
 261        watchdog_set_drvdata(wdd, wdt);
 262        watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
 263        watchdog_init_timeout(wdd, 0, dev);
 264
 265        /*
 266         * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
 267         * (Means U-Boot/bootloaders leaves the watchdog running)
 268         * When we get here we should make a decision to prevent
 269         * any side effects before user space daemon will take care of it.
 270         * The best option, taking into consideration that there is no
 271         * way to read values back from hardware, is to enforce watchdog
 272         * being run with deterministic values.
 273         */
 274        if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
 275                ret = stm32_iwdg_start(wdd);
 276                if (ret)
 277                        return ret;
 278
 279                /* Make sure the watchdog is serviced */
 280                set_bit(WDOG_HW_RUNNING, &wdd->status);
 281        }
 282
 283        ret = devm_watchdog_register_device(dev, wdd);
 284        if (ret)
 285                return ret;
 286
 287        platform_set_drvdata(pdev, wdt);
 288
 289        return 0;
 290}
 291
 292static struct platform_driver stm32_iwdg_driver = {
 293        .probe          = stm32_iwdg_probe,
 294        .driver = {
 295                .name   = "iwdg",
 296                .of_match_table = of_match_ptr(stm32_iwdg_of_match),
 297        },
 298};
 299module_platform_driver(stm32_iwdg_driver);
 300
 301MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
 302MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
 303MODULE_LICENSE("GPL v2");
 304