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9#ifndef __TISCI_PROTOCOL_H
10#define __TISCI_PROTOCOL_H
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21struct ti_sci_version_info {
22 u8 abi_major;
23 u8 abi_minor;
24 u16 firmware_revision;
25 char firmware_description[32];
26};
27
28struct ti_sci_handle;
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36struct ti_sci_core_ops {
37 int (*reboot_device)(const struct ti_sci_handle *handle);
38};
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98struct ti_sci_dev_ops {
99 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
100 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
101 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
102 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
103 u32 id);
104 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
105 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
106 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
107 u32 id, u32 *count);
108 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
109 bool *requested_state);
110 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
111 bool *req_state, bool *current_state);
112 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
113 bool *req_state, bool *current_state);
114 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
115 bool *current_state);
116 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
117 u32 reset_state);
118 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
119 u32 *reset_state);
120};
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171struct ti_sci_clk_ops {
172 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
173 bool needs_ssc, bool can_change_freq,
174 bool enable_input_term);
175 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
176 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
177 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
178 bool *req_state);
179 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
180 bool *req_state, bool *current_state);
181 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
182 bool *req_state, bool *current_state);
183 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
184 u32 parent_id);
185 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
186 u32 *parent_id);
187 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
188 u32 cid, u32 *num_parents);
189 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
190 u32 cid, u64 min_freq, u64 target_freq,
191 u64 max_freq, u64 *match_freq);
192 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
193 u64 min_freq, u64 target_freq, u64 max_freq);
194 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
195 u64 *current_freq);
196};
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215struct ti_sci_rm_core_ops {
216 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
217 u8 subtype, u16 *range_start, u16 *range_num);
218 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
219 u32 dev_id, u8 subtype, u8 s_host,
220 u16 *range_start, u16 *range_num);
221};
222
223#define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
224#define TI_SCI_RESASG_SUBTYPE_IA_VINT 0xa
225#define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
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237struct ti_sci_rm_irq_ops {
238 int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
239 u16 src_index, u16 dst_id, u16 dst_host_irq);
240 int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
241 u16 src_index, u16 ia_id, u16 vint,
242 u16 global_event, u8 vint_status_bit);
243 int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
244 u16 src_index, u16 dst_id, u16 dst_host_irq);
245 int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
246 u16 src_index, u16 ia_id, u16 vint,
247 u16 global_event, u8 vint_status_bit);
248};
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250
251#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
252
253#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
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255#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
256
257#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
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259#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
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261#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
262
263#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
264 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
265 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
266 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
267 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
268 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
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276struct ti_sci_rm_ringacc_ops {
277 int (*config)(const struct ti_sci_handle *handle,
278 u32 valid_params, u16 nav_id, u16 index,
279 u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
280 u8 size, u8 order_id
281 );
282 int (*get_config)(const struct ti_sci_handle *handle,
283 u32 nav_id, u32 index, u8 *mode,
284 u32 *addr_lo, u32 *addr_hi, u32 *count,
285 u8 *size, u8 *order_id);
286};
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301struct ti_sci_rm_psil_ops {
302 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
303 u32 src_thread, u32 dst_thread);
304 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
305 u32 src_thread, u32 dst_thread);
306};
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309#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
310#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3
311#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
312#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
313#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
314#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
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316#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
317#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
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319#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
320#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
321#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
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324#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
325#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
326#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
327#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
328#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
329#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
330#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
331#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
332#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
333#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
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341struct ti_sci_msg_rm_udmap_tx_ch_cfg {
342 u32 valid_params;
343#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
344#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
345#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
346#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
347#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
348 u16 nav_id;
349 u16 index;
350 u8 tx_pause_on_err;
351 u8 tx_filt_einfo;
352 u8 tx_filt_pswords;
353 u8 tx_atype;
354 u8 tx_chan_type;
355 u8 tx_supr_tdpkt;
356 u16 tx_fetch_size;
357 u8 tx_credit_count;
358 u16 txcq_qnum;
359 u8 tx_priority;
360 u8 tx_qos;
361 u8 tx_orderid;
362 u16 fdepth;
363 u8 tx_sched_priority;
364 u8 tx_burst_size;
365};
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373struct ti_sci_msg_rm_udmap_rx_ch_cfg {
374 u32 valid_params;
375#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
376#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
377#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
378#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
379 u16 nav_id;
380 u16 index;
381 u16 rx_fetch_size;
382 u16 rxcq_qnum;
383 u8 rx_priority;
384 u8 rx_qos;
385 u8 rx_orderid;
386 u8 rx_sched_priority;
387 u16 flowid_start;
388 u16 flowid_cnt;
389 u8 rx_pause_on_err;
390 u8 rx_atype;
391 u8 rx_chan_type;
392 u8 rx_ignore_short;
393 u8 rx_ignore_long;
394 u8 rx_burst_size;
395};
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403struct ti_sci_msg_rm_udmap_flow_cfg {
404 u32 valid_params;
405#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
406#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
407#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
408#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
409#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
410#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
411#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
412#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
413#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
414#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
415#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
416#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
417#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
418#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
419#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
420#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
421#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
422#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
423#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
424 u16 nav_id;
425 u16 flow_index;
426 u8 rx_einfo_present;
427 u8 rx_psinfo_present;
428 u8 rx_error_handling;
429 u8 rx_desc_type;
430 u16 rx_sop_offset;
431 u16 rx_dest_qnum;
432 u8 rx_src_tag_hi;
433 u8 rx_src_tag_lo;
434 u8 rx_dest_tag_hi;
435 u8 rx_dest_tag_lo;
436 u8 rx_src_tag_hi_sel;
437 u8 rx_src_tag_lo_sel;
438 u8 rx_dest_tag_hi_sel;
439 u8 rx_dest_tag_lo_sel;
440 u16 rx_fdq0_sz0_qnum;
441 u16 rx_fdq1_qnum;
442 u16 rx_fdq2_qnum;
443 u16 rx_fdq3_qnum;
444 u8 rx_ps_location;
445};
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453struct ti_sci_rm_udmap_ops {
454 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
455 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
456 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
457 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
458 int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
459 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
460};
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478struct ti_sci_proc_ops {
479 int (*request)(const struct ti_sci_handle *handle, u8 pid);
480 int (*release)(const struct ti_sci_handle *handle, u8 pid);
481 int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
482 int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
483 u64 boot_vector, u32 cfg_set, u32 cfg_clr);
484 int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
485 u32 ctrl_set, u32 ctrl_clr);
486 int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
487 u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
488 u32 *status_flags);
489};
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499struct ti_sci_ops {
500 struct ti_sci_core_ops core_ops;
501 struct ti_sci_dev_ops dev_ops;
502 struct ti_sci_clk_ops clk_ops;
503 struct ti_sci_rm_core_ops rm_core_ops;
504 struct ti_sci_rm_irq_ops rm_irq_ops;
505 struct ti_sci_rm_ringacc_ops rm_ring_ops;
506 struct ti_sci_rm_psil_ops rm_psil_ops;
507 struct ti_sci_rm_udmap_ops rm_udmap_ops;
508 struct ti_sci_proc_ops proc_ops;
509};
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516struct ti_sci_handle {
517 struct ti_sci_version_info version;
518 struct ti_sci_ops ops;
519};
520
521#define TI_SCI_RESOURCE_NULL 0xffff
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529struct ti_sci_resource_desc {
530 u16 start;
531 u16 num;
532 unsigned long *res_map;
533};
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542struct ti_sci_resource {
543 u16 sets;
544 raw_spinlock_t lock;
545 struct ti_sci_resource_desc *desc;
546};
547
548#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
549const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
550int ti_sci_put_handle(const struct ti_sci_handle *handle);
551const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
552const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
553 const char *property);
554const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
555 const char *property);
556u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
557void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
558u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
559struct ti_sci_resource *
560devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
561 struct device *dev, u32 dev_id, char *of_prop);
562struct ti_sci_resource *
563devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
564 u32 dev_id, u32 sub_type);
565
566#else
567
568static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
569{
570 return ERR_PTR(-EINVAL);
571}
572
573static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
574{
575 return -EINVAL;
576}
577
578static inline
579const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
580{
581 return ERR_PTR(-EINVAL);
582}
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584static inline
585const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
586 const char *property)
587{
588 return ERR_PTR(-EINVAL);
589}
590
591static inline
592const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
593 const char *property)
594{
595 return ERR_PTR(-EINVAL);
596}
597
598static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
599{
600 return TI_SCI_RESOURCE_NULL;
601}
602
603static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
604{
605}
606
607static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
608{
609 return 0;
610}
611
612static inline struct ti_sci_resource *
613devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
614 struct device *dev, u32 dev_id, char *of_prop)
615{
616 return ERR_PTR(-EINVAL);
617}
618
619static inline struct ti_sci_resource *
620devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
621 u32 dev_id, u32 sub_type);
622{
623 return ERR_PTR(-EINVAL);
624}
625#endif
626
627#endif
628