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12#include <linux/clk/tegra.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/jiffies.h>
19#include <linux/smp.h>
20
21#include <soc/tegra/flowctrl.h>
22#include <soc/tegra/fuse.h>
23#include <soc/tegra/pmc.h>
24
25#include <asm/cacheflush.h>
26#include <asm/mach-types.h>
27#include <asm/smp_plat.h>
28#include <asm/smp_scu.h>
29
30#include "common.h"
31#include "iomap.h"
32#include "reset.h"
33
34static cpumask_t tegra_cpu_init_mask;
35
36static void tegra_secondary_init(unsigned int cpu)
37{
38 cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
39}
40
41
42static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
43{
44 cpu = cpu_logical_map(cpu);
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54 tegra_put_cpu_in_reset(cpu);
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62 flowctrl_write_cpu_halt(cpu, 0);
63
64 tegra_enable_cpu_clock(cpu);
65 flowctrl_write_cpu_csr(cpu, 0);
66 tegra_cpu_out_of_reset(cpu);
67 return 0;
68}
69
70static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
71{
72 int ret;
73 unsigned long timeout;
74
75 cpu = cpu_logical_map(cpu);
76 tegra_put_cpu_in_reset(cpu);
77 flowctrl_write_cpu_halt(cpu, 0);
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93 if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
94 timeout = jiffies + msecs_to_jiffies(50);
95 do {
96 if (tegra_pmc_cpu_is_powered(cpu))
97 goto remove_clamps;
98 udelay(10);
99 } while (time_before(jiffies, timeout));
100 }
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108 ret = tegra_pmc_cpu_power_on(cpu);
109 if (ret)
110 return ret;
111
112remove_clamps:
113
114 tegra_enable_cpu_clock(cpu);
115 udelay(10);
116
117
118 ret = tegra_pmc_cpu_remove_clamping(cpu);
119 if (ret)
120 return ret;
121
122 udelay(10);
123
124 flowctrl_write_cpu_csr(cpu, 0);
125 tegra_cpu_out_of_reset(cpu);
126 return 0;
127}
128
129static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
130{
131 int ret = 0;
132
133 cpu = cpu_logical_map(cpu);
134
135 if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
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142 flowctrl_write_cpu_csr(cpu, 1);
143 flowctrl_write_cpu_halt(cpu,
144 FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
145 } else {
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152 ret = tegra_pmc_cpu_power_on(cpu);
153 }
154
155 return ret;
156}
157
158static int tegra_boot_secondary(unsigned int cpu,
159 struct task_struct *idle)
160{
161 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20)
162 return tegra20_boot_secondary(cpu, idle);
163 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30)
164 return tegra30_boot_secondary(cpu, idle);
165 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114)
166 return tegra114_boot_secondary(cpu, idle);
167 if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124)
168 return tegra114_boot_secondary(cpu, idle);
169
170 return -EINVAL;
171}
172
173static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
174{
175
176 cpumask_set_cpu(0, &tegra_cpu_init_mask);
177
178 if (scu_a9_has_base())
179 scu_enable(IO_ADDRESS(scu_a9_get_base()));
180}
181
182const struct smp_operations tegra_smp_ops __initconst = {
183 .smp_prepare_cpus = tegra_smp_prepare_cpus,
184 .smp_secondary_init = tegra_secondary_init,
185 .smp_boot_secondary = tegra_boot_secondary,
186#ifdef CONFIG_HOTPLUG_CPU
187 .cpu_kill = tegra_cpu_kill,
188 .cpu_die = tegra_cpu_die,
189#endif
190};
191