LXR linux/arch/s390/include/asm/processor.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 *  S390 version
   4 *    Copyright IBM Corp. 1999
   5 *    Author(s): Hartmut Penner (hp@de.ibm.com),
   6 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   7 *
   8 *  Derived from "include/asm-i386/processor.h"
   9 *    Copyright (C) 1994, Linus Torvalds
  10 */
  11
  12#ifndef __ASM_S390_PROCESSOR_H
  13#define __ASM_S390_PROCESSOR_H
  14
  15#include <linux/bits.h>
  16
  17#define CIF_NOHZ_DELAY          2       /* delay HZ disable for a tick */
  18#define CIF_FPU                 3       /* restore FPU registers */
  19#define CIF_ENABLED_WAIT        5       /* in enabled wait state */
  20#define CIF_MCCK_GUEST          6       /* machine check happening in guest */
  21#define CIF_DEDICATED_CPU       7       /* this CPU is dedicated */
  22
  23#define _CIF_NOHZ_DELAY         BIT(CIF_NOHZ_DELAY)
  24#define _CIF_FPU                BIT(CIF_FPU)
  25#define _CIF_ENABLED_WAIT       BIT(CIF_ENABLED_WAIT)
  26#define _CIF_MCCK_GUEST         BIT(CIF_MCCK_GUEST)
  27#define _CIF_DEDICATED_CPU      BIT(CIF_DEDICATED_CPU)
  28
  29#define RESTART_FLAG_CTLREGS    _AC(1 << 0, U)
  30
  31#ifndef __ASSEMBLY__
  32
  33#include <linux/cpumask.h>
  34#include <linux/linkage.h>
  35#include <linux/irqflags.h>
  36#include <asm/cpu.h>
  37#include <asm/page.h>
  38#include <asm/ptrace.h>
  39#include <asm/setup.h>
  40#include <asm/runtime_instr.h>
  41#include <asm/fpu/types.h>
  42#include <asm/fpu/internal.h>
  43#include <asm/irqflags.h>
  44
  45typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
  46
  47static inline void set_cpu_flag(int flag)
  48{
  49        S390_lowcore.cpu_flags |= (1UL << flag);
  50}
  51
  52static inline void clear_cpu_flag(int flag)
  53{
  54        S390_lowcore.cpu_flags &= ~(1UL << flag);
  55}
  56
  57static inline int test_cpu_flag(int flag)
  58{
  59        return !!(S390_lowcore.cpu_flags & (1UL << flag));
  60}
  61
  62/*
  63 * Test CIF flag of another CPU. The caller needs to ensure that
  64 * CPU hotplug can not happen, e.g. by disabling preemption.
  65 */
  66static inline int test_cpu_flag_of(int flag, int cpu)
  67{
  68        struct lowcore *lc = lowcore_ptr[cpu];
  69        return !!(lc->cpu_flags & (1UL << flag));
  70}
  71
  72#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
  73
  74static inline void get_cpu_id(struct cpuid *ptr)
  75{
  76        asm volatile("stidp %0" : "=Q" (*ptr));
  77}
  78
  79void s390_adjust_jiffies(void);
  80void s390_update_cpu_mhz(void);
  81void cpu_detect_mhz_feature(void);
  82
  83extern const struct seq_operations cpuinfo_op;
  84extern void execve_tail(void);
  85extern void __bpon(void);
  86
  87/*
  88 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  89 */
  90
  91#define TASK_SIZE_OF(tsk)       (test_tsk_thread_flag(tsk, TIF_31BIT) ? \
  92                                        _REGION3_SIZE : TASK_SIZE_MAX)
  93#define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  94                                        (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
  95#define TASK_SIZE               TASK_SIZE_OF(current)
  96#define TASK_SIZE_MAX           (-PAGE_SIZE)
  97
  98#define STACK_TOP               (test_thread_flag(TIF_31BIT) ? \
  99                                        _REGION3_SIZE : _REGION2_SIZE)
 100#define STACK_TOP_MAX           _REGION2_SIZE
 101
 102#define HAVE_ARCH_PICK_MMAP_LAYOUT
 103
 104/*
 105 * Thread structure
 106 */
 107struct thread_struct {
 108        unsigned int  acrs[NUM_ACRS];
 109        unsigned long ksp;                      /* kernel stack pointer */
 110        unsigned long user_timer;               /* task cputime in user space */
 111        unsigned long guest_timer;              /* task cputime in kvm guest */
 112        unsigned long system_timer;             /* task cputime in kernel space */
 113        unsigned long hardirq_timer;            /* task cputime in hardirq context */
 114        unsigned long softirq_timer;            /* task cputime in softirq context */
 115        const sys_call_ptr_t *sys_call_table;   /* system call table address */
 116        unsigned long gmap_addr;                /* address of last gmap fault. */
 117        unsigned int gmap_write_flag;           /* gmap fault write indication */
 118        unsigned int gmap_int_code;             /* int code of last gmap fault */
 119        unsigned int gmap_pfault;               /* signal of a pending guest pfault */
 120
 121        /* Per-thread information related to debugging */
 122        struct per_regs per_user;               /* User specified PER registers */
 123        struct per_event per_event;             /* Cause of the last PER trap */
 124        unsigned long per_flags;                /* Flags to control debug behavior */
 125        unsigned int system_call;               /* system call number in signal */
 126        unsigned long last_break;               /* last breaking-event-address. */
 127        /* pfault_wait is used to block the process on a pfault event */
 128        unsigned long pfault_wait;
 129        struct list_head list;
 130        /* cpu runtime instrumentation */
 131        struct runtime_instr_cb *ri_cb;
 132        struct gs_cb *gs_cb;                    /* Current guarded storage cb */
 133        struct gs_cb *gs_bc_cb;                 /* Broadcast guarded storage cb */
 134        struct pgm_tdb trap_tdb;                /* Transaction abort diagnose block */
 135        /*
 136         * Warning: 'fpu' is dynamically-sized. It *MUST* be at
 137         * the end.
 138         */
 139        struct fpu fpu;                 /* FP and VX register save area */
 140};
 141
 142/* Flag to disable transactions. */
 143#define PER_FLAG_NO_TE                  1UL
 144/* Flag to enable random transaction aborts. */
 145#define PER_FLAG_TE_ABORT_RAND          2UL
 146/* Flag to specify random transaction abort mode:
 147 * - abort each transaction at a random instruction before TEND if set.
 148 * - abort random transactions at a random instruction if cleared.
 149 */
 150#define PER_FLAG_TE_ABORT_RAND_TEND     4UL
 151
 152typedef struct thread_struct thread_struct;
 153
 154#define ARCH_MIN_TASKALIGN      8
 155
 156#define INIT_THREAD {                                                   \
 157        .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 158        .fpu.regs = (void *) init_task.thread.fpu.fprs,                 \
 159        .last_break = 1,                                                \
 160}
 161
 162/*
 163 * Do necessary setup to start up a new thread.
 164 */
 165#define start_thread(regs, new_psw, new_stackp) do {                    \
 166        regs->psw.mask  = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;    \
 167        regs->psw.addr  = new_psw;                                      \
 168        regs->gprs[15]  = new_stackp;                                   \
 169        execve_tail();                                                  \
 170} while (0)
 171
 172#define start_thread31(regs, new_psw, new_stackp) do {                  \
 173        regs->psw.mask  = PSW_USER_BITS | PSW_MASK_BA;                  \
 174        regs->psw.addr  = new_psw;                                      \
 175        regs->gprs[15]  = new_stackp;                                   \
 176        execve_tail();                                                  \
 177} while (0)
 178
 179/* Forward declaration, a strange C thing */
 180struct task_struct;
 181struct mm_struct;
 182struct seq_file;
 183struct pt_regs;
 184
 185void show_registers(struct pt_regs *regs);
 186void show_cacheinfo(struct seq_file *m);
 187
 188/* Free all resources held by a thread. */
 189static inline void release_thread(struct task_struct *tsk) { }
 190
 191/* Free guarded storage control block */
 192void guarded_storage_release(struct task_struct *tsk);
 193void gs_load_bc_cb(struct pt_regs *regs);
 194
 195unsigned long get_wchan(struct task_struct *p);
 196#define task_pt_regs(tsk) ((struct pt_regs *) \
 197        (task_stack_page(tsk) + THREAD_SIZE) - 1)
 198#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 199#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 200
 201/* Has task runtime instrumentation enabled ? */
 202#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
 203
 204static __always_inline unsigned long current_stack_pointer(void)
 205{
 206        unsigned long sp;
 207
 208        asm volatile("la %0,0(15)" : "=a" (sp));
 209        return sp;
 210}
 211
 212static __always_inline unsigned short stap(void)
 213{
 214        unsigned short cpu_address;
 215
 216        asm volatile("stap %0" : "=Q" (cpu_address));
 217        return cpu_address;
 218}
 219
 220#define cpu_relax() barrier()
 221
 222#define ECAG_CACHE_ATTRIBUTE    0
 223#define ECAG_CPU_ATTRIBUTE      1
 224
 225static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
 226{
 227        unsigned long val;
 228
 229        asm volatile(".insn     rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
 230                     : "=d" (val) : "a" (asi << 8 | parm));
 231        return val;
 232}
 233
 234static inline void psw_set_key(unsigned int key)
 235{
 236        asm volatile("spka 0(%0)" : : "d" (key));
 237}
 238
 239/*
 240 * Set PSW to specified value.
 241 */
 242static inline void __load_psw(psw_t psw)
 243{
 244        asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 245}
 246
 247/*
 248 * Set PSW mask to specified value, while leaving the
 249 * PSW addr pointing to the next instruction.
 250 */
 251static __always_inline void __load_psw_mask(unsigned long mask)
 252{
 253        unsigned long addr;
 254        psw_t psw;
 255
 256        psw.mask = mask;
 257
 258        asm volatile(
 259                "       larl    %0,1f\n"
 260                "       stg     %0,%1\n"
 261                "       lpswe   %2\n"
 262                "1:"
 263                : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
 264}
 265
 266/*
 267 * Extract current PSW mask
 268 */
 269static inline unsigned long __extract_psw(void)
 270{
 271        unsigned int reg1, reg2;
 272
 273        asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
 274        return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
 275}
 276
 277static inline void local_mcck_enable(void)
 278{
 279        __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
 280}
 281
 282static inline void local_mcck_disable(void)
 283{
 284        __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
 285}
 286
 287/*
 288 * Rewind PSW instruction address by specified number of bytes.
 289 */
 290static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 291{
 292        unsigned long mask;
 293
 294        mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 295               (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 296                                          (1UL << 24) - 1;
 297        return (psw.addr - ilc) & mask;
 298}
 299
 300/*
 301 * Function to drop a processor into disabled wait state
 302 */
 303static __always_inline void __noreturn disabled_wait(void)
 304{
 305        psw_t psw;
 306
 307        psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 308        psw.addr = _THIS_IP_;
 309        __load_psw(psw);
 310        while (1);
 311}
 312
 313/*
 314 * Basic Program Check Handler.
 315 */
 316extern void s390_base_pgm_handler(void);
 317extern void (*s390_base_pgm_handler_fn)(void);
 318
 319#define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 320
 321extern int memcpy_real(void *, void *, size_t);
 322extern void memcpy_absolute(void *, void *, size_t);
 323
 324#define mem_assign_absolute(dest, val) do {                     \
 325        __typeof__(dest) __tmp = (val);                         \
 326                                                                \
 327        BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 328        memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 329} while (0)
 330
 331extern int s390_isolate_bp(void);
 332extern int s390_isolate_bp_guest(void);
 333
 334static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
 335{
 336        return arch_irqs_disabled_flags(regs->psw.mask);
 337}
 338
 339#endif /* __ASSEMBLY__ */
 340
 341#endif /* __ASM_S390_PROCESSOR_H */
 342