1
2#ifndef _ASM_X86_MCE_H
3#define _ASM_X86_MCE_H
4
5#include <uapi/asm/mce.h>
6
7
8
9
10
11
12#define MCG_BANKCNT_MASK 0xff
13#define MCG_CTL_P BIT_ULL(8)
14#define MCG_EXT_P BIT_ULL(9)
15#define MCG_CMCI_P BIT_ULL(10)
16#define MCG_EXT_CNT_MASK 0xff0000
17#define MCG_EXT_CNT_SHIFT 16
18#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
19#define MCG_SER_P BIT_ULL(24)
20#define MCG_ELOG_P BIT_ULL(26)
21#define MCG_LMCE_P BIT_ULL(27)
22
23
24#define MCG_STATUS_RIPV BIT_ULL(0)
25#define MCG_STATUS_EIPV BIT_ULL(1)
26#define MCG_STATUS_MCIP BIT_ULL(2)
27#define MCG_STATUS_LMCES BIT_ULL(3)
28
29
30#define MCG_EXT_CTL_LMCE_EN BIT_ULL(0)
31
32
33#define MCI_STATUS_VAL BIT_ULL(63)
34#define MCI_STATUS_OVER BIT_ULL(62)
35#define MCI_STATUS_UC BIT_ULL(61)
36#define MCI_STATUS_EN BIT_ULL(60)
37#define MCI_STATUS_MISCV BIT_ULL(59)
38#define MCI_STATUS_ADDRV BIT_ULL(58)
39#define MCI_STATUS_PCC BIT_ULL(57)
40#define MCI_STATUS_S BIT_ULL(56)
41#define MCI_STATUS_AR BIT_ULL(55)
42#define MCI_STATUS_CEC_SHIFT 38
43#define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
44#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
45
46
47#define MCI_STATUS_TCC BIT_ULL(55)
48#define MCI_STATUS_SYNDV BIT_ULL(53)
49#define MCI_STATUS_DEFERRED BIT_ULL(44)
50#define MCI_STATUS_POISON BIT_ULL(43)
51#define MCI_STATUS_SCRUB BIT_ULL(40)
52
53
54
55
56
57
58
59
60#define MCI_CONFIG_MCAX 0x1
61#define MCI_IPID_MCATYPE 0xFFFF0000
62#define MCI_IPID_HWID 0xFFF
63
64
65
66
67
68
69
70
71
72#define MCACOD 0xefff
73
74
75#define MCACOD_SCRUB 0x00C0
76#define MCACOD_SCRUBMSK 0xeff0
77#define MCACOD_L3WB 0x017A
78#define MCACOD_DATA 0x0134
79#define MCACOD_INSTR 0x0150
80
81
82#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
83#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
84#define MCI_MISC_ADDR_SEGOFF 0
85#define MCI_MISC_ADDR_LINEAR 1
86#define MCI_MISC_ADDR_PHYS 2
87#define MCI_MISC_ADDR_MEM 3
88#define MCI_MISC_ADDR_GENERIC 7
89
90
91#define MCI_CTL2_CMCI_EN BIT_ULL(30)
92#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
93
94#define MCJ_CTX_MASK 3
95#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
96#define MCJ_CTX_RANDOM 0
97#define MCJ_CTX_PROCESS 0x1
98#define MCJ_CTX_IRQ 0x2
99#define MCJ_NMI_BROADCAST 0x4
100#define MCJ_EXCEPTION 0x8
101#define MCJ_IRQ_BROADCAST 0x10
102
103#define MCE_OVERFLOW 0
104
105#define MCE_LOG_MIN_LEN 32U
106#define MCE_LOG_SIGNATURE "MACHINECHECK"
107
108
109#define MSR_AMD64_SMCA_MC0_CTL 0xc0002000
110#define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001
111#define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002
112#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
113#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
114#define MSR_AMD64_SMCA_MC0_IPID 0xc0002005
115#define MSR_AMD64_SMCA_MC0_SYND 0xc0002006
116#define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008
117#define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009
118#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
119#define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
120#define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
121#define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
122#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
123#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
124#define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
125#define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
126#define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
127#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
128#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
129
130#define XEC(x, mask) (((x) >> 16) & mask)
131
132
133#define MCE_HANDLED_CEC BIT_ULL(0)
134#define MCE_HANDLED_UC BIT_ULL(1)
135#define MCE_HANDLED_EXTLOG BIT_ULL(2)
136#define MCE_HANDLED_NFIT BIT_ULL(3)
137#define MCE_HANDLED_EDAC BIT_ULL(4)
138#define MCE_HANDLED_MCELOG BIT_ULL(5)
139
140
141
142
143
144
145
146#define MCE_IN_KERNEL_RECOV BIT_ULL(6)
147
148
149
150
151
152
153
154#define MCE_IN_KERNEL_COPYIN BIT_ULL(7)
155
156
157
158
159
160
161
162struct mce_log_buffer {
163 char signature[12];
164 unsigned len;
165 unsigned next;
166 unsigned flags;
167 unsigned recordlen;
168 struct mce entry[];
169};
170
171
172enum mce_notifier_prios {
173 MCE_PRIO_LOWEST,
174 MCE_PRIO_MCELOG,
175 MCE_PRIO_EDAC,
176 MCE_PRIO_NFIT,
177 MCE_PRIO_EXTLOG,
178 MCE_PRIO_UC,
179 MCE_PRIO_EARLY,
180 MCE_PRIO_CEC,
181 MCE_PRIO_HIGHEST = MCE_PRIO_CEC
182};
183
184struct notifier_block;
185extern void mce_register_decode_chain(struct notifier_block *nb);
186extern void mce_unregister_decode_chain(struct notifier_block *nb);
187
188#include <linux/percpu.h>
189#include <linux/atomic.h>
190
191extern int mce_p5_enabled;
192
193#ifdef CONFIG_ARCH_HAS_COPY_MC
194extern void enable_copy_mc_fragile(void);
195unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
196#else
197static inline void enable_copy_mc_fragile(void)
198{
199}
200#endif
201
202struct cper_ia_proc_ctx;
203
204#ifdef CONFIG_X86_MCE
205int mcheck_init(void);
206void mcheck_cpu_init(struct cpuinfo_x86 *c);
207void mcheck_cpu_clear(struct cpuinfo_x86 *c);
208void mcheck_vendor_init_severity(void);
209int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
210 u64 lapic_id);
211#else
212static inline int mcheck_init(void) { return 0; }
213static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
214static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
215static inline void mcheck_vendor_init_severity(void) {}
216static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
217 u64 lapic_id) { return -EINVAL; }
218#endif
219
220#ifdef CONFIG_X86_ANCIENT_MCE
221void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
222void winchip_mcheck_init(struct cpuinfo_x86 *c);
223static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
224#else
225static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
226static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
227static inline void enable_p5_mce(void) {}
228#endif
229
230void mce_setup(struct mce *m);
231void mce_log(struct mce *m);
232DECLARE_PER_CPU(struct device *, mce_device);
233
234
235#define MAX_NR_BANKS 64
236
237#ifdef CONFIG_X86_MCE_INTEL
238void mce_intel_feature_init(struct cpuinfo_x86 *c);
239void mce_intel_feature_clear(struct cpuinfo_x86 *c);
240void cmci_clear(void);
241void cmci_reenable(void);
242void cmci_rediscover(void);
243void cmci_recheck(void);
244#else
245static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
246static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
247static inline void cmci_clear(void) {}
248static inline void cmci_reenable(void) {}
249static inline void cmci_rediscover(void) {}
250static inline void cmci_recheck(void) {}
251#endif
252
253int mce_available(struct cpuinfo_x86 *c);
254bool mce_is_memory_error(struct mce *m);
255bool mce_is_correctable(struct mce *m);
256int mce_usable_address(struct mce *m);
257
258DECLARE_PER_CPU(unsigned, mce_exception_count);
259DECLARE_PER_CPU(unsigned, mce_poll_count);
260
261typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
262DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
263
264enum mcp_flags {
265 MCP_TIMESTAMP = BIT(0),
266 MCP_UC = BIT(1),
267 MCP_DONTLOG = BIT(2),
268 MCP_QUEUE_LOG = BIT(3),
269};
270bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
271
272int mce_notify_irq(void);
273
274DECLARE_PER_CPU(struct mce, injectm);
275
276
277extern void mce_disable_bank(int bank);
278
279
280
281
282void do_machine_check(struct pt_regs *pt_regs);
283
284
285
286
287extern void (*mce_threshold_vector)(void);
288
289
290extern void (*deferred_error_int_vector)(void);
291
292
293
294
295
296struct cper_sec_mem_err;
297extern void apei_mce_report_mem_error(int corrected,
298 struct cper_sec_mem_err *mem_err);
299
300
301
302
303
304#ifdef CONFIG_X86_MCE_AMD
305
306
307enum smca_bank_types {
308 SMCA_LS = 0,
309 SMCA_LS_V2,
310 SMCA_IF,
311 SMCA_L2_CACHE,
312 SMCA_DE,
313 SMCA_RESERVED,
314 SMCA_EX,
315 SMCA_FP,
316 SMCA_L3_CACHE,
317 SMCA_CS,
318 SMCA_CS_V2,
319 SMCA_PIE,
320 SMCA_UMC,
321 SMCA_UMC_V2,
322 SMCA_PB,
323 SMCA_PSP,
324 SMCA_PSP_V2,
325 SMCA_SMU,
326 SMCA_SMU_V2,
327 SMCA_MP5,
328 SMCA_NBIO,
329 SMCA_PCIE,
330 SMCA_PCIE_V2,
331 SMCA_XGMI_PCS,
332 SMCA_XGMI_PHY,
333 SMCA_WAFL_PHY,
334 N_SMCA_BANK_TYPES
335};
336
337#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
338
339struct smca_hwid {
340 unsigned int bank_type;
341 u32 hwid_mcatype;
342 u8 count;
343};
344
345struct smca_bank {
346 struct smca_hwid *hwid;
347 u32 id;
348 u8 sysfs_id;
349};
350
351extern struct smca_bank smca_banks[MAX_NR_BANKS];
352
353extern const char *smca_get_long_name(enum smca_bank_types t);
354extern bool amd_mce_is_memory_error(struct mce *m);
355
356extern int mce_threshold_create_device(unsigned int cpu);
357extern int mce_threshold_remove_device(unsigned int cpu);
358
359void mce_amd_feature_init(struct cpuinfo_x86 *c);
360int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
361
362#else
363
364static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
365static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
366static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
367static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
368static inline int
369umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
370#endif
371
372static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
373#endif
374