1
2
3
4
5
6
7#include <linux/compat.h>
8#include <linux/cpu.h>
9#include <linux/mman.h>
10#include <linux/pkeys.h>
11#include <linux/seq_file.h>
12#include <linux/proc_fs.h>
13
14#include <asm/fpu/api.h>
15#include <asm/fpu/internal.h>
16#include <asm/fpu/signal.h>
17#include <asm/fpu/regset.h>
18#include <asm/fpu/xstate.h>
19
20#include <asm/tlbflush.h>
21#include <asm/cpufeature.h>
22
23
24
25
26
27
28static const char *xfeature_names[] =
29{
30 "x87 floating point registers" ,
31 "SSE registers" ,
32 "AVX registers" ,
33 "MPX bounds registers" ,
34 "MPX CSR" ,
35 "AVX-512 opmask" ,
36 "AVX-512 Hi256" ,
37 "AVX-512 ZMM_Hi256" ,
38 "Processor Trace (unused)" ,
39 "Protection Keys User registers",
40 "PASID state",
41 "unknown xstate feature" ,
42};
43
44static short xsave_cpuid_features[] __initdata = {
45 X86_FEATURE_FPU,
46 X86_FEATURE_XMM,
47 X86_FEATURE_AVX,
48 X86_FEATURE_MPX,
49 X86_FEATURE_MPX,
50 X86_FEATURE_AVX512F,
51 X86_FEATURE_AVX512F,
52 X86_FEATURE_AVX512F,
53 X86_FEATURE_INTEL_PT,
54 X86_FEATURE_PKU,
55 X86_FEATURE_ENQCMD,
56};
57
58
59
60
61
62u64 xfeatures_mask_all __ro_after_init;
63EXPORT_SYMBOL_GPL(xfeatures_mask_all);
64
65static unsigned int xstate_offsets[XFEATURE_MAX] __ro_after_init =
66 { [ 0 ... XFEATURE_MAX - 1] = -1};
67static unsigned int xstate_sizes[XFEATURE_MAX] __ro_after_init =
68 { [ 0 ... XFEATURE_MAX - 1] = -1};
69static unsigned int xstate_comp_offsets[XFEATURE_MAX] __ro_after_init =
70 { [ 0 ... XFEATURE_MAX - 1] = -1};
71static unsigned int xstate_supervisor_only_offsets[XFEATURE_MAX] __ro_after_init =
72 { [ 0 ... XFEATURE_MAX - 1] = -1};
73
74
75
76
77
78
79unsigned int fpu_user_xstate_size __ro_after_init;
80
81
82
83
84
85
86int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name)
87{
88 u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask_all;
89
90 if (unlikely(feature_name)) {
91 long xfeature_idx, max_idx;
92 u64 xfeatures_print;
93
94
95
96
97
98
99
100 if (xfeatures_missing)
101 xfeatures_print = xfeatures_missing;
102 else
103 xfeatures_print = xfeatures_needed;
104
105 xfeature_idx = fls64(xfeatures_print)-1;
106 max_idx = ARRAY_SIZE(xfeature_names)-1;
107 xfeature_idx = min(xfeature_idx, max_idx);
108
109 *feature_name = xfeature_names[xfeature_idx];
110 }
111
112 if (xfeatures_missing)
113 return 0;
114
115 return 1;
116}
117EXPORT_SYMBOL_GPL(cpu_has_xfeatures);
118
119static bool xfeature_is_supervisor(int xfeature_nr)
120{
121
122
123
124
125
126 u32 eax, ebx, ecx, edx;
127
128 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
129 return ecx & 1;
130}
131
132
133
134
135
136void fpu__init_cpu_xstate(void)
137{
138 if (!boot_cpu_has(X86_FEATURE_XSAVE) || !xfeatures_mask_all)
139 return;
140
141 cr4_set_bits(X86_CR4_OSXSAVE);
142
143
144
145
146
147
148 xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask_uabi());
149
150
151
152
153 if (boot_cpu_has(X86_FEATURE_XSAVES)) {
154 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() |
155 xfeatures_mask_independent());
156 }
157}
158
159static bool xfeature_enabled(enum xfeature xfeature)
160{
161 return xfeatures_mask_all & BIT_ULL(xfeature);
162}
163
164
165
166
167
168static void __init setup_xstate_features(void)
169{
170 u32 eax, ebx, ecx, edx, i;
171
172 unsigned int last_good_offset = offsetof(struct xregs_state,
173 extended_state_area);
174
175
176
177
178
179 xstate_offsets[XFEATURE_FP] = 0;
180 xstate_sizes[XFEATURE_FP] = offsetof(struct fxregs_state,
181 xmm_space);
182
183 xstate_offsets[XFEATURE_SSE] = xstate_sizes[XFEATURE_FP];
184 xstate_sizes[XFEATURE_SSE] = sizeof_field(struct fxregs_state,
185 xmm_space);
186
187 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
188 if (!xfeature_enabled(i))
189 continue;
190
191 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
192
193 xstate_sizes[i] = eax;
194
195
196
197
198
199 if (xfeature_is_supervisor(i))
200 continue;
201
202 xstate_offsets[i] = ebx;
203
204
205
206
207
208
209 WARN_ONCE(last_good_offset > xstate_offsets[i],
210 "x86/fpu: misordered xstate at %d\n", last_good_offset);
211
212 last_good_offset = xstate_offsets[i];
213 }
214}
215
216static void __init print_xstate_feature(u64 xstate_mask)
217{
218 const char *feature_name;
219
220 if (cpu_has_xfeatures(xstate_mask, &feature_name))
221 pr_info("x86/fpu: Supporting XSAVE feature 0x%03Lx: '%s'\n", xstate_mask, feature_name);
222}
223
224
225
226
227static void __init print_xstate_features(void)
228{
229 print_xstate_feature(XFEATURE_MASK_FP);
230 print_xstate_feature(XFEATURE_MASK_SSE);
231 print_xstate_feature(XFEATURE_MASK_YMM);
232 print_xstate_feature(XFEATURE_MASK_BNDREGS);
233 print_xstate_feature(XFEATURE_MASK_BNDCSR);
234 print_xstate_feature(XFEATURE_MASK_OPMASK);
235 print_xstate_feature(XFEATURE_MASK_ZMM_Hi256);
236 print_xstate_feature(XFEATURE_MASK_Hi16_ZMM);
237 print_xstate_feature(XFEATURE_MASK_PKRU);
238 print_xstate_feature(XFEATURE_MASK_PASID);
239}
240
241
242
243
244
245#define CHECK_XFEATURE(nr) do { \
246 WARN_ON(nr < FIRST_EXTENDED_XFEATURE); \
247 WARN_ON(nr >= XFEATURE_MAX); \
248} while (0)
249
250
251
252
253
254static int xfeature_is_aligned(int xfeature_nr)
255{
256 u32 eax, ebx, ecx, edx;
257
258 CHECK_XFEATURE(xfeature_nr);
259
260 if (!xfeature_enabled(xfeature_nr)) {
261 WARN_ONCE(1, "Checking alignment of disabled xfeature %d\n",
262 xfeature_nr);
263 return 0;
264 }
265
266 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
267
268
269
270
271
272 return !!(ecx & 2);
273}
274
275
276
277
278
279
280static void __init setup_xstate_comp_offsets(void)
281{
282 unsigned int next_offset;
283 int i;
284
285
286
287
288
289
290 xstate_comp_offsets[XFEATURE_FP] = 0;
291 xstate_comp_offsets[XFEATURE_SSE] = offsetof(struct fxregs_state,
292 xmm_space);
293
294 if (!boot_cpu_has(X86_FEATURE_XSAVES)) {
295 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
296 if (xfeature_enabled(i))
297 xstate_comp_offsets[i] = xstate_offsets[i];
298 }
299 return;
300 }
301
302 next_offset = FXSAVE_SIZE + XSAVE_HDR_SIZE;
303
304 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
305 if (!xfeature_enabled(i))
306 continue;
307
308 if (xfeature_is_aligned(i))
309 next_offset = ALIGN(next_offset, 64);
310
311 xstate_comp_offsets[i] = next_offset;
312 next_offset += xstate_sizes[i];
313 }
314}
315
316
317
318
319
320
321
322
323
324static void __init setup_supervisor_only_offsets(void)
325{
326 unsigned int next_offset;
327 int i;
328
329 next_offset = FXSAVE_SIZE + XSAVE_HDR_SIZE;
330
331 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
332 if (!xfeature_enabled(i) || !xfeature_is_supervisor(i))
333 continue;
334
335 if (xfeature_is_aligned(i))
336 next_offset = ALIGN(next_offset, 64);
337
338 xstate_supervisor_only_offsets[i] = next_offset;
339 next_offset += xstate_sizes[i];
340 }
341}
342
343
344
345
346static void __init print_xstate_offset_size(void)
347{
348 int i;
349
350 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
351 if (!xfeature_enabled(i))
352 continue;
353 pr_info("x86/fpu: xstate_offset[%d]: %4d, xstate_sizes[%d]: %4d\n",
354 i, xstate_comp_offsets[i], i, xstate_sizes[i]);
355 }
356}
357
358
359
360
361
362
363
364
365#define XFEATURES_INIT_FPSTATE_HANDLED \
366 (XFEATURE_MASK_FP | \
367 XFEATURE_MASK_SSE | \
368 XFEATURE_MASK_YMM | \
369 XFEATURE_MASK_OPMASK | \
370 XFEATURE_MASK_ZMM_Hi256 | \
371 XFEATURE_MASK_Hi16_ZMM | \
372 XFEATURE_MASK_PKRU | \
373 XFEATURE_MASK_BNDREGS | \
374 XFEATURE_MASK_BNDCSR | \
375 XFEATURE_MASK_PASID)
376
377
378
379
380static void __init setup_init_fpu_buf(void)
381{
382 static int on_boot_cpu __initdata = 1;
383
384 BUILD_BUG_ON((XFEATURE_MASK_USER_SUPPORTED |
385 XFEATURE_MASK_SUPERVISOR_SUPPORTED) !=
386 XFEATURES_INIT_FPSTATE_HANDLED);
387
388 WARN_ON_FPU(!on_boot_cpu);
389 on_boot_cpu = 0;
390
391 if (!boot_cpu_has(X86_FEATURE_XSAVE))
392 return;
393
394 setup_xstate_features();
395 print_xstate_features();
396
397 if (boot_cpu_has(X86_FEATURE_XSAVES))
398 init_fpstate.xsave.header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT |
399 xfeatures_mask_all;
400
401
402
403
404 os_xrstor_booting(&init_fpstate.xsave);
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422 fxsave(&init_fpstate.fxsave);
423}
424
425static int xfeature_uncompacted_offset(int xfeature_nr)
426{
427 u32 eax, ebx, ecx, edx;
428
429
430
431
432
433
434 if (XFEATURE_MASK_SUPERVISOR_ALL & BIT_ULL(xfeature_nr)) {
435 WARN_ONCE(1, "No fixed offset for xstate %d\n", xfeature_nr);
436 return -1;
437 }
438
439 CHECK_XFEATURE(xfeature_nr);
440 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
441 return ebx;
442}
443
444int xfeature_size(int xfeature_nr)
445{
446 u32 eax, ebx, ecx, edx;
447
448 CHECK_XFEATURE(xfeature_nr);
449 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
450 return eax;
451}
452
453
454static int validate_user_xstate_header(const struct xstate_header *hdr)
455{
456
457 if (hdr->xfeatures & ~xfeatures_mask_uabi())
458 return -EINVAL;
459
460
461 if (hdr->xcomp_bv)
462 return -EINVAL;
463
464
465
466
467
468 BUILD_BUG_ON(sizeof(hdr->reserved) != 48);
469
470
471 if (memchr_inv(hdr->reserved, 0, sizeof(hdr->reserved)))
472 return -EINVAL;
473
474 return 0;
475}
476
477static void __xstate_dump_leaves(void)
478{
479 int i;
480 u32 eax, ebx, ecx, edx;
481 static int should_dump = 1;
482
483 if (!should_dump)
484 return;
485 should_dump = 0;
486
487
488
489
490 for (i = 0; i < XFEATURE_MAX + 10; i++) {
491 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
492 pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n",
493 XSTATE_CPUID, i, eax, ebx, ecx, edx);
494 }
495}
496
497#define XSTATE_WARN_ON(x) do { \
498 if (WARN_ONCE(x, "XSAVE consistency problem, dumping leaves")) { \
499 __xstate_dump_leaves(); \
500 } \
501} while (0)
502
503#define XCHECK_SZ(sz, nr, nr_macro, __struct) do { \
504 if ((nr == nr_macro) && \
505 WARN_ONCE(sz != sizeof(__struct), \
506 "%s: struct is %zu bytes, cpu state %d bytes\n", \
507 __stringify(nr_macro), sizeof(__struct), sz)) { \
508 __xstate_dump_leaves(); \
509 } \
510} while (0)
511
512
513
514
515
516
517static void check_xstate_against_struct(int nr)
518{
519
520
521
522 int sz = xfeature_size(nr);
523
524
525
526
527 XCHECK_SZ(sz, nr, XFEATURE_YMM, struct ymmh_struct);
528 XCHECK_SZ(sz, nr, XFEATURE_BNDREGS, struct mpx_bndreg_state);
529 XCHECK_SZ(sz, nr, XFEATURE_BNDCSR, struct mpx_bndcsr_state);
530 XCHECK_SZ(sz, nr, XFEATURE_OPMASK, struct avx_512_opmask_state);
531 XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state);
532 XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state);
533 XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state);
534 XCHECK_SZ(sz, nr, XFEATURE_PASID, struct ia32_pasid_state);
535
536
537
538
539
540
541 if ((nr < XFEATURE_YMM) ||
542 (nr >= XFEATURE_MAX) ||
543 (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR) ||
544 ((nr >= XFEATURE_RSRVD_COMP_11) && (nr <= XFEATURE_LBR))) {
545 WARN_ONCE(1, "no structure for xstate: %d\n", nr);
546 XSTATE_WARN_ON(1);
547 }
548}
549
550
551
552
553
554
555
556
557
558
559static void do_extra_xstate_size_checks(void)
560{
561 int paranoid_xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE;
562 int i;
563
564 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
565 if (!xfeature_enabled(i))
566 continue;
567
568 check_xstate_against_struct(i);
569
570
571
572
573 if (!cpu_feature_enabled(X86_FEATURE_XSAVES))
574 XSTATE_WARN_ON(xfeature_is_supervisor(i));
575
576
577 if (xfeature_is_aligned(i))
578 paranoid_xstate_size = ALIGN(paranoid_xstate_size, 64);
579
580
581
582
583
584
585 if (!cpu_feature_enabled(X86_FEATURE_XSAVES))
586 paranoid_xstate_size = xfeature_uncompacted_offset(i);
587
588
589
590
591 paranoid_xstate_size += xfeature_size(i);
592 }
593 XSTATE_WARN_ON(paranoid_xstate_size != fpu_kernel_xstate_size);
594}
595
596
597
598
599
600
601
602
603
604
605static unsigned int __init get_xsaves_size(void)
606{
607 unsigned int eax, ebx, ecx, edx;
608
609
610
611
612
613
614
615
616 cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
617 return ebx;
618}
619
620
621
622
623
624static unsigned int __init get_xsaves_size_no_independent(void)
625{
626 u64 mask = xfeatures_mask_independent();
627 unsigned int size;
628
629 if (!mask)
630 return get_xsaves_size();
631
632
633 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor());
634
635
636
637
638
639 size = get_xsaves_size();
640
641
642 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() | mask);
643
644 return size;
645}
646
647static unsigned int __init get_xsave_size(void)
648{
649 unsigned int eax, ebx, ecx, edx;
650
651
652
653
654
655
656
657 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
658 return ebx;
659}
660
661
662
663
664
665static bool is_supported_xstate_size(unsigned int test_xstate_size)
666{
667 if (test_xstate_size <= sizeof(union fpregs_state))
668 return true;
669
670 pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n",
671 sizeof(union fpregs_state), test_xstate_size);
672 return false;
673}
674
675static int __init init_xstate_size(void)
676{
677
678 unsigned int possible_xstate_size;
679 unsigned int xsave_size;
680
681 xsave_size = get_xsave_size();
682
683 if (boot_cpu_has(X86_FEATURE_XSAVES))
684 possible_xstate_size = get_xsaves_size_no_independent();
685 else
686 possible_xstate_size = xsave_size;
687
688
689 if (!is_supported_xstate_size(possible_xstate_size))
690 return -EINVAL;
691
692
693
694
695
696 fpu_kernel_xstate_size = possible_xstate_size;
697 do_extra_xstate_size_checks();
698
699
700
701
702 fpu_user_xstate_size = xsave_size;
703 return 0;
704}
705
706
707
708
709
710static void fpu__init_disable_system_xstate(void)
711{
712 xfeatures_mask_all = 0;
713 cr4_clear_bits(X86_CR4_OSXSAVE);
714 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
715}
716
717
718
719
720
721void __init fpu__init_system_xstate(void)
722{
723 unsigned int eax, ebx, ecx, edx;
724 static int on_boot_cpu __initdata = 1;
725 u64 xfeatures;
726 int err;
727 int i;
728
729 WARN_ON_FPU(!on_boot_cpu);
730 on_boot_cpu = 0;
731
732 if (!boot_cpu_has(X86_FEATURE_FPU)) {
733 pr_info("x86/fpu: No FPU detected\n");
734 return;
735 }
736
737 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
738 pr_info("x86/fpu: x87 FPU will use %s\n",
739 boot_cpu_has(X86_FEATURE_FXSR) ? "FXSAVE" : "FSAVE");
740 return;
741 }
742
743 if (boot_cpu_data.cpuid_level < XSTATE_CPUID) {
744 WARN_ON_FPU(1);
745 return;
746 }
747
748
749
750
751 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
752 xfeatures_mask_all = eax + ((u64)edx << 32);
753
754
755
756
757 cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
758 xfeatures_mask_all |= ecx + ((u64)edx << 32);
759
760 if ((xfeatures_mask_uabi() & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) {
761
762
763
764
765
766 pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n",
767 xfeatures_mask_all);
768 goto out_disable;
769 }
770
771
772
773
774 for (i = 0; i < ARRAY_SIZE(xsave_cpuid_features); i++) {
775 if (!boot_cpu_has(xsave_cpuid_features[i]))
776 xfeatures_mask_all &= ~BIT_ULL(i);
777 }
778
779 xfeatures_mask_all &= XFEATURE_MASK_USER_SUPPORTED |
780 XFEATURE_MASK_SUPERVISOR_SUPPORTED;
781
782
783 xfeatures = xfeatures_mask_all;
784
785
786 fpu__init_cpu_xstate();
787 err = init_xstate_size();
788 if (err)
789 goto out_disable;
790
791
792
793
794
795 update_regset_xstate_info(fpu_user_xstate_size, xfeatures_mask_uabi());
796
797 fpu__init_prepare_fx_sw_frame();
798 setup_init_fpu_buf();
799 setup_xstate_comp_offsets();
800 setup_supervisor_only_offsets();
801
802
803
804
805
806 if (xfeatures != xfeatures_mask_all) {
807 pr_err("x86/fpu: xfeatures modified from 0x%016llx to 0x%016llx during init, disabling XSAVE\n",
808 xfeatures, xfeatures_mask_all);
809 goto out_disable;
810 }
811
812 print_xstate_offset_size();
813 pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n",
814 xfeatures_mask_all,
815 fpu_kernel_xstate_size,
816 boot_cpu_has(X86_FEATURE_XSAVES) ? "compacted" : "standard");
817 return;
818
819out_disable:
820
821 fpu__init_disable_system_xstate();
822}
823
824
825
826
827void fpu__resume_cpu(void)
828{
829
830
831
832 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
833 xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask_uabi());
834
835
836
837
838
839 if (cpu_feature_enabled(X86_FEATURE_XSAVES)) {
840 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() |
841 xfeatures_mask_independent());
842 }
843}
844
845
846
847
848
849
850static void *__raw_xsave_addr(struct xregs_state *xsave, int xfeature_nr)
851{
852 if (!xfeature_enabled(xfeature_nr)) {
853 WARN_ON_FPU(1);
854 return NULL;
855 }
856
857 return (void *)xsave + xstate_comp_offsets[xfeature_nr];
858}
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr)
878{
879
880
881
882 if (!boot_cpu_has(X86_FEATURE_XSAVE))
883 return NULL;
884
885
886
887
888
889 WARN_ONCE(!(xfeatures_mask_all & BIT_ULL(xfeature_nr)),
890 "get of unsupported state");
891
892
893
894
895
896
897
898
899
900
901
902 if (!(xsave->header.xfeatures & BIT_ULL(xfeature_nr)))
903 return NULL;
904
905 return __raw_xsave_addr(xsave, xfeature_nr);
906}
907EXPORT_SYMBOL_GPL(get_xsave_addr);
908
909#ifdef CONFIG_ARCH_HAS_PKEYS
910
911
912
913
914
915int arch_set_user_pkey_access(struct task_struct *tsk, int pkey,
916 unsigned long init_val)
917{
918 u32 old_pkru, new_pkru_bits = 0;
919 int pkey_shift;
920
921
922
923
924
925 if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
926 return -EINVAL;
927
928
929
930
931
932
933 if (WARN_ON_ONCE(pkey >= arch_max_pkey()))
934 return -EINVAL;
935
936
937 if (init_val & PKEY_DISABLE_ACCESS)
938 new_pkru_bits |= PKRU_AD_BIT;
939 if (init_val & PKEY_DISABLE_WRITE)
940 new_pkru_bits |= PKRU_WD_BIT;
941
942
943 pkey_shift = pkey * PKRU_BITS_PER_PKEY;
944 new_pkru_bits <<= pkey_shift;
945
946
947 old_pkru = read_pkru();
948 old_pkru &= ~((PKRU_AD_BIT|PKRU_WD_BIT) << pkey_shift);
949
950
951 write_pkru(old_pkru | new_pkru_bits);
952
953 return 0;
954}
955#endif
956
957static void copy_feature(bool from_xstate, struct membuf *to, void *xstate,
958 void *init_xstate, unsigned int size)
959{
960 membuf_write(to, from_xstate ? xstate : init_xstate, size);
961}
962
963
964
965
966
967
968
969
970
971
972
973
974
975void copy_xstate_to_uabi_buf(struct membuf to, struct task_struct *tsk,
976 enum xstate_copy_mode copy_mode)
977{
978 const unsigned int off_mxcsr = offsetof(struct fxregs_state, mxcsr);
979 struct xregs_state *xsave = &tsk->thread.fpu.state.xsave;
980 struct xregs_state *xinit = &init_fpstate.xsave;
981 struct xstate_header header;
982 unsigned int zerofrom;
983 int i;
984
985 memset(&header, 0, sizeof(header));
986 header.xfeatures = xsave->header.xfeatures;
987
988
989 switch (copy_mode) {
990 case XSTATE_COPY_FP:
991 header.xfeatures &= XFEATURE_MASK_FP;
992 break;
993
994 case XSTATE_COPY_FX:
995 header.xfeatures &= XFEATURE_MASK_FP | XFEATURE_MASK_SSE;
996 break;
997
998 case XSTATE_COPY_XSAVE:
999 header.xfeatures &= xfeatures_mask_uabi();
1000 break;
1001 }
1002
1003
1004 copy_feature(header.xfeatures & XFEATURE_MASK_FP, &to, &xsave->i387,
1005 &xinit->i387, off_mxcsr);
1006
1007
1008 copy_feature(header.xfeatures & (XFEATURE_MASK_SSE | XFEATURE_MASK_YMM),
1009 &to, &xsave->i387.mxcsr, &xinit->i387.mxcsr,
1010 MXCSR_AND_FLAGS_SIZE);
1011
1012
1013 copy_feature(header.xfeatures & XFEATURE_MASK_FP,
1014 &to, &xsave->i387.st_space, &xinit->i387.st_space,
1015 sizeof(xsave->i387.st_space));
1016
1017
1018 copy_feature(header.xfeatures & XFEATURE_MASK_SSE,
1019 &to, &xsave->i387.xmm_space, &xinit->i387.xmm_space,
1020 sizeof(xsave->i387.xmm_space));
1021
1022 if (copy_mode != XSTATE_COPY_XSAVE)
1023 goto out;
1024
1025
1026 membuf_zero(&to, sizeof(xsave->i387.padding));
1027
1028
1029 membuf_write(&to, xstate_fx_sw_bytes, sizeof(xsave->i387.sw_reserved));
1030
1031
1032 membuf_write(&to, &header, sizeof(header));
1033
1034 zerofrom = offsetof(struct xregs_state, extended_state_area);
1035
1036 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
1037
1038
1039
1040
1041
1042
1043
1044 if (!(xfeatures_mask_uabi() & BIT_ULL(i)))
1045 continue;
1046
1047
1048
1049
1050
1051 if (zerofrom < xstate_offsets[i])
1052 membuf_zero(&to, xstate_offsets[i] - zerofrom);
1053
1054 if (i == XFEATURE_PKRU) {
1055 struct pkru_state pkru = {0};
1056
1057
1058
1059
1060
1061 pkru.pkru = tsk->thread.pkru;
1062 membuf_write(&to, &pkru, sizeof(pkru));
1063 } else {
1064 copy_feature(header.xfeatures & BIT_ULL(i), &to,
1065 __raw_xsave_addr(xsave, i),
1066 __raw_xsave_addr(xinit, i),
1067 xstate_sizes[i]);
1068 }
1069
1070
1071
1072
1073 zerofrom = xstate_offsets[i] + xstate_sizes[i];
1074 }
1075
1076out:
1077 if (to.left)
1078 membuf_zero(&to, to.left);
1079}
1080
1081static int copy_from_buffer(void *dst, unsigned int offset, unsigned int size,
1082 const void *kbuf, const void __user *ubuf)
1083{
1084 if (kbuf) {
1085 memcpy(dst, kbuf + offset, size);
1086 } else {
1087 if (copy_from_user(dst, ubuf + offset, size))
1088 return -EFAULT;
1089 }
1090 return 0;
1091}
1092
1093
1094static int copy_uabi_to_xstate(struct xregs_state *xsave, const void *kbuf,
1095 const void __user *ubuf)
1096{
1097 unsigned int offset, size;
1098 struct xstate_header hdr;
1099 u64 mask;
1100 int i;
1101
1102 offset = offsetof(struct xregs_state, header);
1103 if (copy_from_buffer(&hdr, offset, sizeof(hdr), kbuf, ubuf))
1104 return -EFAULT;
1105
1106 if (validate_user_xstate_header(&hdr))
1107 return -EINVAL;
1108
1109
1110 mask = XFEATURE_MASK_FP | XFEATURE_MASK_SSE | XFEATURE_MASK_YMM;
1111 if (hdr.xfeatures & mask) {
1112 u32 mxcsr[2];
1113
1114 offset = offsetof(struct fxregs_state, mxcsr);
1115 if (copy_from_buffer(mxcsr, offset, sizeof(mxcsr), kbuf, ubuf))
1116 return -EFAULT;
1117
1118
1119 if (mxcsr[0] & ~mxcsr_feature_mask)
1120 return -EINVAL;
1121
1122
1123 if (!(hdr.xfeatures & XFEATURE_MASK_FP)) {
1124 xsave->i387.mxcsr = mxcsr[0];
1125 xsave->i387.mxcsr_mask = mxcsr[1];
1126 }
1127 }
1128
1129 for (i = 0; i < XFEATURE_MAX; i++) {
1130 u64 mask = ((u64)1 << i);
1131
1132 if (hdr.xfeatures & mask) {
1133 void *dst = __raw_xsave_addr(xsave, i);
1134
1135 offset = xstate_offsets[i];
1136 size = xstate_sizes[i];
1137
1138 if (copy_from_buffer(dst, offset, size, kbuf, ubuf))
1139 return -EFAULT;
1140 }
1141 }
1142
1143
1144
1145
1146
1147 xsave->header.xfeatures &= XFEATURE_MASK_SUPERVISOR_ALL;
1148
1149
1150
1151
1152 xsave->header.xfeatures |= hdr.xfeatures;
1153
1154 return 0;
1155}
1156
1157
1158
1159
1160
1161
1162int copy_uabi_from_kernel_to_xstate(struct xregs_state *xsave, const void *kbuf)
1163{
1164 return copy_uabi_to_xstate(xsave, kbuf, NULL);
1165}
1166
1167
1168
1169
1170
1171
1172int copy_sigframe_from_user_to_xstate(struct xregs_state *xsave,
1173 const void __user *ubuf)
1174{
1175 return copy_uabi_to_xstate(xsave, NULL, ubuf);
1176}
1177
1178static bool validate_xsaves_xrstors(u64 mask)
1179{
1180 u64 xchk;
1181
1182 if (WARN_ON_FPU(!cpu_feature_enabled(X86_FEATURE_XSAVES)))
1183 return false;
1184
1185
1186
1187
1188 if (mask & xfeatures_mask_independent())
1189 xchk = ~xfeatures_mask_independent();
1190 else
1191 xchk = ~xfeatures_mask_all;
1192
1193 if (WARN_ON_ONCE(!mask || mask & xchk))
1194 return false;
1195
1196 return true;
1197}
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212void xsaves(struct xregs_state *xstate, u64 mask)
1213{
1214 int err;
1215
1216 if (!validate_xsaves_xrstors(mask))
1217 return;
1218
1219 XSTATE_OP(XSAVES, xstate, (u32)mask, (u32)(mask >> 32), err);
1220 WARN_ON_ONCE(err);
1221}
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237void xrstors(struct xregs_state *xstate, u64 mask)
1238{
1239 int err;
1240
1241 if (!validate_xsaves_xrstors(mask))
1242 return;
1243
1244 XSTATE_OP(XRSTORS, xstate, (u32)mask, (u32)(mask >> 32), err);
1245 WARN_ON_ONCE(err);
1246}
1247
1248#ifdef CONFIG_PROC_PID_ARCH_STATUS
1249
1250
1251
1252
1253static void avx512_status(struct seq_file *m, struct task_struct *task)
1254{
1255 unsigned long timestamp = READ_ONCE(task->thread.fpu.avx512_timestamp);
1256 long delta;
1257
1258 if (!timestamp) {
1259
1260
1261
1262 delta = -1;
1263 } else {
1264 delta = (long)(jiffies - timestamp);
1265
1266
1267
1268 if (delta < 0)
1269 delta = LONG_MAX;
1270 delta = jiffies_to_msecs(delta);
1271 }
1272
1273 seq_put_decimal_ll(m, "AVX512_elapsed_ms:\t", delta);
1274 seq_putc(m, '\n');
1275}
1276
1277
1278
1279
1280int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns,
1281 struct pid *pid, struct task_struct *task)
1282{
1283
1284
1285
1286 if (cpu_feature_enabled(X86_FEATURE_AVX512F))
1287 avx512_status(m, task);
1288
1289 return 0;
1290}
1291#endif
1292