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12#ifndef _K3_SA2UL_
13#define _K3_SA2UL_
14
15#include <crypto/aes.h>
16#include <crypto/sha1.h>
17#include <crypto/sha2.h>
18
19#define SA_ENGINE_ENABLE_CONTROL 0x1000
20
21struct sa_tfm_ctx;
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24
25#define SA_EEC_ENCSS_EN 0x00000001
26#define SA_EEC_AUTHSS_EN 0x00000002
27#define SA_EEC_TRNG_EN 0x00000008
28#define SA_EEC_PKA_EN 0x00000010
29#define SA_EEC_CTXCACH_EN 0x00000080
30#define SA_EEC_CPPI_PORT_IN_EN 0x00000200
31#define SA_EEC_CPPI_PORT_OUT_EN 0x00000800
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38#define SA_REQ_SUBTYPE_ENC 0x0001
39#define SA_REQ_SUBTYPE_DEC 0x0002
40#define SA_REQ_SUBTYPE_SHIFT 16
41#define SA_REQ_SUBTYPE_MASK 0xffff
42
43
44#define SA_DMA_NUM_EPIB_WORDS 4
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46
47#define SA_DMA_NUM_PS_WORDS 16
48#define NKEY_SZ 3
49#define MCI_SZ 27
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54
55#define SA_MAX_NUM_CTX 512
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59
60#define SA_CTX_SIZE_TO_DMA_SIZE(ctx_sz) \
61 ((ctx_sz) ? ((ctx_sz) / 32 - 1) : 0)
62
63#define SA_CTX_ENC_KEY_OFFSET 32
64#define SA_CTX_ENC_AUX1_OFFSET 64
65#define SA_CTX_ENC_AUX2_OFFSET 96
66#define SA_CTX_ENC_AUX3_OFFSET 112
67#define SA_CTX_ENC_AUX4_OFFSET 128
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69
70#define SA_ENG_ID_EM1 2
71#define SA_ENG_ID_EM2 3
72#define SA_ENG_ID_AM1 4
73#define SA_ENG_ID_AM2 5
74#define SA_ENG_ID_OUTPORT2 20
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78
79#define SA_CMDL_OFFSET_NESC 0
80#define SA_CMDL_OFFSET_LABEL_LEN 1
81
82#define SA_CMDL_OFFSET_DATA_LEN 2
83#define SA_CMDL_OFFSET_DATA_OFFSET 4
84#define SA_CMDL_OFFSET_OPTION_CTRL1 5
85#define SA_CMDL_OFFSET_OPTION_CTRL2 6
86#define SA_CMDL_OFFSET_OPTION_CTRL3 7
87#define SA_CMDL_OFFSET_OPTION_BYTE 8
88
89#define SA_CMDL_HEADER_SIZE_BYTES 8
90
91#define SA_CMDL_OPTION_BYTES_MAX_SIZE 72
92#define SA_CMDL_MAX_SIZE_BYTES (SA_CMDL_HEADER_SIZE_BYTES + \
93 SA_CMDL_OPTION_BYTES_MAX_SIZE)
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95
96#define SA_SW_INFO_FLAG_EVICT 0x0001
97#define SA_SW_INFO_FLAG_TEAR 0x0002
98#define SA_SW_INFO_FLAG_NOPD 0x0004
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105#define SA_CTX_PE_PKT_TYPE_3GPP_AIR 0
106#define SA_CTX_PE_PKT_TYPE_SRTP 1
107#define SA_CTX_PE_PKT_TYPE_IPSEC_AH 2
108
109#define SA_CTX_PE_PKT_TYPE_IPSEC_ESP 3
110
111#define SA_CTX_PE_PKT_TYPE_NONE 4
112#define SA_CTX_ENC_TYPE1_SZ 64
113#define SA_CTX_ENC_TYPE2_SZ 96
114
115#define SA_CTX_AUTH_TYPE1_SZ 64
116#define SA_CTX_AUTH_TYPE2_SZ 96
117
118#define SA_CTX_PHP_PE_CTX_SZ 64
119
120#define SA_CTX_MAX_SZ (64 + SA_CTX_ENC_TYPE2_SZ + SA_CTX_AUTH_TYPE2_SZ)
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134#define SA_CTX_DMA_SIZE_0 0
135#define SA_CTX_DMA_SIZE_64 1
136#define SA_CTX_DMA_SIZE_96 2
137#define SA_CTX_DMA_SIZE_128 3
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143#define SA_CTX_SCCTL_OWNER_OFFSET 0
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145#define SA_CTX_ENC_KEY_OFFSET 32
146#define SA_CTX_ENC_AUX1_OFFSET 64
147#define SA_CTX_ENC_AUX2_OFFSET 96
148#define SA_CTX_ENC_AUX3_OFFSET 112
149#define SA_CTX_ENC_AUX4_OFFSET 128
150
151#define SA_SCCTL_FE_AUTH_ENC 0x65
152#define SA_SCCTL_FE_ENC 0x8D
153
154#define SA_ALIGN_MASK (sizeof(u32) - 1)
155#define SA_ALIGNED __aligned(32)
156
157#define SA_AUTH_SW_CTRL_MD5 1
158#define SA_AUTH_SW_CTRL_SHA1 2
159#define SA_AUTH_SW_CTRL_SHA224 3
160#define SA_AUTH_SW_CTRL_SHA256 4
161#define SA_AUTH_SW_CTRL_SHA384 5
162#define SA_AUTH_SW_CTRL_SHA512 6
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164
165#define SA_MAX_DATA_SZ U16_MAX
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171#define SA_UNSAFE_DATA_SZ_MIN 240
172#define SA_UNSAFE_DATA_SZ_MAX 256
173
174struct sa_match_data;
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193struct sa_crypto_data {
194 void __iomem *base;
195 const struct sa_match_data *match_data;
196 struct platform_device *pdev;
197 struct dma_pool *sc_pool;
198 struct device *dev;
199 spinlock_t scid_lock;
200
201 u16 sc_id_start;
202 u16 sc_id_end;
203 u16 sc_id;
204 unsigned long ctx_bm[DIV_ROUND_UP(SA_MAX_NUM_CTX,
205 BITS_PER_LONG)];
206 struct sa_tfm_ctx *ctx;
207 struct dma_chan *dma_rx1;
208 struct dma_chan *dma_rx2;
209 struct dma_chan *dma_tx;
210};
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218struct sa_cmdl_param_info {
219 u16 index;
220 u16 offset;
221 u16 size;
222};
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225#define SA_MAX_AUX_DATA_WORDS 8
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245struct sa_cmdl_upd_info {
246 u16 flags;
247 u16 submode;
248 struct sa_cmdl_param_info enc_size;
249 struct sa_cmdl_param_info enc_size2;
250 struct sa_cmdl_param_info enc_offset;
251 struct sa_cmdl_param_info enc_iv;
252 struct sa_cmdl_param_info enc_iv2;
253 struct sa_cmdl_param_info aad;
254 struct sa_cmdl_param_info payload;
255 struct sa_cmdl_param_info auth_size;
256 struct sa_cmdl_param_info auth_size2;
257 struct sa_cmdl_param_info auth_offset;
258 struct sa_cmdl_param_info auth_iv;
259 struct sa_cmdl_param_info aux_key_info;
260 u32 aux_key[SA_MAX_AUX_DATA_WORDS];
261};
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269#define SA_PSDATA_CTX_WORDS 4
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272#define SA_MAX_CMDL_WORDS (SA_DMA_NUM_PS_WORDS - SA_PSDATA_CTX_WORDS)
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284struct sa_ctx_info {
285 u8 *sc;
286 dma_addr_t sc_phys;
287 u16 sc_id;
288 u16 cmdl_size;
289 u32 cmdl[SA_MAX_CMDL_WORDS];
290 struct sa_cmdl_upd_info cmdl_upd_info;
291
292 u32 epib[SA_DMA_NUM_EPIB_WORDS];
293};
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305struct sa_tfm_ctx {
306 struct sa_crypto_data *dev_data;
307 struct sa_ctx_info enc;
308 struct sa_ctx_info dec;
309 struct sa_ctx_info auth;
310 int keylen;
311 int iv_idx;
312 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
313 u8 authkey[SHA512_BLOCK_SIZE];
314 struct crypto_shash *shash;
315
316 union {
317 struct crypto_skcipher *skcipher;
318 struct crypto_ahash *ahash;
319 struct crypto_aead *aead;
320 } fallback;
321};
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329struct sa_sha_req_ctx {
330 struct sa_crypto_data *dev_data;
331 u32 cmdl[SA_MAX_CMDL_WORDS + SA_PSDATA_CTX_WORDS];
332 struct ahash_request fallback_req;
333};
334
335enum sa_submode {
336 SA_MODE_GEN = 0,
337 SA_MODE_CCM,
338 SA_MODE_GCM,
339 SA_MODE_GMAC
340};
341
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343enum sa_ealg_id {
344 SA_EALG_ID_NONE = 0,
345 SA_EALG_ID_NULL,
346 SA_EALG_ID_AES_CTR,
347 SA_EALG_ID_AES_F8,
348 SA_EALG_ID_AES_CBC,
349 SA_EALG_ID_DES_CBC,
350 SA_EALG_ID_3DES_CBC,
351 SA_EALG_ID_CCM,
352 SA_EALG_ID_GCM,
353 SA_EALG_ID_AES_ECB,
354 SA_EALG_ID_LAST
355};
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358enum sa_aalg_id {
359 SA_AALG_ID_NONE = 0,
360 SA_AALG_ID_NULL = SA_EALG_ID_LAST,
361 SA_AALG_ID_MD5,
362 SA_AALG_ID_SHA1,
363 SA_AALG_ID_SHA2_224,
364 SA_AALG_ID_SHA2_256,
365 SA_AALG_ID_SHA2_512,
366 SA_AALG_ID_HMAC_MD5,
367 SA_AALG_ID_HMAC_SHA1,
368 SA_AALG_ID_HMAC_SHA2_224,
369 SA_AALG_ID_HMAC_SHA2_256,
370 SA_AALG_ID_GMAC,
371 SA_AALG_ID_CMAC,
372 SA_AALG_ID_CBC_MAC,
373 SA_AALG_ID_AES_XCBC
374};
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380enum sa_eng_algo_id {
381 SA_ENG_ALGO_ECB = 0,
382 SA_ENG_ALGO_CBC,
383 SA_ENG_ALGO_CFB,
384 SA_ENG_ALGO_OFB,
385 SA_ENG_ALGO_CTR,
386 SA_ENG_ALGO_F8,
387 SA_ENG_ALGO_F8F9,
388 SA_ENG_ALGO_GCM,
389 SA_ENG_ALGO_GMAC,
390 SA_ENG_ALGO_CCM,
391 SA_ENG_ALGO_CMAC,
392 SA_ENG_ALGO_CBCMAC,
393 SA_NUM_ENG_ALGOS
394};
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401struct sa_eng_info {
402 u8 eng_id;
403 u16 sc_size;
404};
405
406#endif
407