LXR linux/drivers/fpga/versal-fpga.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2019-2021 Xilinx, Inc.
   4 */
   5
   6#include <linux/dma-mapping.h>
   7#include <linux/fpga/fpga-mgr.h>
   8#include <linux/io.h>
   9#include <linux/kernel.h>
  10#include <linux/module.h>
  11#include <linux/of_address.h>
  12#include <linux/string.h>
  13#include <linux/firmware/xlnx-zynqmp.h>
  14
  15static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
  16                                      struct fpga_image_info *info,
  17                                      const char *buf, size_t size)
  18{
  19        return 0;
  20}
  21
  22static int versal_fpga_ops_write_sg(struct fpga_manager *mgr,
  23                                    struct sg_table *sgt)
  24{
  25        dma_addr_t dma_addr;
  26        int ret;
  27
  28        dma_addr = sg_dma_address(sgt->sgl);
  29        ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
  30
  31        return ret;
  32}
  33
  34static int versal_fpga_ops_write(struct fpga_manager *mgr,
  35                                 const char *buf, size_t size)
  36{
  37        dma_addr_t dma_addr = 0;
  38        char *kbuf;
  39        int ret;
  40
  41        kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);
  42        if (!kbuf)
  43                return -ENOMEM;
  44
  45        memcpy(kbuf, buf, size);
  46        ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
  47        dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
  48
  49        return ret;
  50}
  51
  52static const struct fpga_manager_ops versal_fpga_ops = {
  53        .write_init = versal_fpga_ops_write_init,
  54        .write = versal_fpga_ops_write,
  55        .write_sg = versal_fpga_ops_write_sg,
  56};
  57
  58static int versal_fpga_probe(struct platform_device *pdev)
  59{
  60        struct device *dev = &pdev->dev;
  61        struct fpga_manager *mgr;
  62        int ret;
  63
  64        ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  65        if (ret < 0) {
  66                dev_err(dev, "no usable DMA configuration\n");
  67                return ret;
  68        }
  69
  70        mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
  71                                   &versal_fpga_ops, NULL);
  72        if (!mgr)
  73                return -ENOMEM;
  74
  75        return devm_fpga_mgr_register(dev, mgr);
  76}
  77
  78static const struct of_device_id versal_fpga_of_match[] = {
  79        { .compatible = "xlnx,versal-fpga", },
  80        {},
  81};
  82MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
  83
  84static struct platform_driver versal_fpga_driver = {
  85        .probe = versal_fpga_probe,
  86        .driver = {
  87                .name = "versal_fpga_manager",
  88                .of_match_table = of_match_ptr(versal_fpga_of_match),
  89        },
  90};
  91module_platform_driver(versal_fpga_driver);
  92
  93MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");
  94MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>");
  95MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
  96MODULE_LICENSE("GPL");
  97