LXR linux/drivers/gpu/drm/amd/amdgpu/gfx_v10

   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/delay.h>
  25#include <linux/kernel.h>
  26#include <linux/firmware.h>
  27#include <linux/module.h>
  28#include <linux/pci.h>
  29#include "amdgpu.h"
  30#include "amdgpu_gfx.h"
  31#include "amdgpu_psp.h"
  32#include "nv.h"
  33#include "nvd.h"
  34
  35#include "gc/gc_10_1_0_offset.h"
  36#include "gc/gc_10_1_0_sh_mask.h"
  37#include "smuio/smuio_11_0_0_offset.h"
  38#include "smuio/smuio_11_0_0_sh_mask.h"
  39#include "navi10_enum.h"
  40#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42#include "soc15.h"
  43#include "soc15d.h"
  44#include "soc15_common.h"
  45#include "clearstate_gfx10.h"
  46#include "v10_structs.h"
  47#include "gfx_v10_0.h"
  48#include "nbio_v2_3.h"
  49
  50/*
  51 * Navi10 has two graphic rings to share each graphic pipe.
  52 * 1. Primary ring
  53 * 2. Async ring
  54 */
  55#define GFX10_NUM_GFX_RINGS_NV1X        1
  56#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57#define GFX10_MEC_HPD_SIZE      2048
  58
  59#define RLCG_VFGATE_DISABLED    0x4000000
  60#define RLCG_WRONG_OPERATION_TYPE       0x2000000
  61#define RLCG_NOT_IN_RANGE       0x1000000
  62
  63#define F32_CE_PROGRAM_RAM_SIZE         65536
  64#define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  65
  66#define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  67#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  68#define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  69#define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  70#define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  71#define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  72
  73#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  74#define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  75
  76#define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  77#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  78#define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  79#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  80
  81#define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  82#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  83#define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  84#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  85#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  86#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  87#define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  88#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  89#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  90#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  91#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  92#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  93#define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  94#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  95#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  96#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  97#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  98#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  99#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
 100#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
 101#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
 102#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
 103#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 104#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 105#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 106#define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 107#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 108
 109#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 110#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 111#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 112#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 113#define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 114#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 115#define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 116#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 117#define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 118#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 119#define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 120#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 121#define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 122#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 123#define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 124#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 125#define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 126#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 127#define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 128#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 129#define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 130#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 131#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 132
 133#define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 134#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 135#define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 136#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 137#define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 138#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 139#define mmCP_HYP_CE_UCODE_DATA                  0x5819
 140#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 141#define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 142#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 143#define mmCP_HYP_ME_UCODE_DATA                  0x5817
 144#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 145
 146#define mmCPG_PSP_DEBUG                         0x5c10
 147#define mmCPG_PSP_DEBUG_BASE_IDX                1
 148#define mmCPC_PSP_DEBUG                         0x5c11
 149#define mmCPC_PSP_DEBUG_BASE_IDX                1
 150#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 151#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 152
 153//CC_GC_SA_UNIT_DISABLE
 154#define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 155#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 156#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 157#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 158//GC_USER_SA_UNIT_DISABLE
 159#define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 160#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 161#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 162#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 163//PA_SC_ENHANCE_3
 164#define mmPA_SC_ENHANCE_3                       0x1085
 165#define mmPA_SC_ENHANCE_3_BASE_IDX              0
 166#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 167#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 168
 169#define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 170#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 171
 172#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 173#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 174#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 175#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 176
 177#define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 178#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 179
 180#define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 181#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 182
 183#define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 184#define GFX_RLCG_GC_WRITE       (0x0 << 28)
 185#define GFX_RLCG_GC_READ        (0x1 << 28)
 186#define GFX_RLCG_MMHUB_WRITE    (0x2 << 28)
 187
 188#define RLCG_ERROR_REPORT_ENABLED(adev) \
 189        (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
 190
 191MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 192MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 193MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 194MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 195MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 196MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 197
 198MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 199MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 200MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 201MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 202MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 203MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 204MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 205MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 206MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 207MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 208MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 209
 210MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 211MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 212MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 213MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 214MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 215MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 216
 217MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 218MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 219MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 220MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 221MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 222MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 223
 224MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 225MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 226MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 227MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 228MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 229MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 230
 231MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 232MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 233MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 234MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 235MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 236MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 237
 238MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 239MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 240MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 241MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 242MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 243MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 244
 245MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 246MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 247MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 248MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 249MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 250MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 251
 252MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 253MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 254MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 255MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 256MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 257MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 258
 259MODULE_FIRMWARE("amdgpu/cyan_skillfish_ce.bin");
 260MODULE_FIRMWARE("amdgpu/cyan_skillfish_pfp.bin");
 261MODULE_FIRMWARE("amdgpu/cyan_skillfish_me.bin");
 262MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec.bin");
 263MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec2.bin");
 264MODULE_FIRMWARE("amdgpu/cyan_skillfish_rlc.bin");
 265
 266MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 267MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 268MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 269MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 270MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 271MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 272
 273static const struct soc15_reg_golden golden_settings_gc_10_0[] =
 274{
 275        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 276        /* TA_GRAD_ADJ_UCONFIG -> TA_GRAD_ADJ */
 277        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382),
 278        /* VGT_TF_RING_SIZE_UMD -> VGT_TF_RING_SIZE */
 279        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2262c24e),
 280        /* VGT_HS_OFFCHIP_PARAM_UMD -> VGT_HS_OFFCHIP_PARAM */
 281        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x226cc24f),
 282        /* VGT_TF_MEMORY_BASE_UMD -> VGT_TF_MEMORY_BASE */
 283        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x226ec250),
 284        /* VGT_TF_MEMORY_BASE_HI_UMD -> VGT_TF_MEMORY_BASE_HI */
 285        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2278c261),
 286        /* VGT_ESGS_RING_SIZE_UMD -> VGT_ESGS_RING_SIZE */
 287        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2232c240),
 288        /* VGT_GSVS_RING_SIZE_UMD -> VGT_GSVS_RING_SIZE */
 289        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2233c241),
 290};
 291
 292static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 293{
 294        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 295        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 296        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 297        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 298        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 299        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 300        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 301        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 302        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 303        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 304        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 305        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 306        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 307        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 308        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 309        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 310        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 311        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 312        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 313        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 314        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 315        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 316        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 317        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 318        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 319        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 320        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 321        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 322        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 323        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 324        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 325        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 326        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 327        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 328        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 329        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 330        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 331        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 332        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 333        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 334};
 335
 336static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 337{
 338        /* Pending on emulation bring up */
 339};
 340
 341static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 342{
 343        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 344        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 346        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 348        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 350        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 352        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 353        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 354        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 355        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 356        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 358        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 360        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 362        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 364        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 366        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 368        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 370        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 372        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 374        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 376        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 378        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 380        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 382        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 384        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 386        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 388        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 390        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 392        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 394        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 396        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 398        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 400        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 401        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 402        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 403        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 404        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 406        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 408        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 410        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 412        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 414        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 416        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 418        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 420        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 422        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 424        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 426        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 428        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 430        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 432        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 434        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 436        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 438        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 440        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 442        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 444        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 446        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 448        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 450        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 452        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 454        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 456        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 458        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 460        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 462        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 464        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 466        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 468        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 470        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 472        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 474        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 476        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 478        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 480        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 482        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 484        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 486        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 488        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 490        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 492        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 494        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 496        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 498        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 500        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 502        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 504        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 506        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 508        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 510        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 512        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 514        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 516        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 518        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 520        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 522        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 524        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 526        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 528        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 530        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 532        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 534        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 536        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 538        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 540        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 542        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 544        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 546        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 548        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 550        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 552        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 554        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 556        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 557        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 558        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 560        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 562        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 564        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 565        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 566        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 568        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 570        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 572        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 574        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 576        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 578        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 580        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 582        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 584        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 586        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 588        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 590        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 592        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 594        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 596        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 598        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 600        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 602        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 604        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 606        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 608        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 610        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 612        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 614        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 616        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 618        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 620        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 622        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 624        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 626        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 628        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 630        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 632        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 634        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 636        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 638        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 640        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 642        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 644        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 646        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 648        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 650        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 652        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 654        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 656        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 658        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 660        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 662        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 664        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 666        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 668        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 670        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 672        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 674        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 676        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 678        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 680        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 682        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 684        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 686        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 688        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 690        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 692        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 694        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 696        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 698        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 700        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 702        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 704        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 706        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 708        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 710        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 712        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 714        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 716        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 718        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 720        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 722        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 724        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 726        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 728        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 730        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 732        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 734        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 736        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 738        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 740        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 742        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 744        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 746        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 748        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 750        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 752        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 754        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 756        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 758        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 760        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 762        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 764        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 766        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 768        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 770        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 772        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 774        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 776        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 778        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 780        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 782        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 784        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 786        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 788        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 790        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 792        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 794        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 796        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 798        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 800        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 802        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 804        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 806        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 808        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 810        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 812        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 814        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 816        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 818        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 820        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 822        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 824        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 826        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 828        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 830        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 832        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 834        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 836        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 838        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 840        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 842        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 844        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 846        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 848        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 850        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 852        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 854        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 856        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 858        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 860        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 862        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 864        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 866        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 868        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 870        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 872        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 874        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 876        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 878        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 880        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 882        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 884        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 886        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 888        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 890        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 892        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 894        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 896        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 898        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 900        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 902        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 904        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 906        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 908        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 910        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 912        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 914        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 916        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 918        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 920        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 922        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 924        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 926        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 928        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 930        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 932        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 934        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 936        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 938        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 940        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 942        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 944        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 946        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 948        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 950        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 952        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 954        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 956        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 958        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 960        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 962        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 964        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 966        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 968        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 970        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 972        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 974        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 976        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 978        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 980        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 982        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 984        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 986        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 988        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 990        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 992        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 994        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 996        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 998        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1000        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),

1001        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1002        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1004        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1006        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1008        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1010        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1012        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1014        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1016        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1018        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1020        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1022        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1024        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1026        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1028        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1030        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1032        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1034        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1036        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1038        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1040        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1042        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1044        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1046        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1048        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1050        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1052        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1054        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1056        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1058        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1060        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1062        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1064        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1066        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1068        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1070        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1072        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1074        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1076        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1078        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1080        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1082        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1084        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1086        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1088        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1090        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1092        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1094        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1096        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1098        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1100        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1102        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1104        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1106        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1108        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1110        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1112        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1114        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1116        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1118        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1120        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1122        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1124        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1126        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1128        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1130        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1132        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1134        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1136        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1138        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1140        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1142        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1144        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1146        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1148        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1150        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1152        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1154        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1156        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1158        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1160        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1162        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1164        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1166        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1168        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1170        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1172        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1174        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1176        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1178        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1180        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1182        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1184        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1186        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1188        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1190        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1192        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1194        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1196        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1198        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1200        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1202        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1204        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1206        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1208        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1210        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1212        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1214        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1216        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1218        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1220        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1222        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1224        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1226        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1228        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1230        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1232        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1234        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1236        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1238        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1240        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1242        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1244        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1246        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1248        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1250        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1252        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1254        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1256        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1258        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1260        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1262        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1264        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1266        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1268        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1270        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1272        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1274        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1276        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1278        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1280        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1282        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1284        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1286        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1288        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1290        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1292        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1294        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1296        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1298        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1300        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1302        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1304        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1306        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1308        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1310        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1312        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1314        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1316        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1318        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1319        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1320        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1322        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1324        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1326        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1328        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1330        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1332        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1334        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1335        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1336        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1338        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1340        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1341        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1342        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1343        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1344        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1346        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1348        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1350        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1352        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1354        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1356        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1357        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1358        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1360        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1362        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1364        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1365        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1366        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1367        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1368        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1370        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1372        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1374        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1375        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1376        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1377        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1378        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1379        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1380        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1381        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1382        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1383        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1384        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1385        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1386        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1387        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1388        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1389        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1390        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1391        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1392        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1393        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1394        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1395};
1396
1397static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1398{
1399        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1400        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1401        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1402        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1403        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1404        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1405        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1406        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1407        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1408        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1409        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1410        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1411        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1412        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1413        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1414        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1415        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1416        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1417        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1418        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1419        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1420        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1421        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1422        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1423        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1424        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1425        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1426        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1427        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1428        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1429        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1430        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1431        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1432        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1433        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1434        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1435        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1436        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1437};
1438
1439static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1440{
1441        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1442        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1443        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1444        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1445        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1446        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1447        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1448        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1449        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1450        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1451        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1452        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1453        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1454        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1455        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1456        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1457        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1458        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1459        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1460        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1461        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1462        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1463        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1464        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1465        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1466        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1467        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1468        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1469        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1470        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1471        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1472        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1473        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1474        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1475        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1476        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1477        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1478        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1479        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1480        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1481        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1482        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1483};
1484
1485static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
1486                                 int write, u32 *rlcg_flag)
1487{
1488        switch (hwip) {
1489        case GC_HWIP:
1490                if (amdgpu_sriov_reg_indirect_gc(adev)) {
1491                        *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1492
1493                        return true;
1494                /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
1495                } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
1496                        *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
1497
1498                        return true;
1499                }
1500
1501                break;
1502        case MMHUB_HWIP:
1503                if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
1504                    (acc_flags & AMDGPU_REGS_RLC) && write) {
1505                        *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
1506                        return true;
1507                }
1508
1509                break;
1510        default:
1511                DRM_DEBUG("Not program register by RLCG\n");
1512        }
1513
1514        return false;
1515}
1516
1517static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1518{
1519        static void *scratch_reg0;
1520        static void *scratch_reg1;
1521        static void *scratch_reg2;
1522        static void *scratch_reg3;
1523        static void *spare_int;
1524        static uint32_t grbm_cntl;
1525        static uint32_t grbm_idx;
1526        uint32_t i = 0;
1527        uint32_t retries = 50000;
1528        u32 ret = 0;
1529        u32 tmp;
1530
1531        scratch_reg0 = adev->rmmio +
1532                       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1533        scratch_reg1 = adev->rmmio +
1534                       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1535        scratch_reg2 = adev->rmmio +
1536                       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1537        scratch_reg3 = adev->rmmio +
1538                       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1539
1540        if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
1541                spare_int = adev->rmmio +
1542                            (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
1543                             + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
1544        } else {
1545                spare_int = adev->rmmio +
1546                            (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1547        }
1548
1549        grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1550        grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1551
1552        if (offset == grbm_cntl || offset == grbm_idx) {
1553                if (offset  == grbm_cntl)
1554                        writel(v, scratch_reg2);
1555                else if (offset == grbm_idx)
1556                        writel(v, scratch_reg3);
1557
1558                writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1559        } else {
1560                writel(v, scratch_reg0);
1561                writel(offset | flag, scratch_reg1);
1562                writel(1, spare_int);
1563
1564                for (i = 0; i < retries; i++) {
1565                        tmp = readl(scratch_reg1);
1566                        if (!(tmp & flag))
1567                                break;
1568
1569                        udelay(10);
1570                }
1571
1572                if (i >= retries) {
1573                        if (RLCG_ERROR_REPORT_ENABLED(adev)) {
1574                                if (tmp & RLCG_VFGATE_DISABLED)
1575                                        pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
1576                                else if (tmp & RLCG_WRONG_OPERATION_TYPE)
1577                                        pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
1578                                else if (tmp & RLCG_NOT_IN_RANGE)
1579                                        pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
1580                                else
1581                                        pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
1582                        } else
1583                                pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
1584                }
1585        }
1586
1587        ret = readl(scratch_reg0);
1588
1589        return ret;
1590}
1591
1592static void gfx_v10_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
1593{
1594        u32 rlcg_flag;
1595
1596        if (!amdgpu_sriov_runtime(adev) &&
1597            gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
1598                gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1599                return;
1600        }
1601
1602        if (acc_flags & AMDGPU_REGS_NO_KIQ)
1603                WREG32_NO_KIQ(offset, value);
1604        else
1605                WREG32(offset, value);
1606}
1607
1608static u32 gfx_v10_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
1609{
1610        u32 rlcg_flag;
1611
1612        if (!amdgpu_sriov_runtime(adev) &&
1613            gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
1614                return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1615
1616        if (acc_flags & AMDGPU_REGS_NO_KIQ)
1617                return RREG32_NO_KIQ(offset);
1618        else
1619                return RREG32(offset);
1620}
1621
1622static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1623{
1624        /* Pending on emulation bring up */
1625};
1626
1627static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1628{
1629        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1630        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1632        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1634        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1636        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1638        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1640        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1642        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1644        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1646        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1648        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1650        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1652        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1654        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1656        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1658        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1660        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1662        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1664        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1666        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1668        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1670        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1672        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1674        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1676        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1678        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1680        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1682        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1684        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1686        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1688        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1690        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1692        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1694        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1696        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1698        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1700        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1702        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1704        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1706        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1708        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1710        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1712        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1714        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1716        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1718        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1720        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1722        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1724        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1726        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1728        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1730        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1732        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1734        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1736        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1738        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1740        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1742        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1744        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1746        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1748        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1750        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1752        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1754        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1756        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1758        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1760        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1762        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1764        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1766        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1768        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1770        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1772        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1774        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1776        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1778        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1780        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1782        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1784        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1786        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1788        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1790        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1792        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1794        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1796        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1798        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1800        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1802        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1804        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1806        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1808        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1810        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1812        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1814        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1816        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1818        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1820        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1822        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1824        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1826        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1828        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1830        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1832        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1834        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1836        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1838        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1840        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1842        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1844        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1846        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1848        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1850        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1852        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1854        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1856        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1858        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1860        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1862        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1864        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1866        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1868        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1870        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1872        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1874        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1876        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1878        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1880        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1882        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1884        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1886        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1888        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1890        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1892        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1894        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1896        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1898        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1900        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1902        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1904        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1906        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1908        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1910        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1912        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1914        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1916        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1918        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1920        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1922        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1924        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1926        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1928        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1930        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1932        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1934        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1936        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1938        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1940        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1942        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1944        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1946        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1948        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1950        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1952        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1954        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1956        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1958        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1960        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1962        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1964        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1966        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1968        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1970        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1972        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1974        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1976        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1978        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1980        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1982        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1984        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1986        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1988        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1990        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1992        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1994        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1996        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1998        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2000        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),

2001        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2002        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2004        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2006        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2008        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2010        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2012        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2014        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2016        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2018        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2020        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2022        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2024        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2026        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2028        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2030        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2032        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2034        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2036        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2038        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2040        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2042        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2044        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2046        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2048        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2050        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2052        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2054        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2056        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2058        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2060        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2062        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2064        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2066        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2068        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2070        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2072        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2074        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2076        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2078        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2080        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2082        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2084        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2086        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2088        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2090        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2092        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2094        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2096        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2098        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2100        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2102        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2104        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2106        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2108        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2110        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2112        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2114        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2116        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2118        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2120        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2122        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2124        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2126        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2128        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2130        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2132        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2134        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2136        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2138        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2140        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2142        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2144        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2146        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2148        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2150        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2152        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2154        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2156        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2158        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2160        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2162        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2164        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2166        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2168        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2170        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2172        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2174        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2176        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2178        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2180        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2182        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2184        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2186        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2188        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2190        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2192        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2194        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2196        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2198        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2200        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2202        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2204        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2206        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2208        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2210        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2212        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2214        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2216        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2218        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2220        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2222        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2224        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2226        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2228        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2230        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2232        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2234        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2236        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2238        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2240        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2241        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2242        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2244        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2245        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2246        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2248        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2249};
2250
2251static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2252{
2253        /* Pending on emulation bring up */
2254};
2255
2256static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2257{
2258        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2259        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2261        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2263        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2265        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2267        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2268        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2269        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2270        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2271        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2273        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2275        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2277        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2279        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2281        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2283        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2285        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2287        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2289        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2291        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2293        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2295        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2297        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2299        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2301        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2303        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2305        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2307        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2309        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2311        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2313        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2315        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2316        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2317        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2318        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2319        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2321        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2323        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2325        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2327        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2329        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2331        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2333        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2335        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2337        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2339        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2341        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2343        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2345        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2347        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2349        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2351        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2353        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2355        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2357        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2359        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2361        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2363        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2365        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2367        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2369        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2371        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2373        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2375        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2377        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2379        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2381        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2383        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2385        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2387        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2389        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2391        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2393        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2395        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2397        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2399        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2401        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2403        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2405        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2407        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2409        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2411        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2413        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2415        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2417        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2419        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2421        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2423        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2425        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2427        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2429        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2431        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2433        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2435        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2437        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2439        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2441        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2443        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2445        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2447        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2449        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2451        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2453        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2455        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2457        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2459        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2461        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2463        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2465        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2467        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2469        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2471        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2473        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2475        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2477        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2479        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2481        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2483        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2485        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2487        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2489        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2491        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2493        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2495        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2497        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2499        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2501        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2503        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2505        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2507        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2509        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2511        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2513        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2515        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2517        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2519        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2521        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2523        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2525        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2527        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2529        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2531        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2533        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2535        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2537        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2539        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2541        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2543        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2545        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2547        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2549        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2551        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2553        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2555        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2557        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2559        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2561        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2563        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2565        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2567        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2569        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2571        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2573        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2575        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2577        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2579        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2581        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2583        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2585        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2587        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2589        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2591        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2593        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2595        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2597        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2599        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2601        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2603        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2605        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2607        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2609        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2611        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2613        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2615        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2617        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2619        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2621        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2623        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2625        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2627        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2629        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2631        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2633        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2635        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2637        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2639        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2641        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2643        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2645        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2647        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2649        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2651        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2653        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2655        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2657        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2659        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2661        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2663        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2665        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2667        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2669        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2671        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2673        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2675        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2677        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2679        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2681        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2683        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2685        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2687        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2689        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2691        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2693        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2695        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2697        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2699        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2701        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2703        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2705        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2707        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2709        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2711        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2713        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2715        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2717        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2719        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2721        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2723        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2725        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2727        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2729        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2731        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2733        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2735        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2737        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2739        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2741        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2743        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2745        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2747        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2749        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2751        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2753        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2755        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2757        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2759        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2761        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2763        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2765        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2767        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2769        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2771        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2773        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2775        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2777        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2779        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2781        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2783        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2785        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2787        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2789        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2791        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2793        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2795        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2797        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2799        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2801        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2803        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2805        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2807        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2809        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2811        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2813        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2815        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2817        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2819        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2821        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2825        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2827        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2829        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2831        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2833        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2835        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2837        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2839        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2841        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2843        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2845        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2847        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2849        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2851        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2853        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2855        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2857        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2859        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2861        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2863        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2865        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2867        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2869        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2871        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2873        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2875        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2877        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2879        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2881        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2883        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2885        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2887        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2889        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2891        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2893        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2895        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2897        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2899        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2901        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2903        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2905        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2907        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2909        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2911        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2913        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2915        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2917        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2919        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2921        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2923        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2925        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2927        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2929        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2931        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2933        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2935        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2937        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2939        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2941        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2943        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2945        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2947        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2949        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2951        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2953        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2955        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2957        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2959        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2961        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2963        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2965        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2967        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2969        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2971        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2973        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2975        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2977        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2979        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2981        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2983        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2985        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2987        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2989        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2991        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2993        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2995        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2997        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2999        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),

3001        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3003        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3005        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3007        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3009        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3011        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3013        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3015        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3017        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3019        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3021        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3023        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3025        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3027        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3029        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3031        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3033        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3035        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3037        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3039        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3041        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3043        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3045        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3047        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3049        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3051        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3053        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3055        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3057        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3059        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3061        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3063        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3065        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3067        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3069        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3071        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3073        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3075        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3077        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3079        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3081        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3083        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3085        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3087        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3089        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3091        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3093        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3095        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3097        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3098        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3099        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3101        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3103        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3105        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3107        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3109        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3111        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3113        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3115        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3117        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3119        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3121        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3122        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3123        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3125        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3127        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3129        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3131        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3133        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3135        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3137        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3138        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3139        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3141        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3142        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3143        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3145        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3146        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3147        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3149        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3150        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3151        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3153        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3154        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3155        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3157        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3158        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3159        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3161        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3162        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3163        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3165        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3166        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3167        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3169        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3170        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3171        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3173        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3174        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3175        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3177        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3178        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3179        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3181        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3182        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3183        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3185        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3186        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3187        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3189        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3190        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3191        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3193        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3194        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3195        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3197        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3198        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3199        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3201        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3202        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3203        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3205        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3207        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3208        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3209        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3210        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3211        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3213        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3214        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3215        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3217        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3218        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3219        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3221        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3222        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3223        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3225        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3226        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3227        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3229        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3231        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3232        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3233        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3234        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3235        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3236        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3237        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3239        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3241        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3242        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3243        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3244        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3245        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3246        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3247        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3248        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3249        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3250        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3251        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3252        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3253        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3254        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3255        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3256        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3257        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3258        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3259        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3260        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3261        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3262        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3263        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3264        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3265        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3266        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3267        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3268        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3269        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3270        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3271        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3272        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3273        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3274        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3275        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3276        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3277        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3278        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3279        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3280        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3281        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3282        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3283        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3284        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3285        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3286        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3287        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3288        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3289        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3290        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3291        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3292        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3293        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3294        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3295        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3296        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3297        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3298        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3299        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3300        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3301        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3302        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3303        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3304        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3305        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3306        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3307        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3308        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3309        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3310};
3311
3312static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3313{
3314        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3316        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3317        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3318        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3319        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3320        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3321        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3322        SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3323        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3324        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3325        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3326        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3327        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3328        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3329        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3330        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3331        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3332        SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3333        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3334        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3335        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3336        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3337        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3338        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3339        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3340        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3341        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3342        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3343        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3344        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3345        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3346        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3347        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3348        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3349        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3350        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3351        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3352        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3353        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3354        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3355        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3356        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3357};
3358
3359static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3360{
3361        /* Pending on emulation bring up */
3362};
3363
3364static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3365{
3366        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3367        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3368        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3369        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3370        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3371        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3372        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3373        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3374        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3375        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3376        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3377        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3378        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3379        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3380        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3381        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3382        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3383        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3384        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3385        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3386        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3387        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3388        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3389        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3390        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3391        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3392        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3393        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3394        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3395        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3396        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3397        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3398        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3399        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3400        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3401        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3402        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3403        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3404        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3405        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3406        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3407
3408        /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3409        SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3410};
3411
3412static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3413{
3414        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3415        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3416        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3417        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3418        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3419        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3420        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3421        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3422        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3423        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3424        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3425        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3426        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3427        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3428        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3429        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3430        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3431        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3432        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3433        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3434        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3435        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3436        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3437        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3438
3439        /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3440        SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3441};
3442
3443static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3444{
3445        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3446        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3447        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3448        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3449        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3450        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3451        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3452        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3453        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3454        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3455        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3456        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3457        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3458        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3459        SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3460        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3461        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3462        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3463        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3464        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3465};
3466
3467static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3468{
3469        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3470        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3471        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3472        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3473        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3474        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3475        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3476        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3477        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3478        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3479        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3480        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3481        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3482        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3483        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3484        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3485        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3486        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3487        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3488        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3489        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3490        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3491        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3492        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3493        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3494        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3495        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3496        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3497        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3498        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3499        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3500        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3501        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3502        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3503        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3504        SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3505};
3506
3507static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3508        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3509        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3510        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3511        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3512        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3513        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3514        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3515        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3516        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3517        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3518        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3519        SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3520        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3521        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3522        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3523        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3524        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3525        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3526        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3527        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3528        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3529        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3530        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3531        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3532        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3533        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3534        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3535        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3536        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3537        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3538        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3539        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3540};
3541
3542static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3543        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3544        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3545        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3546        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3547        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3548        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3549        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3550        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3551        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3552        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3553        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3554        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3555        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3556        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3557        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3558        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3559        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3560        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3561        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3562        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3563        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3564        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3565        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3566        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3567        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3568        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3569        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3570        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3571        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3572        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3573        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3574        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3575        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3576        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3577};
3578
3579#define DEFAULT_SH_MEM_CONFIG \
3580        ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3581         (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3582         (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3583         (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3584
3585/* TODO: pending on golden setting value of gb address config */
3586#define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3587
3588static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3589static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3590static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3591static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3592static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3593                                 struct amdgpu_cu_info *cu_info);
3594static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3595static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3596                                   u32 sh_num, u32 instance);
3597static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3598
3599static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3600static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3601static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3602static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3603static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3604static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3605static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3606static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3607static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3608static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3609
3610static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3611{
3612        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3613        amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3614                          PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3615        amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3616        amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3617        amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3618        amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3619        amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3620        amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3621}
3622
3623static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3624                                 struct amdgpu_ring *ring)
3625{
3626        struct amdgpu_device *adev = kiq_ring->adev;
3627        uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3628        uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3629        uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3630
3631        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3632        /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3633        amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3634                          PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3635                          PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3636                          PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3637                          PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3638                          PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3639                          PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3640                          PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3641                          PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3642                          PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3643        amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3644        amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3645        amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3646        amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3647        amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3648}
3649
3650static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3651                                   struct amdgpu_ring *ring,
3652                                   enum amdgpu_unmap_queues_action action,
3653                                   u64 gpu_addr, u64 seq)
3654{
3655        uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3656
3657        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3658        amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3659                          PACKET3_UNMAP_QUEUES_ACTION(action) |
3660                          PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3661                          PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3662                          PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3663        amdgpu_ring_write(kiq_ring,
3664                  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3665
3666        if (action == PREEMPT_QUEUES_NO_UNMAP) {
3667                amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3668                amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3669                amdgpu_ring_write(kiq_ring, seq);
3670        } else {
3671                amdgpu_ring_write(kiq_ring, 0);
3672                amdgpu_ring_write(kiq_ring, 0);
3673                amdgpu_ring_write(kiq_ring, 0);
3674        }
3675}
3676
3677static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3678                                   struct amdgpu_ring *ring,
3679                                   u64 addr,
3680                                   u64 seq)
3681{
3682        uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3683
3684        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3685        amdgpu_ring_write(kiq_ring,
3686                          PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3687                          PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3688                          PACKET3_QUERY_STATUS_COMMAND(2));
3689        amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3690                          PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3691                          PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3692        amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3693        amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3694        amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3695        amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3696}
3697
3698static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3699                                uint16_t pasid, uint32_t flush_type,
3700                                bool all_hub)
3701{
3702        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3703        amdgpu_ring_write(kiq_ring,
3704                        PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3705                        PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3706                        PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3707                        PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3708}
3709
3710static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3711        .kiq_set_resources = gfx10_kiq_set_resources,
3712        .kiq_map_queues = gfx10_kiq_map_queues,
3713        .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3714        .kiq_query_status = gfx10_kiq_query_status,
3715        .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3716        .set_resources_size = 8,
3717        .map_queues_size = 7,
3718        .unmap_queues_size = 6,
3719        .query_status_size = 7,
3720        .invalidate_tlbs_size = 2,
3721};
3722
3723static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3724{
3725        adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3726}
3727
3728static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3729{
3730        switch (adev->asic_type) {
3731        case CHIP_NAVI10:
3732                soc15_program_register_sequence(adev,
3733                                                golden_settings_gc_rlc_spm_10_0_nv10,
3734                                                (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3735                break;
3736        case CHIP_NAVI14:
3737                soc15_program_register_sequence(adev,
3738                                                golden_settings_gc_rlc_spm_10_1_nv14,
3739                                                (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3740                break;
3741        case CHIP_NAVI12:
3742                soc15_program_register_sequence(adev,
3743                                                golden_settings_gc_rlc_spm_10_1_2_nv12,
3744                                                (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3745                break;
3746        default:
3747                break;
3748        }
3749}
3750
3751static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3752{
3753        switch (adev->asic_type) {
3754        case CHIP_NAVI10:
3755                soc15_program_register_sequence(adev,
3756                                                golden_settings_gc_10_1,
3757                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3758                soc15_program_register_sequence(adev,
3759                                                golden_settings_gc_10_0_nv10,
3760                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3761                break;
3762        case CHIP_NAVI14:
3763                soc15_program_register_sequence(adev,
3764                                                golden_settings_gc_10_1_1,
3765                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3766                soc15_program_register_sequence(adev,
3767                                                golden_settings_gc_10_1_nv14,
3768                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3769                break;
3770        case CHIP_NAVI12:
3771                soc15_program_register_sequence(adev,
3772                                                golden_settings_gc_10_1_2,
3773                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3774                soc15_program_register_sequence(adev,
3775                                                golden_settings_gc_10_1_2_nv12,
3776                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3777                break;
3778        case CHIP_SIENNA_CICHLID:
3779                soc15_program_register_sequence(adev,
3780                                                golden_settings_gc_10_3,
3781                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3782                soc15_program_register_sequence(adev,
3783                                                golden_settings_gc_10_3_sienna_cichlid,
3784                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3785                break;
3786        case CHIP_NAVY_FLOUNDER:
3787                soc15_program_register_sequence(adev,
3788                                                golden_settings_gc_10_3_2,
3789                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3790                break;
3791        case CHIP_VANGOGH:
3792                soc15_program_register_sequence(adev,
3793                                                golden_settings_gc_10_3_vangogh,
3794                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3795                break;
3796        case CHIP_YELLOW_CARP:
3797                soc15_program_register_sequence(adev,
3798                                                golden_settings_gc_10_3_3,
3799                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3800                break;
3801        case CHIP_DIMGREY_CAVEFISH:
3802                soc15_program_register_sequence(adev,
3803                                                golden_settings_gc_10_3_4,
3804                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3805                break;
3806        case CHIP_BEIGE_GOBY:
3807                soc15_program_register_sequence(adev,
3808                                                golden_settings_gc_10_3_5,
3809                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3810                break;
3811        case CHIP_CYAN_SKILLFISH:
3812                soc15_program_register_sequence(adev,
3813                                                golden_settings_gc_10_0,
3814                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_0));
3815                soc15_program_register_sequence(adev,
3816                                                golden_settings_gc_10_0_cyan_skillfish,
3817                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3818                break;
3819        default:
3820                break;
3821        }
3822        gfx_v10_0_init_spm_golden_registers(adev);
3823}
3824
3825static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3826{
3827        adev->gfx.scratch.num_reg = 8;
3828        adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3829        adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3830}
3831
3832static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3833                                       bool wc, uint32_t reg, uint32_t val)
3834{
3835        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3836        amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3837                          WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3838        amdgpu_ring_write(ring, reg);
3839        amdgpu_ring_write(ring, 0);
3840        amdgpu_ring_write(ring, val);
3841}
3842
3843static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3844                                  int mem_space, int opt, uint32_t addr0,
3845                                  uint32_t addr1, uint32_t ref, uint32_t mask,
3846                                  uint32_t inv)
3847{
3848        amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3849        amdgpu_ring_write(ring,
3850                          /* memory (1) or register (0) */
3851                          (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3852                           WAIT_REG_MEM_OPERATION(opt) | /* wait */
3853                           WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3854                           WAIT_REG_MEM_ENGINE(eng_sel)));
3855
3856        if (mem_space)
3857                BUG_ON(addr0 & 0x3); /* Dword align */
3858        amdgpu_ring_write(ring, addr0);
3859        amdgpu_ring_write(ring, addr1);
3860        amdgpu_ring_write(ring, ref);
3861        amdgpu_ring_write(ring, mask);
3862        amdgpu_ring_write(ring, inv); /* poll interval */
3863}
3864
3865static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3866{
3867        struct amdgpu_device *adev = ring->adev;
3868        uint32_t scratch;
3869        uint32_t tmp = 0;
3870        unsigned i;
3871        int r;
3872
3873        r = amdgpu_gfx_scratch_get(adev, &scratch);
3874        if (r) {
3875                DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3876                return r;
3877        }
3878
3879        WREG32(scratch, 0xCAFEDEAD);
3880
3881        r = amdgpu_ring_alloc(ring, 3);
3882        if (r) {
3883                DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3884                          ring->idx, r);
3885                amdgpu_gfx_scratch_free(adev, scratch);
3886                return r;
3887        }
3888
3889        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3890        amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3891        amdgpu_ring_write(ring, 0xDEADBEEF);
3892        amdgpu_ring_commit(ring);
3893
3894        for (i = 0; i < adev->usec_timeout; i++) {
3895                tmp = RREG32(scratch);
3896                if (tmp == 0xDEADBEEF)
3897                        break;
3898                if (amdgpu_emu_mode == 1)
3899                        msleep(1);
3900                else
3901                        udelay(1);
3902        }
3903
3904        if (i >= adev->usec_timeout)
3905                r = -ETIMEDOUT;
3906
3907        amdgpu_gfx_scratch_free(adev, scratch);
3908
3909        return r;
3910}
3911
3912static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3913{
3914        struct amdgpu_device *adev = ring->adev;
3915        struct amdgpu_ib ib;
3916        struct dma_fence *f = NULL;
3917        unsigned index;
3918        uint64_t gpu_addr;
3919        uint32_t tmp;
3920        long r;
3921
3922        r = amdgpu_device_wb_get(adev, &index);
3923        if (r)
3924                return r;
3925
3926        gpu_addr = adev->wb.gpu_addr + (index * 4);
3927        adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3928        memset(&ib, 0, sizeof(ib));
3929        r = amdgpu_ib_get(adev, NULL, 16,
3930                                        AMDGPU_IB_POOL_DIRECT, &ib);
3931        if (r)
3932                goto err1;
3933
3934        ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3935        ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3936        ib.ptr[2] = lower_32_bits(gpu_addr);
3937        ib.ptr[3] = upper_32_bits(gpu_addr);
3938        ib.ptr[4] = 0xDEADBEEF;
3939        ib.length_dw = 5;
3940
3941        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3942        if (r)
3943                goto err2;
3944
3945        r = dma_fence_wait_timeout(f, false, timeout);
3946        if (r == 0) {
3947                r = -ETIMEDOUT;
3948                goto err2;
3949        } else if (r < 0) {
3950                goto err2;
3951        }
3952
3953        tmp = adev->wb.wb[index];
3954        if (tmp == 0xDEADBEEF)
3955                r = 0;
3956        else
3957                r = -EINVAL;
3958err2:
3959        amdgpu_ib_free(adev, &ib, NULL);
3960        dma_fence_put(f);
3961err1:
3962        amdgpu_device_wb_free(adev, index);
3963        return r;
3964}
3965
3966static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3967{
3968        release_firmware(adev->gfx.pfp_fw);
3969        adev->gfx.pfp_fw = NULL;
3970        release_firmware(adev->gfx.me_fw);
3971        adev->gfx.me_fw = NULL;
3972        release_firmware(adev->gfx.ce_fw);
3973        adev->gfx.ce_fw = NULL;
3974        release_firmware(adev->gfx.rlc_fw);
3975        adev->gfx.rlc_fw = NULL;
3976        release_firmware(adev->gfx.mec_fw);
3977        adev->gfx.mec_fw = NULL;
3978        release_firmware(adev->gfx.mec2_fw);
3979        adev->gfx.mec2_fw = NULL;
3980
3981        kfree(adev->gfx.rlc.register_list_format);
3982}
3983
3984static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3985{
3986        adev->gfx.cp_fw_write_wait = false;
3987
3988        switch (adev->asic_type) {
3989        case CHIP_NAVI10:
3990        case CHIP_NAVI12:
3991        case CHIP_NAVI14:
3992        case CHIP_CYAN_SKILLFISH:
3993                if ((adev->gfx.me_fw_version >= 0x00000046) &&
3994                    (adev->gfx.me_feature_version >= 27) &&
3995                    (adev->gfx.pfp_fw_version >= 0x00000068) &&
3996                    (adev->gfx.pfp_feature_version >= 27) &&
3997                    (adev->gfx.mec_fw_version >= 0x0000005b) &&
3998                    (adev->gfx.mec_feature_version >= 27))
3999                        adev->gfx.cp_fw_write_wait = true;
4000                break;

4001        case CHIP_SIENNA_CICHLID:
4002        case CHIP_NAVY_FLOUNDER:
4003        case CHIP_VANGOGH:
4004        case CHIP_DIMGREY_CAVEFISH:
4005        case CHIP_BEIGE_GOBY:
4006        case CHIP_YELLOW_CARP:
4007                adev->gfx.cp_fw_write_wait = true;
4008                break;
4009        default:
4010                break;
4011        }
4012
4013        if (!adev->gfx.cp_fw_write_wait)
4014                DRM_WARN_ONCE("CP firmware version too old, please update!");
4015}
4016
4017
4018static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
4019{
4020        const struct rlc_firmware_header_v2_1 *rlc_hdr;
4021
4022        rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
4023        adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
4024        adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
4025        adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
4026        adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
4027        adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
4028        adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
4029        adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
4030        adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
4031        adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
4032        adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
4033        adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
4034        adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
4035        adev->gfx.rlc.reg_list_format_direct_reg_list_length =
4036                        le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
4037}
4038
4039static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
4040{
4041        const struct rlc_firmware_header_v2_2 *rlc_hdr;
4042
4043        rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
4044        adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
4045        adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
4046        adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
4047        adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
4048}
4049
4050static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4051{
4052        bool ret = false;
4053
4054        switch (adev->pdev->revision) {
4055        case 0xc2:
4056        case 0xc3:
4057                ret = true;
4058                break;
4059        default:
4060                ret = false;
4061                break;
4062        }
4063
4064        return ret ;
4065}
4066
4067static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4068{
4069        switch (adev->asic_type) {
4070        case CHIP_NAVI10:
4071                if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4072                        adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4073                break;
4074        default:
4075                break;
4076        }
4077}
4078
4079static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4080{
4081        const char *chip_name;
4082        char fw_name[40];
4083        char *wks = "";
4084        int err;
4085        struct amdgpu_firmware_info *info = NULL;
4086        const struct common_firmware_header *header = NULL;
4087        const struct gfx_firmware_header_v1_0 *cp_hdr;
4088        const struct rlc_firmware_header_v2_0 *rlc_hdr;
4089        unsigned int *tmp = NULL;
4090        unsigned int i = 0;
4091        uint16_t version_major;
4092        uint16_t version_minor;
4093
4094        DRM_DEBUG("\n");
4095
4096        switch (adev->asic_type) {
4097        case CHIP_NAVI10:
4098                chip_name = "navi10";
4099                break;
4100        case CHIP_NAVI14:
4101                chip_name = "navi14";
4102                if (!(adev->pdev->device == 0x7340 &&
4103                      adev->pdev->revision != 0x00))
4104                        wks = "_wks";
4105                break;
4106        case CHIP_NAVI12:
4107                chip_name = "navi12";
4108                break;
4109        case CHIP_SIENNA_CICHLID:
4110                chip_name = "sienna_cichlid";
4111                break;
4112        case CHIP_NAVY_FLOUNDER:
4113                chip_name = "navy_flounder";
4114                break;
4115        case CHIP_VANGOGH:
4116                chip_name = "vangogh";
4117                break;
4118        case CHIP_DIMGREY_CAVEFISH:
4119                chip_name = "dimgrey_cavefish";
4120                break;
4121        case CHIP_BEIGE_GOBY:
4122                chip_name = "beige_goby";
4123                break;
4124        case CHIP_YELLOW_CARP:
4125                chip_name = "yellow_carp";
4126                break;
4127        case CHIP_CYAN_SKILLFISH:
4128                if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
4129                        chip_name = "cyan_skillfish2";
4130                else
4131                        chip_name = "cyan_skillfish";
4132                break;
4133        default:
4134                BUG();
4135        }
4136
4137        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4138        err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4139        if (err)
4140                goto out;
4141        err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4142        if (err)
4143                goto out;
4144        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4145        adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4146        adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4147
4148        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4149        err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4150        if (err)
4151                goto out;
4152        err = amdgpu_ucode_validate(adev->gfx.me_fw);
4153        if (err)
4154                goto out;
4155        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4156        adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4157        adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4158
4159        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4160        err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4161        if (err)
4162                goto out;
4163        err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4164        if (err)
4165                goto out;
4166        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4167        adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4168        adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4169
4170        if (!amdgpu_sriov_vf(adev)) {
4171                snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4172                err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4173                if (err)
4174                        goto out;
4175                err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4176                rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4177                version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4178                version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4179
4180                adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4181                adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4182                adev->gfx.rlc.save_and_restore_offset =
4183                        le32_to_cpu(rlc_hdr->save_and_restore_offset);
4184                adev->gfx.rlc.clear_state_descriptor_offset =
4185                        le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4186                adev->gfx.rlc.avail_scratch_ram_locations =
4187                        le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4188                adev->gfx.rlc.reg_restore_list_size =
4189                        le32_to_cpu(rlc_hdr->reg_restore_list_size);
4190                adev->gfx.rlc.reg_list_format_start =
4191                        le32_to_cpu(rlc_hdr->reg_list_format_start);
4192                adev->gfx.rlc.reg_list_format_separate_start =
4193                        le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4194                adev->gfx.rlc.starting_offsets_start =
4195                        le32_to_cpu(rlc_hdr->starting_offsets_start);
4196                adev->gfx.rlc.reg_list_format_size_bytes =
4197                        le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4198                adev->gfx.rlc.reg_list_size_bytes =
4199                        le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4200                adev->gfx.rlc.register_list_format =
4201                        kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4202                                        adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4203                if (!adev->gfx.rlc.register_list_format) {
4204                        err = -ENOMEM;
4205                        goto out;
4206                }
4207
4208                tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4209                                                           le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4210                for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4211                        adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4212
4213                adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4214
4215                tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4216                                                           le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4217                for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4218                        adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4219
4220                if (version_major == 2) {
4221                        if (version_minor >= 1)
4222                                gfx_v10_0_init_rlc_ext_microcode(adev);
4223                        if (version_minor == 2)
4224                                gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4225                }
4226        }
4227
4228        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4229        err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4230        if (err)
4231                goto out;
4232        err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4233        if (err)
4234                goto out;
4235        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4236        adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4237        adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4238
4239        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4240        err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4241        if (!err) {
4242                err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4243                if (err)
4244                        goto out;
4245                cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4246                adev->gfx.mec2_fw->data;
4247                adev->gfx.mec2_fw_version =
4248                le32_to_cpu(cp_hdr->header.ucode_version);
4249                adev->gfx.mec2_feature_version =
4250                le32_to_cpu(cp_hdr->ucode_feature_version);
4251        } else {
4252                err = 0;
4253                adev->gfx.mec2_fw = NULL;
4254        }
4255
4256        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4257                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4258                info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4259                info->fw = adev->gfx.pfp_fw;
4260                header = (const struct common_firmware_header *)info->fw->data;
4261                adev->firmware.fw_size +=
4262                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4263
4264                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4265                info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4266                info->fw = adev->gfx.me_fw;
4267                header = (const struct common_firmware_header *)info->fw->data;
4268                adev->firmware.fw_size +=
4269                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4270
4271                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4272                info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4273                info->fw = adev->gfx.ce_fw;
4274                header = (const struct common_firmware_header *)info->fw->data;
4275                adev->firmware.fw_size +=
4276                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4277
4278                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4279                info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4280                info->fw = adev->gfx.rlc_fw;
4281                if (info->fw) {
4282                        header = (const struct common_firmware_header *)info->fw->data;
4283                        adev->firmware.fw_size +=
4284                                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4285                }
4286                if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4287                    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4288                    adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4289                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4290                        info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4291                        info->fw = adev->gfx.rlc_fw;
4292                        adev->firmware.fw_size +=
4293                                ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4294
4295                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4296                        info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4297                        info->fw = adev->gfx.rlc_fw;
4298                        adev->firmware.fw_size +=
4299                                ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4300
4301                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4302                        info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4303                        info->fw = adev->gfx.rlc_fw;
4304                        adev->firmware.fw_size +=
4305                                ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4306
4307                        if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4308                            adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4309                                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4310                                info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4311                                info->fw = adev->gfx.rlc_fw;
4312                                adev->firmware.fw_size +=
4313                                        ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4314
4315                                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4316                                info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4317                                info->fw = adev->gfx.rlc_fw;
4318                                adev->firmware.fw_size +=
4319                                        ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4320                        }
4321                }
4322
4323                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4324                info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4325                info->fw = adev->gfx.mec_fw;
4326                header = (const struct common_firmware_header *)info->fw->data;
4327                cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4328                adev->firmware.fw_size +=
4329                        ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4330                              le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4331
4332                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4333                info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4334                info->fw = adev->gfx.mec_fw;
4335                adev->firmware.fw_size +=
4336                        ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4337
4338                if (adev->gfx.mec2_fw) {
4339                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4340                        info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4341                        info->fw = adev->gfx.mec2_fw;
4342                        header = (const struct common_firmware_header *)info->fw->data;
4343                        cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4344                        adev->firmware.fw_size +=
4345                                ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4346                                      le32_to_cpu(cp_hdr->jt_size) * 4,
4347                                      PAGE_SIZE);
4348                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4349                        info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4350                        info->fw = adev->gfx.mec2_fw;
4351                        adev->firmware.fw_size +=
4352                                ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4353                                      PAGE_SIZE);
4354                }
4355        }
4356
4357        gfx_v10_0_check_fw_write_wait(adev);
4358out:
4359        if (err) {
4360                dev_err(adev->dev,
4361                        "gfx10: Failed to load firmware \"%s\"\n",
4362                        fw_name);
4363                release_firmware(adev->gfx.pfp_fw);
4364                adev->gfx.pfp_fw = NULL;
4365                release_firmware(adev->gfx.me_fw);
4366                adev->gfx.me_fw = NULL;
4367                release_firmware(adev->gfx.ce_fw);
4368                adev->gfx.ce_fw = NULL;
4369                release_firmware(adev->gfx.rlc_fw);
4370                adev->gfx.rlc_fw = NULL;
4371                release_firmware(adev->gfx.mec_fw);
4372                adev->gfx.mec_fw = NULL;
4373                release_firmware(adev->gfx.mec2_fw);
4374                adev->gfx.mec2_fw = NULL;
4375        }
4376
4377        gfx_v10_0_check_gfxoff_flag(adev);
4378
4379        return err;
4380}
4381
4382static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4383{
4384        u32 count = 0;
4385        const struct cs_section_def *sect = NULL;
4386        const struct cs_extent_def *ext = NULL;
4387
4388        /* begin clear state */
4389        count += 2;
4390        /* context control state */
4391        count += 3;
4392
4393        for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4394                for (ext = sect->section; ext->extent != NULL; ++ext) {
4395                        if (sect->id == SECT_CONTEXT)
4396                                count += 2 + ext->reg_count;
4397                        else
4398                                return 0;
4399                }
4400        }
4401
4402        /* set PA_SC_TILE_STEERING_OVERRIDE */
4403        count += 3;
4404        /* end clear state */
4405        count += 2;
4406        /* clear state */
4407        count += 2;
4408
4409        return count;
4410}
4411
4412static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4413                                    volatile u32 *buffer)
4414{
4415        u32 count = 0, i;
4416        const struct cs_section_def *sect = NULL;
4417        const struct cs_extent_def *ext = NULL;
4418        int ctx_reg_offset;
4419
4420        if (adev->gfx.rlc.cs_data == NULL)
4421                return;
4422        if (buffer == NULL)
4423                return;
4424
4425        buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4426        buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4427
4428        buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4429        buffer[count++] = cpu_to_le32(0x80000000);
4430        buffer[count++] = cpu_to_le32(0x80000000);
4431
4432        for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4433                for (ext = sect->section; ext->extent != NULL; ++ext) {
4434                        if (sect->id == SECT_CONTEXT) {
4435                                buffer[count++] =
4436                                        cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4437                                buffer[count++] = cpu_to_le32(ext->reg_index -
4438                                                PACKET3_SET_CONTEXT_REG_START);
4439                                for (i = 0; i < ext->reg_count; i++)
4440                                        buffer[count++] = cpu_to_le32(ext->extent[i]);
4441                        } else {
4442                                return;
4443                        }
4444                }
4445        }
4446
4447        ctx_reg_offset =
4448                SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4449        buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4450        buffer[count++] = cpu_to_le32(ctx_reg_offset);
4451        buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4452
4453        buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4454        buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4455
4456        buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4457        buffer[count++] = cpu_to_le32(0);
4458}
4459
4460static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4461{
4462        /* clear state block */
4463        amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4464                        &adev->gfx.rlc.clear_state_gpu_addr,
4465                        (void **)&adev->gfx.rlc.cs_ptr);
4466
4467        /* jump table block */
4468        amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4469                        &adev->gfx.rlc.cp_table_gpu_addr,
4470                        (void **)&adev->gfx.rlc.cp_table_ptr);
4471}
4472
4473static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4474{
4475        const struct cs_section_def *cs_data;
4476        int r;
4477
4478        adev->gfx.rlc.cs_data = gfx10_cs_data;
4479
4480        cs_data = adev->gfx.rlc.cs_data;
4481
4482        if (cs_data) {
4483                /* init clear state block */
4484                r = amdgpu_gfx_rlc_init_csb(adev);
4485                if (r)
4486                        return r;
4487        }
4488
4489        /* init spm vmid with 0xf */
4490        if (adev->gfx.rlc.funcs->update_spm_vmid)
4491                adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4492
4493        return 0;
4494}
4495
4496static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4497{
4498        amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4499        amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4500}
4501
4502static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4503{
4504        int r;
4505
4506        bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4507
4508        amdgpu_gfx_graphics_queue_acquire(adev);
4509
4510        r = gfx_v10_0_init_microcode(adev);
4511        if (r)
4512                DRM_ERROR("Failed to load gfx firmware!\n");
4513
4514        return r;
4515}
4516
4517static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4518{
4519        int r;
4520        u32 *hpd;
4521        const __le32 *fw_data = NULL;
4522        unsigned fw_size;
4523        u32 *fw = NULL;
4524        size_t mec_hpd_size;
4525
4526        const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4527
4528        bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4529
4530        /* take ownership of the relevant compute queues */
4531        amdgpu_gfx_compute_queue_acquire(adev);
4532        mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4533
4534        if (mec_hpd_size) {
4535                r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4536                                              AMDGPU_GEM_DOMAIN_GTT,
4537                                              &adev->gfx.mec.hpd_eop_obj,
4538                                              &adev->gfx.mec.hpd_eop_gpu_addr,
4539                                              (void **)&hpd);
4540                if (r) {
4541                        dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4542                        gfx_v10_0_mec_fini(adev);
4543                        return r;
4544                }
4545
4546                memset(hpd, 0, mec_hpd_size);
4547
4548                amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4549                amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4550        }
4551
4552        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4553                mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4554
4555                fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4556                         le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4557                fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4558
4559                r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4560                                              PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4561                                              &adev->gfx.mec.mec_fw_obj,
4562                                              &adev->gfx.mec.mec_fw_gpu_addr,
4563                                              (void **)&fw);
4564                if (r) {
4565                        dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4566                        gfx_v10_0_mec_fini(adev);
4567                        return r;
4568                }
4569
4570                memcpy(fw, fw_data, fw_size);
4571
4572                amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4573                amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4574        }
4575
4576        return 0;
4577}
4578
4579static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4580{
4581        WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4582                (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4583                (address << SQ_IND_INDEX__INDEX__SHIFT));
4584        return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4585}
4586
4587static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4588                           uint32_t thread, uint32_t regno,
4589                           uint32_t num, uint32_t *out)
4590{
4591        WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4592                (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4593                (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4594                (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4595                (SQ_IND_INDEX__AUTO_INCR_MASK));
4596        while (num--)
4597                *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4598}
4599
4600static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4601{
4602        /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4603         * field when performing a select_se_sh so it should be
4604         * zero here */
4605        WARN_ON(simd != 0);
4606
4607        /* type 2 wave data */
4608        dst[(*no_fields)++] = 2;
4609        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4610        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4611        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4612        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4613        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4614        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4615        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4616        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4617        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4618        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4619        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4620        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4621        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4622        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4623        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4624        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4625}
4626
4627static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4628                                     uint32_t wave, uint32_t start,
4629                                     uint32_t size, uint32_t *dst)
4630{
4631        WARN_ON(simd != 0);
4632
4633        wave_read_regs(
4634                adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4635                dst);
4636}
4637
4638static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4639                                      uint32_t wave, uint32_t thread,
4640                                      uint32_t start, uint32_t size,
4641                                      uint32_t *dst)
4642{
4643        wave_read_regs(
4644                adev, wave, thread,
4645                start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4646}
4647
4648static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4649                                       u32 me, u32 pipe, u32 q, u32 vm)
4650{
4651        nv_grbm_select(adev, me, pipe, q, vm);
4652}
4653
4654static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4655                                          bool enable)
4656{
4657        uint32_t data, def;
4658
4659        data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4660
4661        if (enable)
4662                data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4663        else
4664                data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4665
4666        if (data != def)
4667                WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4668}
4669
4670static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4671        .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4672        .select_se_sh = &gfx_v10_0_select_se_sh,
4673        .read_wave_data = &gfx_v10_0_read_wave_data,
4674        .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4675        .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4676        .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4677        .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4678        .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4679};
4680
4681static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4682{
4683        u32 gb_addr_config;
4684
4685        adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4686
4687        switch (adev->asic_type) {
4688        case CHIP_NAVI10:
4689        case CHIP_NAVI14:
4690        case CHIP_NAVI12:
4691                adev->gfx.config.max_hw_contexts = 8;
4692                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4693                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4694                adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4695                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4696                gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4697                break;
4698        case CHIP_SIENNA_CICHLID:
4699        case CHIP_NAVY_FLOUNDER:
4700        case CHIP_VANGOGH:
4701        case CHIP_DIMGREY_CAVEFISH:
4702        case CHIP_BEIGE_GOBY:
4703        case CHIP_YELLOW_CARP:
4704                adev->gfx.config.max_hw_contexts = 8;
4705                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4706                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4707                adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4708                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4709                gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4710                adev->gfx.config.gb_addr_config_fields.num_pkrs =
4711                        1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4712                break;
4713        case CHIP_CYAN_SKILLFISH:
4714                adev->gfx.config.max_hw_contexts = 8;
4715                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4716                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4717                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4718                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4719                gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4720                break;
4721        default:
4722                BUG();
4723                break;
4724        }
4725
4726        adev->gfx.config.gb_addr_config = gb_addr_config;
4727
4728        adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4729                        REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4730                                      GB_ADDR_CONFIG, NUM_PIPES);
4731
4732        adev->gfx.config.max_tile_pipes =
4733                adev->gfx.config.gb_addr_config_fields.num_pipes;
4734
4735        adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4736                        REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4737                                      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4738        adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4739                        REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4740                                      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4741        adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4742                        REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4743                                      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4744        adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4745                        REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4746                                      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4747}
4748
4749static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4750                                   int me, int pipe, int queue)
4751{
4752        int r;
4753        struct amdgpu_ring *ring;
4754        unsigned int irq_type;
4755
4756        ring = &adev->gfx.gfx_ring[ring_id];
4757
4758        ring->me = me;
4759        ring->pipe = pipe;
4760        ring->queue = queue;
4761
4762        ring->ring_obj = NULL;
4763        ring->use_doorbell = true;
4764
4765        if (!ring_id)
4766                ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4767        else
4768                ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4769        sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4770
4771        irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4772        r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4773                             AMDGPU_RING_PRIO_DEFAULT, NULL);
4774        if (r)
4775                return r;
4776        return 0;
4777}
4778
4779static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4780                                       int mec, int pipe, int queue)
4781{
4782        int r;
4783        unsigned irq_type;
4784        struct amdgpu_ring *ring;
4785        unsigned int hw_prio;
4786
4787        ring = &adev->gfx.compute_ring[ring_id];
4788
4789        /* mec0 is me1 */
4790        ring->me = mec + 1;
4791        ring->pipe = pipe;
4792        ring->queue = queue;
4793
4794        ring->ring_obj = NULL;
4795        ring->use_doorbell = true;
4796        ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4797        ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4798                                + (ring_id * GFX10_MEC_HPD_SIZE);
4799        sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4800
4801        irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4802                + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4803                + ring->pipe;
4804        hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4805                        AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4806        /* type-2 packets are deprecated on MEC, use type-3 instead */
4807        r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4808                             hw_prio, NULL);
4809        if (r)
4810                return r;
4811
4812        return 0;
4813}
4814
4815static int gfx_v10_0_sw_init(void *handle)
4816{
4817        int i, j, k, r, ring_id = 0;
4818        struct amdgpu_kiq *kiq;
4819        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4820
4821        switch (adev->asic_type) {
4822        case CHIP_NAVI10:
4823        case CHIP_NAVI14:
4824        case CHIP_NAVI12:
4825        case CHIP_CYAN_SKILLFISH:
4826                adev->gfx.me.num_me = 1;
4827                adev->gfx.me.num_pipe_per_me = 1;
4828                adev->gfx.me.num_queue_per_pipe = 1;
4829                adev->gfx.mec.num_mec = 2;
4830                adev->gfx.mec.num_pipe_per_mec = 4;
4831                adev->gfx.mec.num_queue_per_pipe = 8;
4832                break;
4833        case CHIP_SIENNA_CICHLID:
4834        case CHIP_NAVY_FLOUNDER:
4835        case CHIP_VANGOGH:
4836        case CHIP_DIMGREY_CAVEFISH:
4837        case CHIP_BEIGE_GOBY:
4838        case CHIP_YELLOW_CARP:
4839                adev->gfx.me.num_me = 1;
4840                adev->gfx.me.num_pipe_per_me = 1;
4841                adev->gfx.me.num_queue_per_pipe = 1;
4842                adev->gfx.mec.num_mec = 2;
4843                adev->gfx.mec.num_pipe_per_mec = 4;
4844                adev->gfx.mec.num_queue_per_pipe = 4;
4845                break;
4846        default:
4847                adev->gfx.me.num_me = 1;
4848                adev->gfx.me.num_pipe_per_me = 1;
4849                adev->gfx.me.num_queue_per_pipe = 1;
4850                adev->gfx.mec.num_mec = 1;
4851                adev->gfx.mec.num_pipe_per_mec = 4;
4852                adev->gfx.mec.num_queue_per_pipe = 8;
4853                break;
4854        }
4855
4856        /* KIQ event */
4857        r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4858                              GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4859                              &adev->gfx.kiq.irq);
4860        if (r)
4861                return r;
4862
4863        /* EOP Event */
4864        r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4865                              GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4866                              &adev->gfx.eop_irq);
4867        if (r)
4868                return r;
4869
4870        /* Privileged reg */
4871        r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4872                              &adev->gfx.priv_reg_irq);
4873        if (r)
4874                return r;
4875
4876        /* Privileged inst */
4877        r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4878                              &adev->gfx.priv_inst_irq);
4879        if (r)
4880                return r;
4881
4882        adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4883
4884        gfx_v10_0_scratch_init(adev);
4885
4886        r = gfx_v10_0_me_init(adev);
4887        if (r)
4888                return r;
4889
4890        r = gfx_v10_0_rlc_init(adev);
4891        if (r) {
4892                DRM_ERROR("Failed to init rlc BOs!\n");
4893                return r;
4894        }
4895
4896        r = gfx_v10_0_mec_init(adev);
4897        if (r) {
4898                DRM_ERROR("Failed to init MEC BOs!\n");
4899                return r;
4900        }
4901
4902        /* set up the gfx ring */
4903        for (i = 0; i < adev->gfx.me.num_me; i++) {
4904                for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4905                        for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4906                                if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4907                                        continue;
4908
4909                                r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4910                                                            i, k, j);
4911                                if (r)
4912                                        return r;
4913                                ring_id++;
4914                        }
4915                }
4916        }
4917
4918        ring_id = 0;
4919        /* set up the compute queues - allocate horizontally across pipes */
4920        for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4921                for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4922                        for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4923                                if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4924                                                                     j))
4925                                        continue;
4926
4927                                r = gfx_v10_0_compute_ring_init(adev, ring_id,
4928                                                                i, k, j);
4929                                if (r)
4930                                        return r;
4931
4932                                ring_id++;
4933                        }
4934                }
4935        }
4936
4937        r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4938        if (r) {
4939                DRM_ERROR("Failed to init KIQ BOs!\n");
4940                return r;
4941        }
4942
4943        kiq = &adev->gfx.kiq;
4944        r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4945        if (r)
4946                return r;
4947
4948        r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4949        if (r)
4950                return r;
4951
4952        /* allocate visible FB for rlc auto-loading fw */
4953        if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4954                r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4955                if (r)
4956                        return r;
4957        }
4958
4959        adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4960
4961        gfx_v10_0_gpu_early_init(adev);
4962
4963        return 0;
4964}
4965
4966static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4967{
4968        amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4969                              &adev->gfx.pfp.pfp_fw_gpu_addr,
4970                              (void **)&adev->gfx.pfp.pfp_fw_ptr);
4971}
4972
4973static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4974{
4975        amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4976                              &adev->gfx.ce.ce_fw_gpu_addr,
4977                              (void **)&adev->gfx.ce.ce_fw_ptr);
4978}
4979
4980static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4981{
4982        amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4983                              &adev->gfx.me.me_fw_gpu_addr,
4984                              (void **)&adev->gfx.me.me_fw_ptr);
4985}
4986
4987static int gfx_v10_0_sw_fini(void *handle)
4988{
4989        int i;
4990        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4991
4992        for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4993                amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4994        for (i = 0; i < adev->gfx.num_compute_rings; i++)
4995                amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4996
4997        amdgpu_gfx_mqd_sw_fini(adev);
4998        amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4999        amdgpu_gfx_kiq_fini(adev);
5000

5001        gfx_v10_0_pfp_fini(adev);
5002        gfx_v10_0_ce_fini(adev);
5003        gfx_v10_0_me_fini(adev);
5004        gfx_v10_0_rlc_fini(adev);
5005        gfx_v10_0_mec_fini(adev);
5006
5007        if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5008                gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5009
5010        gfx_v10_0_free_microcode(adev);
5011
5012        return 0;
5013}
5014
5015static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5016                                   u32 sh_num, u32 instance)
5017{
5018        u32 data;
5019
5020        if (instance == 0xffffffff)
5021                data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5022                                     INSTANCE_BROADCAST_WRITES, 1);
5023        else
5024                data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5025                                     instance);
5026
5027        if (se_num == 0xffffffff)
5028                data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5029                                     1);
5030        else
5031                data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5032
5033        if (sh_num == 0xffffffff)
5034                data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5035                                     1);
5036        else
5037                data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5038
5039        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5040}
5041
5042static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5043{
5044        u32 data, mask;
5045
5046        data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5047        data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5048
5049        data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5050        data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5051
5052        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5053                                         adev->gfx.config.max_sh_per_se);
5054
5055        return (~data) & mask;
5056}
5057
5058static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5059{
5060        int i, j;
5061        u32 data;
5062        u32 active_rbs = 0;
5063        u32 bitmap;
5064        u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5065                                        adev->gfx.config.max_sh_per_se;
5066
5067        mutex_lock(&adev->grbm_idx_mutex);
5068        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5069                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5070                        bitmap = i * adev->gfx.config.max_sh_per_se + j;
5071                        if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
5072                                (adev->asic_type == CHIP_YELLOW_CARP)) &&
5073                            ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5074                                continue;
5075                        gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5076                        data = gfx_v10_0_get_rb_active_bitmap(adev);
5077                        active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5078                                               rb_bitmap_width_per_sh);
5079                }
5080        }
5081        gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5082        mutex_unlock(&adev->grbm_idx_mutex);
5083
5084        adev->gfx.config.backend_enable_mask = active_rbs;
5085        adev->gfx.config.num_rbs = hweight32(active_rbs);
5086}
5087
5088static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5089{
5090        uint32_t num_sc;
5091        uint32_t enabled_rb_per_sh;
5092        uint32_t active_rb_bitmap;
5093        uint32_t num_rb_per_sc;
5094        uint32_t num_packer_per_sc;
5095        uint32_t pa_sc_tile_steering_override;
5096
5097        /* for ASICs that integrates GFX v10.3
5098         * pa_sc_tile_steering_override should be set to 0 */
5099        if (adev->asic_type >= CHIP_SIENNA_CICHLID)
5100                return 0;
5101
5102        /* init num_sc */
5103        num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5104                        adev->gfx.config.num_sc_per_sh;
5105        /* init num_rb_per_sc */
5106        active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5107        enabled_rb_per_sh = hweight32(active_rb_bitmap);
5108        num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5109        /* init num_packer_per_sc */
5110        num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5111
5112        pa_sc_tile_steering_override = 0;
5113        pa_sc_tile_steering_override |=
5114                (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5115                PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5116        pa_sc_tile_steering_override |=
5117                (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5118                PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5119        pa_sc_tile_steering_override |=
5120                (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5121                PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5122
5123        return pa_sc_tile_steering_override;
5124}
5125
5126#define DEFAULT_SH_MEM_BASES    (0x6000)
5127
5128static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5129{
5130        int i;
5131        uint32_t sh_mem_bases;
5132
5133        /*
5134         * Configure apertures:
5135         * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5136         * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5137         * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5138         */
5139        sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5140
5141        mutex_lock(&adev->srbm_mutex);
5142        for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5143                nv_grbm_select(adev, 0, 0, 0, i);
5144                /* CP and shaders */
5145                WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5146                WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5147        }
5148        nv_grbm_select(adev, 0, 0, 0, 0);
5149        mutex_unlock(&adev->srbm_mutex);
5150
5151        /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5152           acccess. These should be enabled by FW for target VMIDs. */
5153        for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5154                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5155                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5156                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5157                WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5158        }
5159}
5160
5161static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5162{
5163        int vmid;
5164
5165        /*
5166         * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5167         * access. Compute VMIDs should be enabled by FW for target VMIDs,
5168         * the driver can enable them for graphics. VMID0 should maintain
5169         * access so that HWS firmware can save/restore entries.
5170         */
5171        for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5172                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5173                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5174                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5175                WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5176        }
5177}
5178
5179
5180static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5181{
5182        int i, j, k;
5183        int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5184        u32 tmp, wgp_active_bitmap = 0;
5185        u32 gcrd_targets_disable_tcp = 0;
5186        u32 utcl_invreq_disable = 0;
5187        /*
5188         * GCRD_TARGETS_DISABLE field contains
5189         * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5190         * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5191         */
5192        u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5193                2 * max_wgp_per_sh + /* TCP */
5194                max_wgp_per_sh + /* SQC */
5195                4); /* GL1C */
5196        /*
5197         * UTCL1_UTCL0_INVREQ_DISABLE field contains
5198         * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5199         * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5200         */
5201        u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5202                2 * max_wgp_per_sh + /* TCP */
5203                2 * max_wgp_per_sh + /* SQC */
5204                4 + /* RMI */
5205                1); /* SQG */
5206
5207        mutex_lock(&adev->grbm_idx_mutex);
5208        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5209                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5210                        gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5211                        wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5212                        /*
5213                         * Set corresponding TCP bits for the inactive WGPs in
5214                         * GCRD_SA_TARGETS_DISABLE
5215                         */
5216                        gcrd_targets_disable_tcp = 0;
5217                        /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5218                        utcl_invreq_disable = 0;
5219
5220                        for (k = 0; k < max_wgp_per_sh; k++) {
5221                                if (!(wgp_active_bitmap & (1 << k))) {
5222                                        gcrd_targets_disable_tcp |= 3 << (2 * k);
5223                                        gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5224                                        utcl_invreq_disable |= (3 << (2 * k)) |
5225                                                (3 << (2 * (max_wgp_per_sh + k)));
5226                                }
5227                        }
5228
5229                        tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5230                        /* only override TCP & SQC bits */
5231                        tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5232                        tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5233                        WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5234
5235                        tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5236                        /* only override TCP & SQC bits */
5237                        tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5238                        tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5239                        WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5240                }
5241        }
5242
5243        gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5244        mutex_unlock(&adev->grbm_idx_mutex);
5245}
5246
5247static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5248{
5249        /* TCCs are global (not instanced). */
5250        uint32_t tcc_disable;
5251
5252        if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5253                tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5254                              RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5255        } else {
5256                tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5257                              RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5258        }
5259
5260        adev->gfx.config.tcc_disabled_mask =
5261                REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5262                (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5263}
5264
5265static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5266{
5267        u32 tmp;
5268        int i;
5269
5270        WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5271
5272        gfx_v10_0_setup_rb(adev);
5273        gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5274        gfx_v10_0_get_tcc_info(adev);
5275        adev->gfx.config.pa_sc_tile_steering_override =
5276                gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5277
5278        /* XXX SH_MEM regs */
5279        /* where to put LDS, scratch, GPUVM in FSA64 space */
5280        mutex_lock(&adev->srbm_mutex);
5281        for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5282                nv_grbm_select(adev, 0, 0, 0, i);
5283                /* CP and shaders */
5284                WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5285                if (i != 0) {
5286                        tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5287                                (adev->gmc.private_aperture_start >> 48));
5288                        tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5289                                (adev->gmc.shared_aperture_start >> 48));
5290                        WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5291                }
5292        }
5293        nv_grbm_select(adev, 0, 0, 0, 0);
5294
5295        mutex_unlock(&adev->srbm_mutex);
5296
5297        gfx_v10_0_init_compute_vmid(adev);
5298        gfx_v10_0_init_gds_vmid(adev);
5299
5300}
5301
5302static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5303                                               bool enable)
5304{
5305        u32 tmp;
5306
5307        if (amdgpu_sriov_vf(adev))
5308                return;
5309
5310        tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5311
5312        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5313                            enable ? 1 : 0);
5314        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5315                            enable ? 1 : 0);
5316        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5317                            enable ? 1 : 0);
5318        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5319                            enable ? 1 : 0);
5320
5321        WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5322}
5323
5324static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5325{
5326        adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5327
5328        /* csib */
5329        if (adev->asic_type == CHIP_NAVI12) {
5330                WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5331                                adev->gfx.rlc.clear_state_gpu_addr >> 32);
5332                WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5333                                adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5334                WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5335        } else {
5336                WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5337                                adev->gfx.rlc.clear_state_gpu_addr >> 32);
5338                WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5339                                adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5340                WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5341        }
5342        return 0;
5343}
5344
5345static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5346{
5347        u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5348
5349        tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5350        WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5351}
5352
5353static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5354{
5355        WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5356        udelay(50);
5357        WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5358        udelay(50);
5359}
5360
5361static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5362                                             bool enable)
5363{
5364        uint32_t rlc_pg_cntl;
5365
5366        rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5367
5368        if (!enable) {
5369                /* RLC_PG_CNTL[23] = 0 (default)
5370                 * RLC will wait for handshake acks with SMU
5371                 * GFXOFF will be enabled
5372                 * RLC_PG_CNTL[23] = 1
5373                 * RLC will not issue any message to SMU
5374                 * hence no handshake between SMU & RLC
5375                 * GFXOFF will be disabled
5376                 */
5377                rlc_pg_cntl |= 0x800000;
5378        } else
5379                rlc_pg_cntl &= ~0x800000;
5380        WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5381}
5382
5383static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5384{
5385        /* TODO: enable rlc & smu handshake until smu
5386         * and gfxoff feature works as expected */
5387        if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5388                gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5389
5390        WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5391        udelay(50);
5392}
5393
5394static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5395{
5396        uint32_t tmp;
5397
5398        /* enable Save Restore Machine */
5399        tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5400        tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5401        tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5402        WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5403}
5404
5405static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5406{
5407        const struct rlc_firmware_header_v2_0 *hdr;
5408        const __le32 *fw_data;
5409        unsigned i, fw_size;
5410
5411        if (!adev->gfx.rlc_fw)
5412                return -EINVAL;
5413
5414        hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5415        amdgpu_ucode_print_rlc_hdr(&hdr->header);
5416
5417        fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5418                           le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5419        fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5420
5421        WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5422                     RLCG_UCODE_LOADING_START_ADDRESS);
5423
5424        for (i = 0; i < fw_size; i++)
5425                WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5426                             le32_to_cpup(fw_data++));
5427
5428        WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5429
5430        return 0;
5431}
5432
5433static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5434{
5435        int r;
5436
5437        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5438                adev->psp.autoload_supported) {
5439
5440                r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5441                if (r)
5442                        return r;
5443
5444                gfx_v10_0_init_csb(adev);
5445
5446                if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5447                        gfx_v10_0_rlc_enable_srm(adev);
5448        } else {
5449                if (amdgpu_sriov_vf(adev)) {
5450                        gfx_v10_0_init_csb(adev);
5451                        return 0;
5452                }
5453
5454                adev->gfx.rlc.funcs->stop(adev);
5455
5456                /* disable CG */
5457                WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5458
5459                /* disable PG */
5460                WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5461
5462                if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5463                        /* legacy rlc firmware loading */
5464                        r = gfx_v10_0_rlc_load_microcode(adev);
5465                        if (r)
5466                                return r;
5467                } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5468                        /* rlc backdoor autoload firmware */
5469                        r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5470                        if (r)
5471                                return r;
5472                }
5473
5474                gfx_v10_0_init_csb(adev);
5475
5476                adev->gfx.rlc.funcs->start(adev);
5477
5478                if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5479                        r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5480                        if (r)
5481                                return r;
5482                }
5483        }
5484        return 0;
5485}
5486
5487static struct {
5488        FIRMWARE_ID     id;
5489        unsigned int    offset;
5490        unsigned int    size;
5491} rlc_autoload_info[FIRMWARE_ID_MAX];
5492
5493static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5494{
5495        int ret;
5496        RLC_TABLE_OF_CONTENT *rlc_toc;
5497
5498        ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5499                                        AMDGPU_GEM_DOMAIN_GTT,
5500                                        &adev->gfx.rlc.rlc_toc_bo,
5501                                        &adev->gfx.rlc.rlc_toc_gpu_addr,
5502                                        (void **)&adev->gfx.rlc.rlc_toc_buf);
5503        if (ret) {
5504                dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5505                return ret;
5506        }
5507
5508        /* Copy toc from psp sos fw to rlc toc buffer */
5509        memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5510
5511        rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5512        while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5513                (rlc_toc->id < FIRMWARE_ID_MAX)) {
5514                if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5515                    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5516                        /* Offset needs 4KB alignment */
5517                        rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5518                }
5519
5520                rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5521                rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5522                rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5523
5524                rlc_toc++;
5525        }
5526
5527        return 0;
5528}
5529
5530static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5531{
5532        uint32_t total_size = 0;
5533        FIRMWARE_ID id;
5534        int ret;
5535
5536        ret = gfx_v10_0_parse_rlc_toc(adev);
5537        if (ret) {
5538                dev_err(adev->dev, "failed to parse rlc toc\n");
5539                return 0;
5540        }
5541
5542        for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5543                total_size += rlc_autoload_info[id].size;
5544
5545        /* In case the offset in rlc toc ucode is aligned */
5546        if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5547                total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5548                                rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5549
5550        return total_size;
5551}
5552
5553static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5554{
5555        int r;
5556        uint32_t total_size;
5557
5558        total_size = gfx_v10_0_calc_toc_total_size(adev);
5559
5560        r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5561                                      AMDGPU_GEM_DOMAIN_GTT,
5562                                      &adev->gfx.rlc.rlc_autoload_bo,
5563                                      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5564                                      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5565        if (r) {
5566                dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5567                return r;
5568        }
5569
5570        return 0;
5571}
5572
5573static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5574{
5575        amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5576                              &adev->gfx.rlc.rlc_toc_gpu_addr,
5577                              (void **)&adev->gfx.rlc.rlc_toc_buf);
5578        amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5579                              &adev->gfx.rlc.rlc_autoload_gpu_addr,
5580                              (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5581}
5582
5583static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5584                                                       FIRMWARE_ID id,
5585                                                       const void *fw_data,
5586                                                       uint32_t fw_size)
5587{
5588        uint32_t toc_offset;
5589        uint32_t toc_fw_size;
5590        char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5591
5592        if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5593                return;
5594
5595        toc_offset = rlc_autoload_info[id].offset;
5596        toc_fw_size = rlc_autoload_info[id].size;
5597
5598        if (fw_size == 0)
5599                fw_size = toc_fw_size;
5600
5601        if (fw_size > toc_fw_size)
5602                fw_size = toc_fw_size;
5603
5604        memcpy(ptr + toc_offset, fw_data, fw_size);
5605
5606        if (fw_size < toc_fw_size)
5607                memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5608}
5609
5610static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5611{
5612        void *data;
5613        uint32_t size;
5614
5615        data = adev->gfx.rlc.rlc_toc_buf;
5616        size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5617
5618        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5619                                                   FIRMWARE_ID_RLC_TOC,
5620                                                   data, size);
5621}
5622
5623static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5624{
5625        const __le32 *fw_data;
5626        uint32_t fw_size;
5627        const struct gfx_firmware_header_v1_0 *cp_hdr;
5628        const struct rlc_firmware_header_v2_0 *rlc_hdr;
5629
5630        /* pfp ucode */
5631        cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5632                adev->gfx.pfp_fw->data;
5633        fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5634                le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5635        fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5636        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5637                                                   FIRMWARE_ID_CP_PFP,
5638                                                   fw_data, fw_size);
5639
5640        /* ce ucode */
5641        cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5642                adev->gfx.ce_fw->data;
5643        fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5644                le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5645        fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5646        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5647                                                   FIRMWARE_ID_CP_CE,
5648                                                   fw_data, fw_size);
5649
5650        /* me ucode */
5651        cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5652                adev->gfx.me_fw->data;
5653        fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5654                le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5655        fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5656        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5657                                                   FIRMWARE_ID_CP_ME,
5658                                                   fw_data, fw_size);
5659
5660        /* rlc ucode */
5661        rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5662                adev->gfx.rlc_fw->data;
5663        fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5664                le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5665        fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5666        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5667                                                   FIRMWARE_ID_RLC_G_UCODE,
5668                                                   fw_data, fw_size);
5669
5670        /* mec1 ucode */
5671        cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5672                adev->gfx.mec_fw->data;
5673        fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5674                le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5675        fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5676                cp_hdr->jt_size * 4;
5677        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5678                                                   FIRMWARE_ID_CP_MEC,
5679                                                   fw_data, fw_size);
5680        /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5681}
5682
5683/* Temporarily put sdma part here */
5684static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5685{
5686        const __le32 *fw_data;
5687        uint32_t fw_size;
5688        const struct sdma_firmware_header_v1_0 *sdma_hdr;
5689        int i;
5690
5691        for (i = 0; i < adev->sdma.num_instances; i++) {
5692                sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5693                        adev->sdma.instance[i].fw->data;
5694                fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5695                        le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5696                fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5697
5698                if (i == 0) {
5699                        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5700                                FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5701                        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5702                                FIRMWARE_ID_SDMA0_JT,
5703                                (uint32_t *)fw_data +
5704                                sdma_hdr->jt_offset,
5705                                sdma_hdr->jt_size * 4);
5706                } else if (i == 1) {
5707                        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5708                                FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5709                        gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5710                                FIRMWARE_ID_SDMA1_JT,
5711                                (uint32_t *)fw_data +
5712                                sdma_hdr->jt_offset,
5713                                sdma_hdr->jt_size * 4);
5714                }
5715        }
5716}
5717
5718static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5719{
5720        uint32_t rlc_g_offset, rlc_g_size, tmp;
5721        uint64_t gpu_addr;
5722
5723        gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5724        gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5725        gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5726
5727        rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5728        rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5729        gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5730
5731        WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5732        WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5733        WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5734
5735        tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5736        if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5737                   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5738                DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5739                return -EINVAL;
5740        }
5741
5742        tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5743        if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5744                DRM_ERROR("RLC ROM should halt itself\n");
5745                return -EINVAL;
5746        }
5747
5748        return 0;
5749}
5750
5751static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5752{
5753        uint32_t usec_timeout = 50000;  /* wait for 50ms */
5754        uint32_t tmp;
5755        int i;
5756        uint64_t addr;
5757
5758        /* Trigger an invalidation of the L1 instruction caches */
5759        tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5760        tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5761        WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5762
5763        /* Wait for invalidation complete */
5764        for (i = 0; i < usec_timeout; i++) {
5765                tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5766                if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5767                        INVALIDATE_CACHE_COMPLETE))
5768                        break;
5769                udelay(1);
5770        }
5771
5772        if (i >= usec_timeout) {
5773                dev_err(adev->dev, "failed to invalidate instruction cache\n");
5774                return -EINVAL;
5775        }
5776
5777        /* Program me ucode address into intruction cache address register */
5778        addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5779                rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5780        WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5781                        lower_32_bits(addr) & 0xFFFFF000);
5782        WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5783                        upper_32_bits(addr));
5784
5785        return 0;
5786}
5787
5788static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5789{
5790        uint32_t usec_timeout = 50000;  /* wait for 50ms */
5791        uint32_t tmp;
5792        int i;
5793        uint64_t addr;
5794
5795        /* Trigger an invalidation of the L1 instruction caches */
5796        tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5797        tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5798        WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5799
5800        /* Wait for invalidation complete */
5801        for (i = 0; i < usec_timeout; i++) {
5802                tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5803                if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5804                        INVALIDATE_CACHE_COMPLETE))
5805                        break;
5806                udelay(1);
5807        }
5808
5809        if (i >= usec_timeout) {
5810                dev_err(adev->dev, "failed to invalidate instruction cache\n");
5811                return -EINVAL;
5812        }
5813
5814        /* Program ce ucode address into intruction cache address register */
5815        addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5816                rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5817        WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5818                        lower_32_bits(addr) & 0xFFFFF000);
5819        WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5820                        upper_32_bits(addr));
5821
5822        return 0;
5823}
5824
5825static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5826{
5827        uint32_t usec_timeout = 50000;  /* wait for 50ms */
5828        uint32_t tmp;
5829        int i;
5830        uint64_t addr;
5831
5832        /* Trigger an invalidation of the L1 instruction caches */
5833        tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5834        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5835        WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5836
5837        /* Wait for invalidation complete */
5838        for (i = 0; i < usec_timeout; i++) {
5839                tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5840                if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5841                        INVALIDATE_CACHE_COMPLETE))
5842                        break;
5843                udelay(1);
5844        }
5845
5846        if (i >= usec_timeout) {
5847                dev_err(adev->dev, "failed to invalidate instruction cache\n");
5848                return -EINVAL;
5849        }
5850
5851        /* Program pfp ucode address into intruction cache address register */
5852        addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5853                rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5854        WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5855                        lower_32_bits(addr) & 0xFFFFF000);
5856        WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5857                        upper_32_bits(addr));
5858
5859        return 0;
5860}
5861
5862static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5863{
5864        uint32_t usec_timeout = 50000;  /* wait for 50ms */
5865        uint32_t tmp;
5866        int i;
5867        uint64_t addr;
5868
5869        /* Trigger an invalidation of the L1 instruction caches */
5870        tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5871        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5872        WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5873
5874        /* Wait for invalidation complete */
5875        for (i = 0; i < usec_timeout; i++) {
5876                tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5877                if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5878                        INVALIDATE_CACHE_COMPLETE))
5879                        break;
5880                udelay(1);
5881        }
5882
5883        if (i >= usec_timeout) {
5884                dev_err(adev->dev, "failed to invalidate instruction cache\n");
5885                return -EINVAL;
5886        }
5887
5888        /* Program mec1 ucode address into intruction cache address register */
5889        addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5890                rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5891        WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5892                        lower_32_bits(addr) & 0xFFFFF000);
5893        WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5894                        upper_32_bits(addr));
5895
5896        return 0;
5897}
5898
5899static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5900{
5901        uint32_t cp_status;
5902        uint32_t bootload_status;
5903        int i, r;
5904
5905        for (i = 0; i < adev->usec_timeout; i++) {
5906                cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5907                bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5908                if ((cp_status == 0) &&
5909                    (REG_GET_FIELD(bootload_status,
5910                        RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5911                        break;
5912                }
5913                udelay(1);
5914        }
5915
5916        if (i >= adev->usec_timeout) {
5917                dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5918                return -ETIMEDOUT;
5919        }
5920
5921        if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5922                r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5923                if (r)
5924                        return r;
5925
5926                r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5927                if (r)
5928                        return r;
5929
5930                r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5931                if (r)
5932                        return r;
5933
5934                r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5935                if (r)
5936                        return r;
5937        }
5938
5939        return 0;
5940}
5941
5942static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5943{
5944        int i;
5945        u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5946
5947        tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5948        tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5949        tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5950
5951        if (adev->asic_type == CHIP_NAVI12) {
5952                WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5953        } else {
5954                WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5955        }
5956
5957        for (i = 0; i < adev->usec_timeout; i++) {
5958                if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5959                        break;
5960                udelay(1);
5961        }
5962
5963        if (i >= adev->usec_timeout)
5964                DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5965
5966        return 0;
5967}
5968
5969static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5970{
5971        int r;
5972        const struct gfx_firmware_header_v1_0 *pfp_hdr;
5973        const __le32 *fw_data;
5974        unsigned i, fw_size;
5975        uint32_t tmp;
5976        uint32_t usec_timeout = 50000;  /* wait for 50ms */
5977
5978        pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5979                adev->gfx.pfp_fw->data;
5980
5981        amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5982
5983        fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5984                le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5985        fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5986
5987        r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5988                                      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5989                                      &adev->gfx.pfp.pfp_fw_obj,
5990                                      &adev->gfx.pfp.pfp_fw_gpu_addr,
5991                                      (void **)&adev->gfx.pfp.pfp_fw_ptr);
5992        if (r) {
5993                dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5994                gfx_v10_0_pfp_fini(adev);
5995                return r;
5996        }
5997
5998        memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5999
6000        amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);

6001        amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6002
6003        /* Trigger an invalidation of the L1 instruction caches */
6004        tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6005        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6006        WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6007
6008        /* Wait for invalidation complete */
6009        for (i = 0; i < usec_timeout; i++) {
6010                tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6011                if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6012                        INVALIDATE_CACHE_COMPLETE))
6013                        break;
6014                udelay(1);
6015        }
6016
6017        if (i >= usec_timeout) {
6018                dev_err(adev->dev, "failed to invalidate instruction cache\n");
6019                return -EINVAL;
6020        }
6021
6022        if (amdgpu_emu_mode == 1)
6023                adev->hdp.funcs->flush_hdp(adev, NULL);
6024
6025        tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6026        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6027        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6028        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6029        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6030        WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6031        WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6032                adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6033        WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6034                upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6035
6036        WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6037
6038        for (i = 0; i < pfp_hdr->jt_size; i++)
6039                WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6040                             le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6041
6042        WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6043
6044        return 0;
6045}
6046
6047static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6048{
6049        int r;
6050        const struct gfx_firmware_header_v1_0 *ce_hdr;
6051        const __le32 *fw_data;
6052        unsigned i, fw_size;
6053        uint32_t tmp;
6054        uint32_t usec_timeout = 50000;  /* wait for 50ms */
6055
6056        ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6057                adev->gfx.ce_fw->data;
6058
6059        amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6060
6061        fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6062                le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6063        fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6064
6065        r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6066                                      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6067                                      &adev->gfx.ce.ce_fw_obj,
6068                                      &adev->gfx.ce.ce_fw_gpu_addr,
6069                                      (void **)&adev->gfx.ce.ce_fw_ptr);
6070        if (r) {
6071                dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6072                gfx_v10_0_ce_fini(adev);
6073                return r;
6074        }
6075
6076        memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6077
6078        amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6079        amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6080
6081        /* Trigger an invalidation of the L1 instruction caches */
6082        tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6083        tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6084        WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6085
6086        /* Wait for invalidation complete */
6087        for (i = 0; i < usec_timeout; i++) {
6088                tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6089                if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6090                        INVALIDATE_CACHE_COMPLETE))
6091                        break;
6092                udelay(1);
6093        }
6094
6095        if (i >= usec_timeout) {
6096                dev_err(adev->dev, "failed to invalidate instruction cache\n");
6097                return -EINVAL;
6098        }
6099
6100        if (amdgpu_emu_mode == 1)
6101                adev->hdp.funcs->flush_hdp(adev, NULL);
6102
6103        tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6104        tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6105        tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6106        tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6107        tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6108        WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6109                adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6110        WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6111                upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6112
6113        WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6114
6115        for (i = 0; i < ce_hdr->jt_size; i++)
6116                WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6117                             le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6118
6119        WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6120
6121        return 0;
6122}
6123
6124static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6125{
6126        int r;
6127        const struct gfx_firmware_header_v1_0 *me_hdr;
6128        const __le32 *fw_data;
6129        unsigned i, fw_size;
6130        uint32_t tmp;
6131        uint32_t usec_timeout = 50000;  /* wait for 50ms */
6132
6133        me_hdr = (const struct gfx_firmware_header_v1_0 *)
6134                adev->gfx.me_fw->data;
6135
6136        amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6137
6138        fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6139                le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6140        fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6141
6142        r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6143                                      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6144                                      &adev->gfx.me.me_fw_obj,
6145                                      &adev->gfx.me.me_fw_gpu_addr,
6146                                      (void **)&adev->gfx.me.me_fw_ptr);
6147        if (r) {
6148                dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6149                gfx_v10_0_me_fini(adev);
6150                return r;
6151        }
6152
6153        memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6154
6155        amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6156        amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6157
6158        /* Trigger an invalidation of the L1 instruction caches */
6159        tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6160        tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6161        WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6162
6163        /* Wait for invalidation complete */
6164        for (i = 0; i < usec_timeout; i++) {
6165                tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6166                if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6167                        INVALIDATE_CACHE_COMPLETE))
6168                        break;
6169                udelay(1);
6170        }
6171
6172        if (i >= usec_timeout) {
6173                dev_err(adev->dev, "failed to invalidate instruction cache\n");
6174                return -EINVAL;
6175        }
6176
6177        if (amdgpu_emu_mode == 1)
6178                adev->hdp.funcs->flush_hdp(adev, NULL);
6179
6180        tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6181        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6182        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6183        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6184        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6185        WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6186                adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6187        WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6188                upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6189
6190        WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6191
6192        for (i = 0; i < me_hdr->jt_size; i++)
6193                WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6194                             le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6195
6196        WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6197
6198        return 0;
6199}
6200
6201static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6202{
6203        int r;
6204
6205        if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6206                return -EINVAL;
6207
6208        gfx_v10_0_cp_gfx_enable(adev, false);
6209
6210        r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6211        if (r) {
6212                dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6213                return r;
6214        }
6215
6216        r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6217        if (r) {
6218                dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6219                return r;
6220        }
6221
6222        r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6223        if (r) {
6224                dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6225                return r;
6226        }
6227
6228        return 0;
6229}
6230
6231static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6232{
6233        struct amdgpu_ring *ring;
6234        const struct cs_section_def *sect = NULL;
6235        const struct cs_extent_def *ext = NULL;
6236        int r, i;
6237        int ctx_reg_offset;
6238
6239        /* init the CP */
6240        WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6241                     adev->gfx.config.max_hw_contexts - 1);
6242        WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6243
6244        gfx_v10_0_cp_gfx_enable(adev, true);
6245
6246        ring = &adev->gfx.gfx_ring[0];
6247        r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6248        if (r) {
6249                DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6250                return r;
6251        }
6252
6253        amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6254        amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6255
6256        amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6257        amdgpu_ring_write(ring, 0x80000000);
6258        amdgpu_ring_write(ring, 0x80000000);
6259
6260        for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6261                for (ext = sect->section; ext->extent != NULL; ++ext) {
6262                        if (sect->id == SECT_CONTEXT) {
6263                                amdgpu_ring_write(ring,
6264                                                  PACKET3(PACKET3_SET_CONTEXT_REG,
6265                                                          ext->reg_count));
6266                                amdgpu_ring_write(ring, ext->reg_index -
6267                                                  PACKET3_SET_CONTEXT_REG_START);
6268                                for (i = 0; i < ext->reg_count; i++)
6269                                        amdgpu_ring_write(ring, ext->extent[i]);
6270                        }
6271                }
6272        }
6273
6274        ctx_reg_offset =
6275                SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6276        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6277        amdgpu_ring_write(ring, ctx_reg_offset);
6278        amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6279
6280        amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6281        amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6282
6283        amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6284        amdgpu_ring_write(ring, 0);
6285
6286        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6287        amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6288        amdgpu_ring_write(ring, 0x8000);
6289        amdgpu_ring_write(ring, 0x8000);
6290
6291        amdgpu_ring_commit(ring);
6292
6293        /* submit cs packet to copy state 0 to next available state */
6294        if (adev->gfx.num_gfx_rings > 1) {
6295                /* maximum supported gfx ring is 2 */
6296                ring = &adev->gfx.gfx_ring[1];
6297                r = amdgpu_ring_alloc(ring, 2);
6298                if (r) {
6299                        DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6300                        return r;
6301                }
6302
6303                amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6304                amdgpu_ring_write(ring, 0);
6305
6306                amdgpu_ring_commit(ring);
6307        }
6308        return 0;
6309}
6310
6311static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6312                                         CP_PIPE_ID pipe)
6313{
6314        u32 tmp;
6315
6316        tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6317        tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6318
6319        WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6320}
6321
6322static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6323                                          struct amdgpu_ring *ring)
6324{
6325        u32 tmp;
6326
6327        if (!amdgpu_async_gfx_ring) {
6328                tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6329                if (ring->use_doorbell) {
6330                        tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6331                                                DOORBELL_OFFSET, ring->doorbell_index);
6332                        tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6333                                                DOORBELL_EN, 1);
6334                } else {
6335                        tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6336                                                DOORBELL_EN, 0);
6337                }
6338                WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6339        }
6340        switch (adev->asic_type) {
6341        case CHIP_SIENNA_CICHLID:
6342        case CHIP_NAVY_FLOUNDER:
6343        case CHIP_VANGOGH:
6344        case CHIP_DIMGREY_CAVEFISH:
6345        case CHIP_BEIGE_GOBY:
6346        case CHIP_YELLOW_CARP:
6347                tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6348                                    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6349                WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6350
6351                WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6352                             CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6353                break;
6354        default:
6355                tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6356                                    DOORBELL_RANGE_LOWER, ring->doorbell_index);
6357                WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6358
6359                WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6360                             CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6361                break;
6362        }
6363}
6364
6365static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6366{
6367        struct amdgpu_ring *ring;
6368        u32 tmp;
6369        u32 rb_bufsz;
6370        u64 rb_addr, rptr_addr, wptr_gpu_addr;
6371        u32 i;
6372
6373        /* Set the write pointer delay */
6374        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6375
6376        /* set the RB to use vmid 0 */
6377        WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6378
6379        /* Init gfx ring 0 for pipe 0 */
6380        mutex_lock(&adev->srbm_mutex);
6381        gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6382
6383        /* Set ring buffer size */
6384        ring = &adev->gfx.gfx_ring[0];
6385        rb_bufsz = order_base_2(ring->ring_size / 8);
6386        tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6387        tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6388#ifdef __BIG_ENDIAN
6389        tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6390#endif
6391        WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6392
6393        /* Initialize the ring buffer's write pointers */
6394        ring->wptr = 0;
6395        WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6396        WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6397
6398        /* set the wb address wether it's enabled or not */
6399        rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6400        WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6401        WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6402                     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6403
6404        wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6405        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6406                     lower_32_bits(wptr_gpu_addr));
6407        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6408                     upper_32_bits(wptr_gpu_addr));
6409
6410        mdelay(1);
6411        WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6412
6413        rb_addr = ring->gpu_addr >> 8;
6414        WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6415        WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6416
6417        WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6418
6419        gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6420        mutex_unlock(&adev->srbm_mutex);
6421
6422        /* Init gfx ring 1 for pipe 1 */
6423        if (adev->gfx.num_gfx_rings > 1) {
6424                mutex_lock(&adev->srbm_mutex);
6425                gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6426                /* maximum supported gfx ring is 2 */
6427                ring = &adev->gfx.gfx_ring[1];
6428                rb_bufsz = order_base_2(ring->ring_size / 8);
6429                tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6430                tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6431                WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6432                /* Initialize the ring buffer's write pointers */
6433                ring->wptr = 0;
6434                WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6435                WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6436                /* Set the wb address wether it's enabled or not */
6437                rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6438                WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6439                WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6440                             CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6441                wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6442                WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6443                             lower_32_bits(wptr_gpu_addr));
6444                WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6445                             upper_32_bits(wptr_gpu_addr));
6446
6447                mdelay(1);
6448                WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6449
6450                rb_addr = ring->gpu_addr >> 8;
6451                WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6452                WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6453                WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6454
6455                gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6456                mutex_unlock(&adev->srbm_mutex);
6457        }
6458        /* Switch to pipe 0 */
6459        mutex_lock(&adev->srbm_mutex);
6460        gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6461        mutex_unlock(&adev->srbm_mutex);
6462
6463        /* start the ring */
6464        gfx_v10_0_cp_gfx_start(adev);
6465
6466        for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6467                ring = &adev->gfx.gfx_ring[i];
6468                ring->sched.ready = true;
6469        }
6470
6471        return 0;
6472}
6473
6474static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6475{
6476        if (enable) {
6477                switch (adev->asic_type) {
6478                case CHIP_SIENNA_CICHLID:
6479                case CHIP_NAVY_FLOUNDER:
6480                case CHIP_VANGOGH:
6481                case CHIP_DIMGREY_CAVEFISH:
6482                case CHIP_BEIGE_GOBY:
6483                case CHIP_YELLOW_CARP:
6484                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6485                        break;
6486                default:
6487                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6488                        break;
6489                }
6490        } else {
6491                switch (adev->asic_type) {
6492                case CHIP_SIENNA_CICHLID:
6493                case CHIP_NAVY_FLOUNDER:
6494                case CHIP_VANGOGH:
6495                case CHIP_DIMGREY_CAVEFISH:
6496                case CHIP_BEIGE_GOBY:
6497                case CHIP_YELLOW_CARP:
6498                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6499                                     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6500                                      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6501                        break;
6502                default:
6503                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6504                                     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6505                                      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6506                        break;
6507                }
6508                adev->gfx.kiq.ring.sched.ready = false;
6509        }
6510        udelay(50);
6511}
6512
6513static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6514{
6515        const struct gfx_firmware_header_v1_0 *mec_hdr;
6516        const __le32 *fw_data;
6517        unsigned i;
6518        u32 tmp;
6519        u32 usec_timeout = 50000; /* Wait for 50 ms */
6520
6521        if (!adev->gfx.mec_fw)
6522                return -EINVAL;
6523
6524        gfx_v10_0_cp_compute_enable(adev, false);
6525
6526        mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6527        amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6528
6529        fw_data = (const __le32 *)
6530                (adev->gfx.mec_fw->data +
6531                 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6532
6533        /* Trigger an invalidation of the L1 instruction caches */
6534        tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6535        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6536        WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6537
6538        /* Wait for invalidation complete */
6539        for (i = 0; i < usec_timeout; i++) {
6540                tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6541                if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6542                                       INVALIDATE_CACHE_COMPLETE))
6543                        break;
6544                udelay(1);
6545        }
6546
6547        if (i >= usec_timeout) {
6548                dev_err(adev->dev, "failed to invalidate instruction cache\n");
6549                return -EINVAL;
6550        }
6551
6552        if (amdgpu_emu_mode == 1)
6553                adev->hdp.funcs->flush_hdp(adev, NULL);
6554
6555        tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6556        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6557        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6558        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6559        WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6560
6561        WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6562                     0xFFFFF000);
6563        WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6564                     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6565
6566        /* MEC1 */
6567        WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6568
6569        for (i = 0; i < mec_hdr->jt_size; i++)
6570                WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6571                             le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6572
6573        WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6574
6575        /*
6576         * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6577         * different microcode than MEC1.
6578         */
6579
6580        return 0;
6581}
6582
6583static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6584{
6585        uint32_t tmp;
6586        struct amdgpu_device *adev = ring->adev;
6587
6588        /* tell RLC which is KIQ queue */
6589        switch (adev->asic_type) {
6590        case CHIP_SIENNA_CICHLID:
6591        case CHIP_NAVY_FLOUNDER:
6592        case CHIP_VANGOGH:
6593        case CHIP_DIMGREY_CAVEFISH:
6594        case CHIP_BEIGE_GOBY:
6595        case CHIP_YELLOW_CARP:
6596                tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6597                tmp &= 0xffffff00;
6598                tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6599                WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6600                tmp |= 0x80;
6601                WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6602                break;
6603        default:
6604                tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6605                tmp &= 0xffffff00;
6606                tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6607                WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6608                tmp |= 0x80;
6609                WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6610                break;
6611        }
6612}
6613
6614static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6615{
6616        struct amdgpu_device *adev = ring->adev;
6617        struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6618        uint64_t hqd_gpu_addr, wb_gpu_addr;
6619        uint32_t tmp;
6620        uint32_t rb_bufsz;
6621
6622        /* set up gfx hqd wptr */
6623        mqd->cp_gfx_hqd_wptr = 0;
6624        mqd->cp_gfx_hqd_wptr_hi = 0;
6625
6626        /* set the pointer to the MQD */
6627        mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6628        mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6629
6630        /* set up mqd control */
6631        tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6632        tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6633        tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6634        tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6635        mqd->cp_gfx_mqd_control = tmp;
6636
6637        /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6638        tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6639        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6640        mqd->cp_gfx_hqd_vmid = 0;
6641
6642        /* set up default queue priority level
6643         * 0x0 = low priority, 0x1 = high priority */
6644        tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6645        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6646        mqd->cp_gfx_hqd_queue_priority = tmp;
6647
6648        /* set up time quantum */
6649        tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6650        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6651        mqd->cp_gfx_hqd_quantum = tmp;
6652
6653        /* set up gfx hqd base. this is similar as CP_RB_BASE */
6654        hqd_gpu_addr = ring->gpu_addr >> 8;
6655        mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6656        mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6657
6658        /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6659        wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6660        mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6661        mqd->cp_gfx_hqd_rptr_addr_hi =
6662                upper_32_bits(wb_gpu_addr) & 0xffff;
6663
6664        /* set up rb_wptr_poll addr */
6665        wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6666        mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6667        mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6668
6669        /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6670        rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6671        tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6672        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6673        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6674#ifdef __BIG_ENDIAN
6675        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6676#endif
6677        mqd->cp_gfx_hqd_cntl = tmp;
6678
6679        /* set up cp_doorbell_control */
6680        tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6681        if (ring->use_doorbell) {
6682                tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6683                                    DOORBELL_OFFSET, ring->doorbell_index);
6684                tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6685                                    DOORBELL_EN, 1);
6686        } else
6687                tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6688                                    DOORBELL_EN, 0);
6689        mqd->cp_rb_doorbell_control = tmp;
6690
6691        /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6692         *otherwise the range of the second ring will override the first ring */
6693        if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6694                gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6695
6696        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6697        ring->wptr = 0;
6698        mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6699
6700        /* active the queue */
6701        mqd->cp_gfx_hqd_active = 1;
6702
6703        return 0;
6704}
6705
6706#ifdef BRING_UP_DEBUG
6707static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6708{
6709        struct amdgpu_device *adev = ring->adev;
6710        struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6711
6712        /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6713        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6714        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6715
6716        /* set GFX_MQD_BASE */
6717        WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6718        WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6719
6720        /* set GFX_MQD_CONTROL */
6721        WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6722
6723        /* set GFX_HQD_VMID to 0 */
6724        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6725
6726        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6727                        mqd->cp_gfx_hqd_queue_priority);
6728        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6729
6730        /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6731        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6732        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6733
6734        /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6735        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6736        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6737
6738        /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6739        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6740
6741        /* set RB_WPTR_POLL_ADDR */
6742        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6743        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6744
6745        /* set RB_DOORBELL_CONTROL */
6746        WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6747
6748        /* active the queue */
6749        WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6750
6751        return 0;
6752}
6753#endif
6754
6755static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6756{
6757        struct amdgpu_device *adev = ring->adev;
6758        struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6759        int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6760
6761        if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6762                memset((void *)mqd, 0, sizeof(*mqd));
6763                mutex_lock(&adev->srbm_mutex);
6764                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6765                gfx_v10_0_gfx_mqd_init(ring);
6766#ifdef BRING_UP_DEBUG
6767                gfx_v10_0_gfx_queue_init_register(ring);
6768#endif
6769                nv_grbm_select(adev, 0, 0, 0, 0);
6770                mutex_unlock(&adev->srbm_mutex);
6771                if (adev->gfx.me.mqd_backup[mqd_idx])
6772                        memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6773        } else if (amdgpu_in_reset(adev)) {
6774                /* reset mqd with the backup copy */
6775                if (adev->gfx.me.mqd_backup[mqd_idx])
6776                        memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6777                /* reset the ring */
6778                ring->wptr = 0;
6779                adev->wb.wb[ring->wptr_offs] = 0;
6780                amdgpu_ring_clear_ring(ring);
6781#ifdef BRING_UP_DEBUG
6782                mutex_lock(&adev->srbm_mutex);
6783                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6784                gfx_v10_0_gfx_queue_init_register(ring);
6785                nv_grbm_select(adev, 0, 0, 0, 0);
6786                mutex_unlock(&adev->srbm_mutex);
6787#endif
6788        } else {
6789                amdgpu_ring_clear_ring(ring);
6790        }
6791
6792        return 0;
6793}
6794
6795#ifndef BRING_UP_DEBUG
6796static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6797{
6798        struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6799        struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6800        int r, i;
6801
6802        if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6803                return -EINVAL;
6804
6805        r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6806                                        adev->gfx.num_gfx_rings);
6807        if (r) {
6808                DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6809                return r;
6810        }
6811
6812        for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6813                kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6814
6815        return amdgpu_ring_test_helper(kiq_ring);
6816}
6817#endif
6818
6819static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6820{
6821        int r, i;
6822        struct amdgpu_ring *ring;
6823
6824        for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6825                ring = &adev->gfx.gfx_ring[i];
6826
6827                r = amdgpu_bo_reserve(ring->mqd_obj, false);
6828                if (unlikely(r != 0))
6829                        goto done;
6830
6831                r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6832                if (!r) {
6833                        r = gfx_v10_0_gfx_init_queue(ring);
6834                        amdgpu_bo_kunmap(ring->mqd_obj);
6835                        ring->mqd_ptr = NULL;
6836                }
6837                amdgpu_bo_unreserve(ring->mqd_obj);
6838                if (r)
6839                        goto done;
6840        }
6841#ifndef BRING_UP_DEBUG
6842        r = gfx_v10_0_kiq_enable_kgq(adev);
6843        if (r)
6844                goto done;
6845#endif
6846        r = gfx_v10_0_cp_gfx_start(adev);
6847        if (r)
6848                goto done;
6849
6850        for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6851                ring = &adev->gfx.gfx_ring[i];
6852                ring->sched.ready = true;
6853        }
6854done:
6855        return r;
6856}
6857
6858static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6859{
6860        struct amdgpu_device *adev = ring->adev;
6861
6862        if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6863                if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6864                        mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6865                        mqd->cp_hqd_queue_priority =
6866                                AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6867                }
6868        }
6869}
6870
6871static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6872{
6873        struct amdgpu_device *adev = ring->adev;
6874        struct v10_compute_mqd *mqd = ring->mqd_ptr;
6875        uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6876        uint32_t tmp;
6877
6878        mqd->header = 0xC0310800;
6879        mqd->compute_pipelinestat_enable = 0x00000001;
6880        mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6881        mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6882        mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6883        mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6884        mqd->compute_misc_reserved = 0x00000003;
6885
6886        eop_base_addr = ring->eop_gpu_addr >> 8;
6887        mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6888        mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6889
6890        /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6891        tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6892        tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6893                        (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6894
6895        mqd->cp_hqd_eop_control = tmp;
6896
6897        /* enable doorbell? */
6898        tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6899
6900        if (ring->use_doorbell) {
6901                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6902                                    DOORBELL_OFFSET, ring->doorbell_index);
6903                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6904                                    DOORBELL_EN, 1);
6905                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6906                                    DOORBELL_SOURCE, 0);
6907                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6908                                    DOORBELL_HIT, 0);
6909        } else {
6910                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6911                                    DOORBELL_EN, 0);
6912        }
6913
6914        mqd->cp_hqd_pq_doorbell_control = tmp;
6915
6916        /* disable the queue if it's active */
6917        ring->wptr = 0;
6918        mqd->cp_hqd_dequeue_request = 0;
6919        mqd->cp_hqd_pq_rptr = 0;
6920        mqd->cp_hqd_pq_wptr_lo = 0;
6921        mqd->cp_hqd_pq_wptr_hi = 0;
6922
6923        /* set the pointer to the MQD */
6924        mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6925        mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6926
6927        /* set MQD vmid to 0 */
6928        tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6929        tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6930        mqd->cp_mqd_control = tmp;
6931
6932        /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6933        hqd_gpu_addr = ring->gpu_addr >> 8;
6934        mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6935        mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6936
6937        /* set up the HQD, this is similar to CP_RB0_CNTL */
6938        tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6939        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6940                            (order_base_2(ring->ring_size / 4) - 1));
6941        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6942                            ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6943#ifdef __BIG_ENDIAN
6944        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6945#endif
6946        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6947        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6948        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6949        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6950        mqd->cp_hqd_pq_control = tmp;
6951
6952        /* set the wb address whether it's enabled or not */
6953        wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6954        mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6955        mqd->cp_hqd_pq_rptr_report_addr_hi =
6956                upper_32_bits(wb_gpu_addr) & 0xffff;
6957
6958        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6959        wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6960        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6961        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6962
6963        tmp = 0;
6964        /* enable the doorbell if requested */
6965        if (ring->use_doorbell) {
6966                tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6967                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6968                                DOORBELL_OFFSET, ring->doorbell_index);
6969
6970                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6971                                    DOORBELL_EN, 1);
6972                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6973                                    DOORBELL_SOURCE, 0);
6974                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6975                                    DOORBELL_HIT, 0);
6976        }
6977
6978        mqd->cp_hqd_pq_doorbell_control = tmp;
6979
6980        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6981        ring->wptr = 0;
6982        mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6983
6984        /* set the vmid for the queue */
6985        mqd->cp_hqd_vmid = 0;
6986
6987        tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6988        tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6989        mqd->cp_hqd_persistent_state = tmp;
6990
6991        /* set MIN_IB_AVAIL_SIZE */
6992        tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6993        tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6994        mqd->cp_hqd_ib_control = tmp;
6995
6996        /* set static priority for a compute queue/ring */
6997        gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6998
6999        /* map_queues packet doesn't need activate the queue,
7000         * so only kiq need set this field.

7001         */
7002        if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
7003                mqd->cp_hqd_active = 1;
7004
7005        return 0;
7006}
7007
7008static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
7009{
7010        struct amdgpu_device *adev = ring->adev;
7011        struct v10_compute_mqd *mqd = ring->mqd_ptr;
7012        int j;
7013
7014        /* inactivate the queue */
7015        if (amdgpu_sriov_vf(adev))
7016                WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
7017
7018        /* disable wptr polling */
7019        WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
7020
7021        /* write the EOP addr */
7022        WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7023               mqd->cp_hqd_eop_base_addr_lo);
7024        WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7025               mqd->cp_hqd_eop_base_addr_hi);
7026
7027        /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7028        WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7029               mqd->cp_hqd_eop_control);
7030
7031        /* enable doorbell? */
7032        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7033               mqd->cp_hqd_pq_doorbell_control);
7034
7035        /* disable the queue if it's active */
7036        if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
7037                WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7038                for (j = 0; j < adev->usec_timeout; j++) {
7039                        if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7040                                break;
7041                        udelay(1);
7042                }
7043                WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7044                       mqd->cp_hqd_dequeue_request);
7045                WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7046                       mqd->cp_hqd_pq_rptr);
7047                WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7048                       mqd->cp_hqd_pq_wptr_lo);
7049                WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7050                       mqd->cp_hqd_pq_wptr_hi);
7051        }
7052
7053        /* set the pointer to the MQD */
7054        WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7055               mqd->cp_mqd_base_addr_lo);
7056        WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7057               mqd->cp_mqd_base_addr_hi);
7058
7059        /* set MQD vmid to 0 */
7060        WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7061               mqd->cp_mqd_control);
7062
7063        /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7064        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7065               mqd->cp_hqd_pq_base_lo);
7066        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7067               mqd->cp_hqd_pq_base_hi);
7068
7069        /* set up the HQD, this is similar to CP_RB0_CNTL */
7070        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7071               mqd->cp_hqd_pq_control);
7072
7073        /* set the wb address whether it's enabled or not */
7074        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7075                mqd->cp_hqd_pq_rptr_report_addr_lo);
7076        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7077                mqd->cp_hqd_pq_rptr_report_addr_hi);
7078
7079        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7080        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7081               mqd->cp_hqd_pq_wptr_poll_addr_lo);
7082        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7083               mqd->cp_hqd_pq_wptr_poll_addr_hi);
7084
7085        /* enable the doorbell if requested */
7086        if (ring->use_doorbell) {
7087                WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7088                        (adev->doorbell_index.kiq * 2) << 2);
7089                WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7090                        (adev->doorbell_index.userqueue_end * 2) << 2);
7091        }
7092
7093        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7094               mqd->cp_hqd_pq_doorbell_control);
7095
7096        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7097        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7098               mqd->cp_hqd_pq_wptr_lo);
7099        WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7100               mqd->cp_hqd_pq_wptr_hi);
7101
7102        /* set the vmid for the queue */
7103        WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7104
7105        WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7106               mqd->cp_hqd_persistent_state);
7107
7108        /* activate the queue */
7109        WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7110               mqd->cp_hqd_active);
7111
7112        if (ring->use_doorbell)
7113                WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7114
7115        return 0;
7116}
7117
7118static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7119{
7120        struct amdgpu_device *adev = ring->adev;
7121        struct v10_compute_mqd *mqd = ring->mqd_ptr;
7122        int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7123
7124        gfx_v10_0_kiq_setting(ring);
7125
7126        if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7127                /* reset MQD to a clean status */
7128                if (adev->gfx.mec.mqd_backup[mqd_idx])
7129                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7130
7131                /* reset ring buffer */
7132                ring->wptr = 0;
7133                amdgpu_ring_clear_ring(ring);
7134
7135                mutex_lock(&adev->srbm_mutex);
7136                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7137                gfx_v10_0_kiq_init_register(ring);
7138                nv_grbm_select(adev, 0, 0, 0, 0);
7139                mutex_unlock(&adev->srbm_mutex);
7140        } else {
7141                memset((void *)mqd, 0, sizeof(*mqd));
7142                mutex_lock(&adev->srbm_mutex);
7143                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7144                gfx_v10_0_compute_mqd_init(ring);
7145                gfx_v10_0_kiq_init_register(ring);
7146                nv_grbm_select(adev, 0, 0, 0, 0);
7147                mutex_unlock(&adev->srbm_mutex);
7148
7149                if (adev->gfx.mec.mqd_backup[mqd_idx])
7150                        memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7151        }
7152
7153        return 0;
7154}
7155
7156static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7157{
7158        struct amdgpu_device *adev = ring->adev;
7159        struct v10_compute_mqd *mqd = ring->mqd_ptr;
7160        int mqd_idx = ring - &adev->gfx.compute_ring[0];
7161
7162        if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7163                memset((void *)mqd, 0, sizeof(*mqd));
7164                mutex_lock(&adev->srbm_mutex);
7165                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7166                gfx_v10_0_compute_mqd_init(ring);
7167                nv_grbm_select(adev, 0, 0, 0, 0);
7168                mutex_unlock(&adev->srbm_mutex);
7169
7170                if (adev->gfx.mec.mqd_backup[mqd_idx])
7171                        memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7172        } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7173                /* reset MQD to a clean status */
7174                if (adev->gfx.mec.mqd_backup[mqd_idx])
7175                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7176
7177                /* reset ring buffer */
7178                ring->wptr = 0;
7179                atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
7180                amdgpu_ring_clear_ring(ring);
7181        } else {
7182                amdgpu_ring_clear_ring(ring);
7183        }
7184
7185        return 0;
7186}
7187
7188static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7189{
7190        struct amdgpu_ring *ring;
7191        int r;
7192
7193        ring = &adev->gfx.kiq.ring;
7194
7195        r = amdgpu_bo_reserve(ring->mqd_obj, false);
7196        if (unlikely(r != 0))
7197                return r;
7198
7199        r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7200        if (unlikely(r != 0))
7201                return r;
7202
7203        gfx_v10_0_kiq_init_queue(ring);
7204        amdgpu_bo_kunmap(ring->mqd_obj);
7205        ring->mqd_ptr = NULL;
7206        amdgpu_bo_unreserve(ring->mqd_obj);
7207        ring->sched.ready = true;
7208        return 0;
7209}
7210
7211static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7212{
7213        struct amdgpu_ring *ring = NULL;
7214        int r = 0, i;
7215
7216        gfx_v10_0_cp_compute_enable(adev, true);
7217
7218        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7219                ring = &adev->gfx.compute_ring[i];
7220
7221                r = amdgpu_bo_reserve(ring->mqd_obj, false);
7222                if (unlikely(r != 0))
7223                        goto done;
7224                r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7225                if (!r) {
7226                        r = gfx_v10_0_kcq_init_queue(ring);
7227                        amdgpu_bo_kunmap(ring->mqd_obj);
7228                        ring->mqd_ptr = NULL;
7229                }
7230                amdgpu_bo_unreserve(ring->mqd_obj);
7231                if (r)
7232                        goto done;
7233        }
7234
7235        r = amdgpu_gfx_enable_kcq(adev);
7236done:
7237        return r;
7238}
7239
7240static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7241{
7242        int r, i;
7243        struct amdgpu_ring *ring;
7244
7245        if (!(adev->flags & AMD_IS_APU))
7246                gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7247
7248        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7249                /* legacy firmware loading */
7250                r = gfx_v10_0_cp_gfx_load_microcode(adev);
7251                if (r)
7252                        return r;
7253
7254                r = gfx_v10_0_cp_compute_load_microcode(adev);
7255                if (r)
7256                        return r;
7257        }
7258
7259        r = gfx_v10_0_kiq_resume(adev);
7260        if (r)
7261                return r;
7262
7263        r = gfx_v10_0_kcq_resume(adev);
7264        if (r)
7265                return r;
7266
7267        if (!amdgpu_async_gfx_ring) {
7268                r = gfx_v10_0_cp_gfx_resume(adev);
7269                if (r)
7270                        return r;
7271        } else {
7272                r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7273                if (r)
7274                        return r;
7275        }
7276
7277        for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7278                ring = &adev->gfx.gfx_ring[i];
7279                r = amdgpu_ring_test_helper(ring);
7280                if (r)
7281                        return r;
7282        }
7283
7284        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7285                ring = &adev->gfx.compute_ring[i];
7286                r = amdgpu_ring_test_helper(ring);
7287                if (r)
7288                        return r;
7289        }
7290
7291        return 0;
7292}
7293
7294static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7295{
7296        gfx_v10_0_cp_gfx_enable(adev, enable);
7297        gfx_v10_0_cp_compute_enable(adev, enable);
7298}
7299
7300static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7301{
7302        uint32_t data, pattern = 0xDEADBEEF;
7303
7304        /* check if mmVGT_ESGS_RING_SIZE_UMD
7305         * has been remapped to mmVGT_ESGS_RING_SIZE */
7306        switch (adev->asic_type) {
7307        case CHIP_SIENNA_CICHLID:
7308        case CHIP_NAVY_FLOUNDER:
7309        case CHIP_DIMGREY_CAVEFISH:
7310        case CHIP_BEIGE_GOBY:
7311                data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7312                WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7313                WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7314
7315                if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7316                        WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7317                        return true;
7318                } else {
7319                        WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7320                        return false;
7321                }
7322                break;
7323        case CHIP_VANGOGH:
7324        case CHIP_YELLOW_CARP:
7325                return true;
7326        default:
7327                data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7328                WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7329                WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7330
7331                if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7332                        WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7333                        return true;
7334                } else {
7335                        WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7336                        return false;
7337                }
7338                break;
7339        }
7340}
7341
7342static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7343{
7344        uint32_t data;
7345
7346        if (amdgpu_sriov_vf(adev))
7347                return;
7348
7349        /* initialize cam_index to 0
7350         * index will auto-inc after each data writting */
7351        WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7352
7353        switch (adev->asic_type) {
7354        case CHIP_SIENNA_CICHLID:
7355        case CHIP_NAVY_FLOUNDER:
7356        case CHIP_VANGOGH:
7357        case CHIP_DIMGREY_CAVEFISH:
7358        case CHIP_BEIGE_GOBY:
7359        case CHIP_YELLOW_CARP:
7360                /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7361                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7362                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7363                       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7364                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7365                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7366                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7367
7368                /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7369                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7370                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7371                       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7372                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7373                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7374                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7375
7376                /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7377                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7378                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7379                       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7380                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7381                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7382                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7383
7384                /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7385                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7386                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7387                       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7388                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7389                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7390                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7391
7392                /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7393                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7394                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7395                       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7396                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7397                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7398                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7399
7400                /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7401                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7402                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7403                       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7404                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7405                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7406                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7407
7408                /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7409                data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7410                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7411                       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7412                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7413                break;
7414        default:
7415                /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7416                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7417                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7418                       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7419                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7420                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7421                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7422
7423                /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7424                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7425                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7426                       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7427                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7428                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7429                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7430
7431                /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7432                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7433                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7434                       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7435                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7436                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7437                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7438
7439                /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7440                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7441                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7442                       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7443                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7444                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7445                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7446
7447                /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7448                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7449                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7450                       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7451                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7452                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7453                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7454
7455                /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7456                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7457                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7458                       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7459                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7460                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7461                WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7462
7463                /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7464                data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7465                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7466                       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7467                        GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7468                break;
7469        }
7470
7471        WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7472        WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7473}
7474
7475static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7476{
7477        uint32_t data;
7478        data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7479        data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7480        WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7481
7482        data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7483        data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7484        WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7485}
7486
7487static int gfx_v10_0_hw_init(void *handle)
7488{
7489        int r;
7490        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7491
7492        if (!amdgpu_emu_mode)
7493                gfx_v10_0_init_golden_registers(adev);
7494
7495        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7496                /**
7497                 * For gfx 10, rlc firmware loading relies on smu firmware is
7498                 * loaded firstly, so in direct type, it has to load smc ucode
7499                 * here before rlc.
7500                 */
7501                if (!(adev->flags & AMD_IS_APU)) {
7502                        r = amdgpu_pm_load_smu_firmware(adev, NULL);
7503                        if (r)
7504                                return r;
7505                }
7506                gfx_v10_0_disable_gpa_mode(adev);
7507        }
7508
7509        /* if GRBM CAM not remapped, set up the remapping */
7510        if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7511                gfx_v10_0_setup_grbm_cam_remapping(adev);
7512
7513        gfx_v10_0_constants_init(adev);
7514
7515        r = gfx_v10_0_rlc_resume(adev);
7516        if (r)
7517                return r;
7518
7519        /*
7520         * init golden registers and rlc resume may override some registers,
7521         * reconfig them here
7522         */
7523        if (adev->asic_type == CHIP_NAVI10 ||
7524            adev->asic_type == CHIP_NAVI14 ||
7525            adev->asic_type == CHIP_NAVI12)
7526                gfx_v10_0_tcp_harvest(adev);
7527
7528        r = gfx_v10_0_cp_resume(adev);
7529        if (r)
7530                return r;
7531
7532        if (adev->asic_type == CHIP_SIENNA_CICHLID)
7533                gfx_v10_3_program_pbb_mode(adev);
7534
7535        if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7536                gfx_v10_3_set_power_brake_sequence(adev);
7537
7538        return r;
7539}
7540
7541#ifndef BRING_UP_DEBUG
7542static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7543{
7544        struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7545        struct amdgpu_ring *kiq_ring = &kiq->ring;
7546        int i;
7547
7548        if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7549                return -EINVAL;
7550
7551        if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7552                                        adev->gfx.num_gfx_rings))
7553                return -ENOMEM;
7554
7555        for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7556                kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7557                                           PREEMPT_QUEUES, 0, 0);
7558
7559        return amdgpu_ring_test_helper(kiq_ring);
7560}
7561#endif
7562
7563static int gfx_v10_0_hw_fini(void *handle)
7564{
7565        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7566        int r;
7567        uint32_t tmp;
7568
7569        amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7570        amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7571
7572        if (!adev->no_hw_access) {
7573#ifndef BRING_UP_DEBUG
7574                if (amdgpu_async_gfx_ring) {
7575                        r = gfx_v10_0_kiq_disable_kgq(adev);
7576                        if (r)
7577                                DRM_ERROR("KGQ disable failed\n");
7578                }
7579#endif
7580                if (amdgpu_gfx_disable_kcq(adev))
7581                        DRM_ERROR("KCQ disable failed\n");
7582        }
7583
7584        if (amdgpu_sriov_vf(adev)) {
7585                gfx_v10_0_cp_gfx_enable(adev, false);
7586                /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7587                if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
7588                        tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7589                        tmp &= 0xffffff00;
7590                        WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7591                } else {
7592                        tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7593                        tmp &= 0xffffff00;
7594                        WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7595                }
7596
7597                return 0;
7598        }
7599        gfx_v10_0_cp_enable(adev, false);
7600        gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7601
7602        return 0;
7603}
7604
7605static int gfx_v10_0_suspend(void *handle)
7606{
7607        return gfx_v10_0_hw_fini(handle);
7608}
7609
7610static int gfx_v10_0_resume(void *handle)
7611{
7612        return gfx_v10_0_hw_init(handle);
7613}
7614
7615static bool gfx_v10_0_is_idle(void *handle)
7616{
7617        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7618
7619        if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7620                                GRBM_STATUS, GUI_ACTIVE))
7621                return false;
7622        else
7623                return true;
7624}
7625
7626static int gfx_v10_0_wait_for_idle(void *handle)
7627{
7628        unsigned i;
7629        u32 tmp;
7630        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7631
7632        for (i = 0; i < adev->usec_timeout; i++) {
7633                /* read MC_STATUS */
7634                tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7635                        GRBM_STATUS__GUI_ACTIVE_MASK;
7636
7637                if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7638                        return 0;
7639                udelay(1);
7640        }
7641        return -ETIMEDOUT;
7642}
7643
7644static int gfx_v10_0_soft_reset(void *handle)
7645{
7646        u32 grbm_soft_reset = 0;
7647        u32 tmp;
7648        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7649
7650        /* GRBM_STATUS */
7651        tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7652        if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7653                   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7654                   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7655                   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7656                   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7657                grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7658                                                GRBM_SOFT_RESET, SOFT_RESET_CP,
7659                                                1);
7660                grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7661                                                GRBM_SOFT_RESET, SOFT_RESET_GFX,
7662                                                1);
7663        }
7664
7665        if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7666                grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7667                                                GRBM_SOFT_RESET, SOFT_RESET_CP,
7668                                                1);
7669        }
7670
7671        /* GRBM_STATUS2 */
7672        tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7673        switch (adev->asic_type) {
7674        case CHIP_SIENNA_CICHLID:
7675        case CHIP_NAVY_FLOUNDER:
7676        case CHIP_VANGOGH:
7677        case CHIP_DIMGREY_CAVEFISH:
7678        case CHIP_BEIGE_GOBY:
7679        case CHIP_YELLOW_CARP:
7680                if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7681                        grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7682                                                        GRBM_SOFT_RESET,
7683                                                        SOFT_RESET_RLC,
7684                                                        1);
7685                break;
7686        default:
7687                if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7688                        grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7689                                                        GRBM_SOFT_RESET,
7690                                                        SOFT_RESET_RLC,
7691                                                        1);
7692                break;
7693        }
7694
7695        if (grbm_soft_reset) {
7696                /* stop the rlc */
7697                gfx_v10_0_rlc_stop(adev);
7698
7699                /* Disable GFX parsing/prefetching */
7700                gfx_v10_0_cp_gfx_enable(adev, false);
7701
7702                /* Disable MEC parsing/prefetching */
7703                gfx_v10_0_cp_compute_enable(adev, false);
7704
7705                if (grbm_soft_reset) {
7706                        tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7707                        tmp |= grbm_soft_reset;
7708                        dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7709                        WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7710                        tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7711
7712                        udelay(50);
7713
7714                        tmp &= ~grbm_soft_reset;
7715                        WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7716                        tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7717                }
7718
7719                /* Wait a little for things to settle down */
7720                udelay(50);
7721        }
7722        return 0;
7723}
7724
7725static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7726{
7727        uint64_t clock, clock_lo, clock_hi, hi_check;
7728
7729        switch (adev->asic_type) {
7730        case CHIP_VANGOGH:
7731        case CHIP_YELLOW_CARP:
7732                clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7733                        ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7734                break;
7735        default:
7736                preempt_disable();
7737                clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7738                clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7739                hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7740                /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7741                 * roughly every 42 seconds.
7742                 */
7743                if (hi_check != clock_hi) {
7744                        clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7745                        clock_hi = hi_check;
7746                }
7747                preempt_enable();
7748                clock = clock_lo | (clock_hi << 32ULL);
7749                break;
7750        }
7751        return clock;
7752}
7753
7754static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7755                                           uint32_t vmid,
7756                                           uint32_t gds_base, uint32_t gds_size,
7757                                           uint32_t gws_base, uint32_t gws_size,
7758                                           uint32_t oa_base, uint32_t oa_size)
7759{
7760        struct amdgpu_device *adev = ring->adev;
7761
7762        /* GDS Base */
7763        gfx_v10_0_write_data_to_reg(ring, 0, false,
7764                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7765                                    gds_base);
7766
7767        /* GDS Size */
7768        gfx_v10_0_write_data_to_reg(ring, 0, false,
7769                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7770                                    gds_size);
7771
7772        /* GWS */
7773        gfx_v10_0_write_data_to_reg(ring, 0, false,
7774                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7775                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7776
7777        /* OA */
7778        gfx_v10_0_write_data_to_reg(ring, 0, false,
7779                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7780                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
7781}
7782
7783static int gfx_v10_0_early_init(void *handle)
7784{
7785        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7786
7787        switch (adev->asic_type) {
7788        case CHIP_NAVI10:
7789        case CHIP_NAVI14:
7790        case CHIP_NAVI12:
7791        case CHIP_CYAN_SKILLFISH:
7792                adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7793                break;
7794        case CHIP_SIENNA_CICHLID:
7795        case CHIP_NAVY_FLOUNDER:
7796        case CHIP_VANGOGH:
7797        case CHIP_DIMGREY_CAVEFISH:
7798        case CHIP_BEIGE_GOBY:
7799        case CHIP_YELLOW_CARP:
7800                adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7801                break;
7802        default:
7803                break;
7804        }
7805
7806        adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7807                                          AMDGPU_MAX_COMPUTE_RINGS);
7808
7809        gfx_v10_0_set_kiq_pm4_funcs(adev);
7810        gfx_v10_0_set_ring_funcs(adev);
7811        gfx_v10_0_set_irq_funcs(adev);
7812        gfx_v10_0_set_gds_init(adev);
7813        gfx_v10_0_set_rlc_funcs(adev);
7814
7815        return 0;
7816}
7817
7818static int gfx_v10_0_late_init(void *handle)
7819{
7820        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7821        int r;
7822
7823        r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7824        if (r)
7825                return r;
7826
7827        r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7828        if (r)
7829                return r;
7830
7831        return 0;
7832}
7833
7834static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7835{
7836        uint32_t rlc_cntl;
7837
7838        /* if RLC is not enabled, do nothing */
7839        rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7840        return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7841}
7842
7843static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7844{
7845        uint32_t data;
7846        unsigned i;
7847
7848        data = RLC_SAFE_MODE__CMD_MASK;
7849        data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7850
7851        switch (adev->asic_type) {
7852        case CHIP_SIENNA_CICHLID:
7853        case CHIP_NAVY_FLOUNDER:
7854        case CHIP_VANGOGH:
7855        case CHIP_DIMGREY_CAVEFISH:
7856        case CHIP_BEIGE_GOBY:
7857        case CHIP_YELLOW_CARP:
7858                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7859
7860                /* wait for RLC_SAFE_MODE */
7861                for (i = 0; i < adev->usec_timeout; i++) {
7862                        if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7863                                           RLC_SAFE_MODE, CMD))
7864                                break;
7865                        udelay(1);
7866                }
7867                break;
7868        default:
7869                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7870
7871                /* wait for RLC_SAFE_MODE */
7872                for (i = 0; i < adev->usec_timeout; i++) {
7873                        if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7874                                           RLC_SAFE_MODE, CMD))
7875                                break;
7876                        udelay(1);
7877                }
7878                break;
7879        }
7880}
7881
7882static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7883{
7884        uint32_t data;
7885
7886        data = RLC_SAFE_MODE__CMD_MASK;
7887        switch (adev->asic_type) {
7888        case CHIP_SIENNA_CICHLID:
7889        case CHIP_NAVY_FLOUNDER:
7890        case CHIP_VANGOGH:
7891        case CHIP_DIMGREY_CAVEFISH:
7892        case CHIP_BEIGE_GOBY:
7893        case CHIP_YELLOW_CARP:
7894                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7895                break;
7896        default:
7897                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7898                break;
7899        }
7900}
7901
7902static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7903                                                      bool enable)
7904{
7905        uint32_t data, def;
7906
7907        if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7908                return;
7909
7910        /* It is disabled by HW by default */
7911        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7912                /* 0 - Disable some blocks' MGCG */
7913                WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7914                WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7915                WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7916                WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7917
7918                /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7919                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7920                data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7921                          RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7922                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7923                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7924                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7925                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7926
7927                if (def != data)
7928                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7929
7930                /* MGLS is a global flag to control all MGLS in GFX */
7931                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7932                        /* 2 - RLC memory Light sleep */
7933                        if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7934                                def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7935                                data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7936                                if (def != data)
7937                                        WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7938                        }
7939                        /* 3 - CP memory Light sleep */
7940                        if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7941                                def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7942                                data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7943                                if (def != data)
7944                                        WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7945                        }
7946                }
7947        } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7948                /* 1 - MGCG_OVERRIDE */
7949                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7950                data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7951                         RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7952                         RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7953                         RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7954                         RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7955                         RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7956                if (def != data)
7957                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7958
7959                /* 2 - disable MGLS in CP */
7960                data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7961                if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7962                        data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7963                        WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7964                }
7965
7966                /* 3 - disable MGLS in RLC */
7967                data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7968                if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7969                        data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7970                        WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7971                }
7972
7973        }
7974}
7975
7976static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7977                                           bool enable)
7978{
7979        uint32_t data, def;
7980
7981        if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7982                return;
7983
7984        /* Enable 3D CGCG/CGLS */
7985        if (enable) {
7986                /* write cmd to clear cgcg/cgls ov */
7987                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7988
7989                /* unset CGCG override */
7990                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7991                        data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7992
7993                /* update CGCG and CGLS override bits */
7994                if (def != data)
7995                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7996
7997                /* enable 3Dcgcg FSM(0x0000363f) */
7998                def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7999                data = 0;
8000

8001                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8002                        data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8003                                RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8004
8005                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8006                        data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8007                                RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8008
8009                if (def != data)
8010                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8011
8012                /* set IDLE_POLL_COUNT(0x00900100) */
8013                def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8014                data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8015                        (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8016                if (def != data)
8017                        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8018        } else {
8019                /* Disable CGCG/CGLS */
8020                def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8021
8022                /* disable cgcg, cgls should be disabled */
8023                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8024                        data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8025
8026                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8027                        data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8028
8029                /* disable cgcg and cgls in FSM */
8030                if (def != data)
8031                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8032        }
8033}
8034
8035static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8036                                                      bool enable)
8037{
8038        uint32_t def, data;
8039
8040        if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8041                return;
8042
8043        if (enable) {
8044                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8045
8046                /* unset CGCG override */
8047                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8048                        data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8049
8050                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8051                        data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8052
8053                /* update CGCG and CGLS override bits */
8054                if (def != data)
8055                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8056
8057                /* enable cgcg FSM(0x0000363F) */
8058                def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8059                data = 0;
8060
8061                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8062                        data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8063                                RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8064
8065                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8066                        data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8067                                RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8068
8069                if (def != data)
8070                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8071
8072                /* set IDLE_POLL_COUNT(0x00900100) */
8073                def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8074                data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8075                        (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8076                if (def != data)
8077                        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8078        } else {
8079                def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8080
8081                /* reset CGCG/CGLS bits */
8082                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8083                        data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8084
8085                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8086                        data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8087
8088                /* disable cgcg and cgls in FSM */
8089                if (def != data)
8090                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8091        }
8092}
8093
8094static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8095                                                      bool enable)
8096{
8097        uint32_t def, data;
8098
8099        if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8100                return;
8101
8102        if (enable) {
8103                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8104                /* unset FGCG override */
8105                data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8106                /* update FGCG override bits */
8107                if (def != data)
8108                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8109
8110                def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8111                /* unset RLC SRAM CLK GATER override */
8112                data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8113                /* update RLC SRAM CLK GATER override bits */
8114                if (def != data)
8115                        WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8116        } else {
8117                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8118                /* reset FGCG bits */
8119                data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8120                /* disable FGCG*/
8121                if (def != data)
8122                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8123
8124                def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8125                /* reset RLC SRAM CLK GATER bits */
8126                data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8127                /* disable RLC SRAM CLK*/
8128                if (def != data)
8129                        WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8130        }
8131}
8132
8133static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8134{
8135        uint32_t reg_data = 0;
8136        uint32_t reg_idx = 0;
8137        uint32_t i;
8138
8139        const uint32_t tcp_ctrl_regs[] = {
8140                mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8141                mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8142                mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8143                mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8144                mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8145                mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8146                mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8147                mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8148                mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8149                mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8150                mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8151                mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8152                mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8153                mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8154                mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8155                mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8156                mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8157                mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8158                mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8159                mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8160                mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8161                mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8162                mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8163                mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8164        };
8165
8166        const uint32_t tcp_ctrl_regs_nv12[] = {
8167                mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8168                mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8169                mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8170                mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8171                mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8172                mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8173                mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8174                mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8175                mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8176                mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8177                mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8178                mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8179                mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8180                mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8181                mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8182                mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8183                mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8184                mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8185                mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8186                mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8187        };
8188
8189        const uint32_t sm_ctlr_regs[] = {
8190                mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8191                mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8192                mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8193                mmCGTS_SA1_QUAD1_SM_CTRL_REG
8194        };
8195
8196        if (adev->asic_type == CHIP_NAVI12) {
8197                for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8198                        reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8199                                  tcp_ctrl_regs_nv12[i];
8200                        reg_data = RREG32(reg_idx);
8201                        reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8202                        WREG32(reg_idx, reg_data);
8203                }
8204        } else {
8205                for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8206                        reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8207                                  tcp_ctrl_regs[i];
8208                        reg_data = RREG32(reg_idx);
8209                        reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8210                        WREG32(reg_idx, reg_data);
8211                }
8212        }
8213
8214        for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8215                reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8216                          sm_ctlr_regs[i];
8217                reg_data = RREG32(reg_idx);
8218                reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8219                reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8220                WREG32(reg_idx, reg_data);
8221        }
8222}
8223
8224static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8225                                            bool enable)
8226{
8227        amdgpu_gfx_rlc_enter_safe_mode(adev);
8228
8229        if (enable) {
8230                /* enable FGCG firstly*/
8231                gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8232                /* CGCG/CGLS should be enabled after MGCG/MGLS
8233                 * ===  MGCG + MGLS ===
8234                 */
8235                gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8236                /* ===  CGCG /CGLS for GFX 3D Only === */
8237                gfx_v10_0_update_3d_clock_gating(adev, enable);
8238                /* ===  CGCG + CGLS === */
8239                gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8240
8241                if ((adev->asic_type >= CHIP_NAVI10) &&
8242                     (adev->asic_type <= CHIP_NAVI12))
8243                        gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8244        } else {
8245                /* CGCG/CGLS should be disabled before MGCG/MGLS
8246                 * ===  CGCG + CGLS ===
8247                 */
8248                gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8249                /* ===  CGCG /CGLS for GFX 3D Only === */
8250                gfx_v10_0_update_3d_clock_gating(adev, enable);
8251                /* ===  MGCG + MGLS === */
8252                gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8253                /* disable fgcg at last*/
8254                gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8255        }
8256
8257        if (adev->cg_flags &
8258            (AMD_CG_SUPPORT_GFX_MGCG |
8259             AMD_CG_SUPPORT_GFX_CGLS |
8260             AMD_CG_SUPPORT_GFX_CGCG |
8261             AMD_CG_SUPPORT_GFX_3D_CGCG |
8262             AMD_CG_SUPPORT_GFX_3D_CGLS))
8263                gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8264
8265        amdgpu_gfx_rlc_exit_safe_mode(adev);
8266
8267        return 0;
8268}
8269
8270static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8271{
8272        u32 reg, data;
8273        /* not for *_SOC15 */
8274        reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8275        if (amdgpu_sriov_is_pp_one_vf(adev))
8276                data = RREG32_NO_KIQ(reg);
8277        else
8278                data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8279
8280        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8281        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8282
8283        if (amdgpu_sriov_is_pp_one_vf(adev))
8284                WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8285        else
8286                WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8287}
8288
8289static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8290                                        uint32_t offset,
8291                                        struct soc15_reg_rlcg *entries, int arr_size)
8292{
8293        int i;
8294        uint32_t reg;
8295
8296        if (!entries)
8297                return false;
8298
8299        for (i = 0; i < arr_size; i++) {
8300                const struct soc15_reg_rlcg *entry;
8301
8302                entry = &entries[i];
8303                reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8304                if (offset == reg)
8305                        return true;
8306        }
8307
8308        return false;
8309}
8310
8311static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8312{
8313        return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8314}
8315
8316static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8317{
8318        u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8319
8320        if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8321                data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8322        else
8323                data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8324
8325        WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8326
8327        /*
8328         * CGPG enablement required and the register to program the hysteresis value
8329         * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8330         * in refclk count. Note that RLC FW is modified to take 16 bits from
8331         * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8332         *
8333         * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8334         * of CGPG enablement starting point.
8335         * Power/performance team will optimize it and might give a new value later.
8336         */
8337        if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8338                switch (adev->asic_type) {
8339                case CHIP_VANGOGH:
8340                        data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8341                        WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8342                        break;
8343                case CHIP_YELLOW_CARP:
8344                        data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8345                        WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8346                        break;
8347                default:
8348                        break;
8349                }
8350        }
8351}
8352
8353static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8354{
8355        amdgpu_gfx_rlc_enter_safe_mode(adev);
8356
8357        gfx_v10_cntl_power_gating(adev, enable);
8358
8359        amdgpu_gfx_rlc_exit_safe_mode(adev);
8360}
8361
8362static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8363        .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8364        .set_safe_mode = gfx_v10_0_set_safe_mode,
8365        .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8366        .init = gfx_v10_0_rlc_init,
8367        .get_csb_size = gfx_v10_0_get_csb_size,
8368        .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8369        .resume = gfx_v10_0_rlc_resume,
8370        .stop = gfx_v10_0_rlc_stop,
8371        .reset = gfx_v10_0_rlc_reset,
8372        .start = gfx_v10_0_rlc_start,
8373        .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8374};
8375
8376static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8377        .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8378        .set_safe_mode = gfx_v10_0_set_safe_mode,
8379        .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8380        .init = gfx_v10_0_rlc_init,
8381        .get_csb_size = gfx_v10_0_get_csb_size,
8382        .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8383        .resume = gfx_v10_0_rlc_resume,
8384        .stop = gfx_v10_0_rlc_stop,
8385        .reset = gfx_v10_0_rlc_reset,
8386        .start = gfx_v10_0_rlc_start,
8387        .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8388        .sriov_wreg = gfx_v10_sriov_wreg,
8389        .sriov_rreg = gfx_v10_sriov_rreg,
8390        .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8391};
8392
8393static int gfx_v10_0_set_powergating_state(void *handle,
8394                                          enum amd_powergating_state state)
8395{
8396        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8397        bool enable = (state == AMD_PG_STATE_GATE);
8398
8399        if (amdgpu_sriov_vf(adev))
8400                return 0;
8401
8402        switch (adev->asic_type) {
8403        case CHIP_NAVI10:
8404        case CHIP_NAVI14:
8405        case CHIP_NAVI12:
8406        case CHIP_SIENNA_CICHLID:
8407        case CHIP_NAVY_FLOUNDER:
8408        case CHIP_DIMGREY_CAVEFISH:
8409        case CHIP_BEIGE_GOBY:
8410                amdgpu_gfx_off_ctrl(adev, enable);
8411                break;
8412        case CHIP_VANGOGH:
8413        case CHIP_YELLOW_CARP:
8414                gfx_v10_cntl_pg(adev, enable);
8415                amdgpu_gfx_off_ctrl(adev, enable);
8416                break;
8417        default:
8418                break;
8419        }
8420        return 0;
8421}
8422
8423static int gfx_v10_0_set_clockgating_state(void *handle,
8424                                          enum amd_clockgating_state state)
8425{
8426        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8427
8428        if (amdgpu_sriov_vf(adev))
8429                return 0;
8430
8431        switch (adev->asic_type) {
8432        case CHIP_NAVI10:
8433        case CHIP_NAVI14:
8434        case CHIP_NAVI12:
8435        case CHIP_SIENNA_CICHLID:
8436        case CHIP_NAVY_FLOUNDER:
8437        case CHIP_VANGOGH:
8438        case CHIP_DIMGREY_CAVEFISH:
8439        case CHIP_BEIGE_GOBY:
8440        case CHIP_YELLOW_CARP:
8441                gfx_v10_0_update_gfx_clock_gating(adev,
8442                                                 state == AMD_CG_STATE_GATE);
8443                break;
8444        default:
8445                break;
8446        }
8447        return 0;
8448}
8449
8450static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8451{
8452        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8453        int data;
8454
8455        /* AMD_CG_SUPPORT_GFX_FGCG */
8456        data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8457        if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8458                *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8459
8460        /* AMD_CG_SUPPORT_GFX_MGCG */
8461        data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8462        if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8463                *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8464
8465        /* AMD_CG_SUPPORT_GFX_CGCG */
8466        data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8467        if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8468                *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8469
8470        /* AMD_CG_SUPPORT_GFX_CGLS */
8471        if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8472                *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8473
8474        /* AMD_CG_SUPPORT_GFX_RLC_LS */
8475        data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8476        if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8477                *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8478
8479        /* AMD_CG_SUPPORT_GFX_CP_LS */
8480        data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8481        if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8482                *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8483
8484        /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8485        data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8486        if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8487                *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8488
8489        /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8490        if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8491                *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8492}
8493
8494static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8495{
8496        return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8497}
8498
8499static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8500{
8501        struct amdgpu_device *adev = ring->adev;
8502        u64 wptr;
8503
8504        /* XXX check if swapping is necessary on BE */
8505        if (ring->use_doorbell) {
8506                wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8507        } else {
8508                wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8509                wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8510        }
8511
8512        return wptr;
8513}
8514
8515static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8516{
8517        struct amdgpu_device *adev = ring->adev;
8518
8519        if (ring->use_doorbell) {
8520                /* XXX check if swapping is necessary on BE */
8521                atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8522                WDOORBELL64(ring->doorbell_index, ring->wptr);
8523        } else {
8524                WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8525                WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8526        }
8527}
8528
8529static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8530{
8531        return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8532}
8533
8534static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8535{
8536        u64 wptr;
8537
8538        /* XXX check if swapping is necessary on BE */
8539        if (ring->use_doorbell)
8540                wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8541        else
8542                BUG();
8543        return wptr;
8544}
8545
8546static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8547{
8548        struct amdgpu_device *adev = ring->adev;
8549
8550        /* XXX check if swapping is necessary on BE */
8551        if (ring->use_doorbell) {
8552                atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8553                WDOORBELL64(ring->doorbell_index, ring->wptr);
8554        } else {
8555                BUG(); /* only DOORBELL method supported on gfx10 now */
8556        }
8557}
8558
8559static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8560{
8561        struct amdgpu_device *adev = ring->adev;
8562        u32 ref_and_mask, reg_mem_engine;
8563        const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8564
8565        if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8566                switch (ring->me) {
8567                case 1:
8568                        ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8569                        break;
8570                case 2:
8571                        ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8572                        break;
8573                default:
8574                        return;
8575                }
8576                reg_mem_engine = 0;
8577        } else {
8578                ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8579                reg_mem_engine = 1; /* pfp */
8580        }
8581
8582        gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8583                               adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8584                               adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8585                               ref_and_mask, ref_and_mask, 0x20);
8586}
8587
8588static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8589                                       struct amdgpu_job *job,
8590                                       struct amdgpu_ib *ib,
8591                                       uint32_t flags)
8592{
8593        unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8594        u32 header, control = 0;
8595
8596        if (ib->flags & AMDGPU_IB_FLAG_CE)
8597                header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8598        else
8599                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8600
8601        control |= ib->length_dw | (vmid << 24);
8602
8603        if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8604                control |= INDIRECT_BUFFER_PRE_ENB(1);
8605
8606                if (flags & AMDGPU_IB_PREEMPTED)
8607                        control |= INDIRECT_BUFFER_PRE_RESUME(1);
8608
8609                if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8610                        gfx_v10_0_ring_emit_de_meta(ring,
8611                                    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8612        }
8613
8614        amdgpu_ring_write(ring, header);
8615        BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8616        amdgpu_ring_write(ring,
8617#ifdef __BIG_ENDIAN
8618                (2 << 0) |
8619#endif
8620                lower_32_bits(ib->gpu_addr));
8621        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8622        amdgpu_ring_write(ring, control);
8623}
8624
8625static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8626                                           struct amdgpu_job *job,
8627                                           struct amdgpu_ib *ib,
8628                                           uint32_t flags)
8629{
8630        unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8631        u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8632
8633        /* Currently, there is a high possibility to get wave ID mismatch
8634         * between ME and GDS, leading to a hw deadlock, because ME generates
8635         * different wave IDs than the GDS expects. This situation happens
8636         * randomly when at least 5 compute pipes use GDS ordered append.
8637         * The wave IDs generated by ME are also wrong after suspend/resume.
8638         * Those are probably bugs somewhere else in the kernel driver.
8639         *
8640         * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8641         * GDS to 0 for this ring (me/pipe).
8642         */
8643        if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8644                amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8645                amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8646                amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8647        }
8648
8649        amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8650        BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8651        amdgpu_ring_write(ring,
8652#ifdef __BIG_ENDIAN
8653                                (2 << 0) |
8654#endif
8655                                lower_32_bits(ib->gpu_addr));
8656        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8657        amdgpu_ring_write(ring, control);
8658}
8659
8660static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8661                                     u64 seq, unsigned flags)
8662{
8663        bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8664        bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8665
8666        /* RELEASE_MEM - flush caches, send int */
8667        amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8668        amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8669                                 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8670                                 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8671                                 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8672                                 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8673                                 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8674                                 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8675        amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8676                                 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8677
8678        /*
8679         * the address should be Qword aligned if 64bit write, Dword
8680         * aligned if only send 32bit data low (discard data high)
8681         */
8682        if (write64bit)
8683                BUG_ON(addr & 0x7);
8684        else
8685                BUG_ON(addr & 0x3);
8686        amdgpu_ring_write(ring, lower_32_bits(addr));
8687        amdgpu_ring_write(ring, upper_32_bits(addr));
8688        amdgpu_ring_write(ring, lower_32_bits(seq));
8689        amdgpu_ring_write(ring, upper_32_bits(seq));
8690        amdgpu_ring_write(ring, 0);
8691}
8692
8693static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8694{
8695        int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8696        uint32_t seq = ring->fence_drv.sync_seq;
8697        uint64_t addr = ring->fence_drv.gpu_addr;
8698
8699        gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8700                               upper_32_bits(addr), seq, 0xffffffff, 4);
8701}
8702
8703static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8704                                         unsigned vmid, uint64_t pd_addr)
8705{
8706        amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8707
8708        /* compute doesn't have PFP */
8709        if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8710                /* sync PFP to ME, otherwise we might get invalid PFP reads */
8711                amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8712                amdgpu_ring_write(ring, 0x0);
8713        }
8714}
8715
8716static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8717                                          u64 seq, unsigned int flags)
8718{
8719        struct amdgpu_device *adev = ring->adev;
8720
8721        /* we only allocate 32bit for each seq wb address */
8722        BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8723
8724        /* write fence seq to the "addr" */
8725        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8726        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8727                                 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8728        amdgpu_ring_write(ring, lower_32_bits(addr));
8729        amdgpu_ring_write(ring, upper_32_bits(addr));
8730        amdgpu_ring_write(ring, lower_32_bits(seq));
8731
8732        if (flags & AMDGPU_FENCE_FLAG_INT) {
8733                /* set register to trigger INT */
8734                amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8735                amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8736                                         WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8737                amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8738                amdgpu_ring_write(ring, 0);
8739                amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8740        }
8741}
8742
8743static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8744{
8745        amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8746        amdgpu_ring_write(ring, 0);
8747}
8748
8749static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8750                                         uint32_t flags)
8751{
8752        uint32_t dw2 = 0;
8753
8754        if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8755                gfx_v10_0_ring_emit_ce_meta(ring,
8756                                    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8757
8758        dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8759        if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8760                /* set load_global_config & load_global_uconfig */
8761                dw2 |= 0x8001;
8762                /* set load_cs_sh_regs */
8763                dw2 |= 0x01000000;
8764                /* set load_per_context_state & load_gfx_sh_regs for GFX */
8765                dw2 |= 0x10002;
8766
8767                /* set load_ce_ram if preamble presented */
8768                if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8769                        dw2 |= 0x10000000;
8770        } else {
8771                /* still load_ce_ram if this is the first time preamble presented
8772                 * although there is no context switch happens.
8773                 */
8774                if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8775                        dw2 |= 0x10000000;
8776        }
8777
8778        amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8779        amdgpu_ring_write(ring, dw2);
8780        amdgpu_ring_write(ring, 0);
8781}
8782
8783static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8784{
8785        unsigned ret;
8786
8787        amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8788        amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8789        amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8790        amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8791        ret = ring->wptr & ring->buf_mask;
8792        amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8793
8794        return ret;
8795}
8796
8797static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8798{
8799        unsigned cur;
8800        BUG_ON(offset > ring->buf_mask);
8801        BUG_ON(ring->ring[offset] != 0x55aa55aa);
8802
8803        cur = (ring->wptr - 1) & ring->buf_mask;
8804        if (likely(cur > offset))
8805                ring->ring[offset] = cur - offset;
8806        else
8807                ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8808}
8809
8810static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8811{
8812        int i, r = 0;
8813        struct amdgpu_device *adev = ring->adev;
8814        struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8815        struct amdgpu_ring *kiq_ring = &kiq->ring;
8816        unsigned long flags;
8817
8818        if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8819                return -EINVAL;
8820
8821        spin_lock_irqsave(&kiq->ring_lock, flags);
8822
8823        if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8824                spin_unlock_irqrestore(&kiq->ring_lock, flags);
8825                return -ENOMEM;
8826        }
8827
8828        /* assert preemption condition */
8829        amdgpu_ring_set_preempt_cond_exec(ring, false);
8830
8831        /* assert IB preemption, emit the trailing fence */
8832        kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8833                                   ring->trail_fence_gpu_addr,
8834                                   ++ring->trail_seq);
8835        amdgpu_ring_commit(kiq_ring);
8836
8837        spin_unlock_irqrestore(&kiq->ring_lock, flags);
8838
8839        /* poll the trailing fence */
8840        for (i = 0; i < adev->usec_timeout; i++) {
8841                if (ring->trail_seq ==
8842                    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8843                        break;
8844                udelay(1);
8845        }
8846
8847        if (i >= adev->usec_timeout) {
8848                r = -EINVAL;
8849                DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8850        }
8851
8852        /* deassert preemption condition */
8853        amdgpu_ring_set_preempt_cond_exec(ring, true);
8854        return r;
8855}
8856
8857static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8858{
8859        struct amdgpu_device *adev = ring->adev;
8860        struct v10_ce_ib_state ce_payload = {0};
8861        uint64_t csa_addr;
8862        int cnt;
8863
8864        cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8865        csa_addr = amdgpu_csa_vaddr(ring->adev);
8866
8867        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8868        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8869                                 WRITE_DATA_DST_SEL(8) |
8870                                 WR_CONFIRM) |
8871                                 WRITE_DATA_CACHE_POLICY(0));
8872        amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8873                              offsetof(struct v10_gfx_meta_data, ce_payload)));
8874        amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8875                              offsetof(struct v10_gfx_meta_data, ce_payload)));
8876
8877        if (resume)
8878                amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8879                                           offsetof(struct v10_gfx_meta_data,
8880                                                    ce_payload),
8881                                           sizeof(ce_payload) >> 2);
8882        else
8883                amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8884                                           sizeof(ce_payload) >> 2);
8885}
8886
8887static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8888{
8889        struct amdgpu_device *adev = ring->adev;
8890        struct v10_de_ib_state de_payload = {0};
8891        uint64_t csa_addr, gds_addr;
8892        int cnt;
8893
8894        csa_addr = amdgpu_csa_vaddr(ring->adev);
8895        gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8896                         PAGE_SIZE);
8897        de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8898        de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8899
8900        cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8901        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8902        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8903                                 WRITE_DATA_DST_SEL(8) |
8904                                 WR_CONFIRM) |
8905                                 WRITE_DATA_CACHE_POLICY(0));
8906        amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8907                              offsetof(struct v10_gfx_meta_data, de_payload)));
8908        amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8909                              offsetof(struct v10_gfx_meta_data, de_payload)));
8910
8911        if (resume)
8912                amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8913                                           offsetof(struct v10_gfx_meta_data,
8914                                                    de_payload),
8915                                           sizeof(de_payload) >> 2);
8916        else
8917                amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8918                                           sizeof(de_payload) >> 2);
8919}
8920
8921static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8922                                    bool secure)
8923{
8924        uint32_t v = secure ? FRAME_TMZ : 0;
8925
8926        amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8927        amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8928}
8929
8930static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8931                                     uint32_t reg_val_offs)
8932{
8933        struct amdgpu_device *adev = ring->adev;
8934
8935        amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8936        amdgpu_ring_write(ring, 0 |     /* src: register*/
8937                                (5 << 8) |      /* dst: memory */
8938                                (1 << 20));     /* write confirm */
8939        amdgpu_ring_write(ring, reg);
8940        amdgpu_ring_write(ring, 0);
8941        amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8942                                reg_val_offs * 4));
8943        amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8944                                reg_val_offs * 4));
8945}
8946
8947static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8948                                   uint32_t val)
8949{
8950        uint32_t cmd = 0;
8951
8952        switch (ring->funcs->type) {
8953        case AMDGPU_RING_TYPE_GFX:
8954                cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8955                break;
8956        case AMDGPU_RING_TYPE_KIQ:
8957                cmd = (1 << 16); /* no inc addr */
8958                break;
8959        default:
8960                cmd = WR_CONFIRM;
8961                break;
8962        }
8963        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8964        amdgpu_ring_write(ring, cmd);
8965        amdgpu_ring_write(ring, reg);
8966        amdgpu_ring_write(ring, 0);
8967        amdgpu_ring_write(ring, val);
8968}
8969
8970static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8971                                        uint32_t val, uint32_t mask)
8972{
8973        gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8974}
8975
8976static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8977                                                   uint32_t reg0, uint32_t reg1,
8978                                                   uint32_t ref, uint32_t mask)
8979{
8980        int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8981        struct amdgpu_device *adev = ring->adev;
8982        bool fw_version_ok = false;
8983
8984        fw_version_ok = adev->gfx.cp_fw_write_wait;
8985
8986        if (fw_version_ok)
8987                gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8988                                       ref, mask, 0x20);
8989        else
8990                amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8991                                                           ref, mask);
8992}
8993
8994static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8995                                         unsigned vmid)
8996{
8997        struct amdgpu_device *adev = ring->adev;
8998        uint32_t value = 0;
8999
9000        value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

9001        value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9002        value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9003        value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9004        WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9005}
9006
9007static void
9008gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9009                                      uint32_t me, uint32_t pipe,
9010                                      enum amdgpu_interrupt_state state)
9011{
9012        uint32_t cp_int_cntl, cp_int_cntl_reg;
9013
9014        if (!me) {
9015                switch (pipe) {
9016                case 0:
9017                        cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9018                        break;
9019                case 1:
9020                        cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9021                        break;
9022                default:
9023                        DRM_DEBUG("invalid pipe %d\n", pipe);
9024                        return;
9025                }
9026        } else {
9027                DRM_DEBUG("invalid me %d\n", me);
9028                return;
9029        }
9030
9031        switch (state) {
9032        case AMDGPU_IRQ_STATE_DISABLE:
9033                cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9034                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9035                                            TIME_STAMP_INT_ENABLE, 0);
9036                WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9037                break;
9038        case AMDGPU_IRQ_STATE_ENABLE:
9039                cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9040                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9041                                            TIME_STAMP_INT_ENABLE, 1);
9042                WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9043                break;
9044        default:
9045                break;
9046        }
9047}
9048
9049static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9050                                                     int me, int pipe,
9051                                                     enum amdgpu_interrupt_state state)
9052{
9053        u32 mec_int_cntl, mec_int_cntl_reg;
9054
9055        /*
9056         * amdgpu controls only the first MEC. That's why this function only
9057         * handles the setting of interrupts for this specific MEC. All other
9058         * pipes' interrupts are set by amdkfd.
9059         */
9060
9061        if (me == 1) {
9062                switch (pipe) {
9063                case 0:
9064                        mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9065                        break;
9066                case 1:
9067                        mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9068                        break;
9069                case 2:
9070                        mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9071                        break;
9072                case 3:
9073                        mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9074                        break;
9075                default:
9076                        DRM_DEBUG("invalid pipe %d\n", pipe);
9077                        return;
9078                }
9079        } else {
9080                DRM_DEBUG("invalid me %d\n", me);
9081                return;
9082        }
9083
9084        switch (state) {
9085        case AMDGPU_IRQ_STATE_DISABLE:
9086                mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9087                mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9088                                             TIME_STAMP_INT_ENABLE, 0);
9089                WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9090                break;
9091        case AMDGPU_IRQ_STATE_ENABLE:
9092                mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9093                mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9094                                             TIME_STAMP_INT_ENABLE, 1);
9095                WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9096                break;
9097        default:
9098                break;
9099        }
9100}
9101
9102static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9103                                            struct amdgpu_irq_src *src,
9104                                            unsigned type,
9105                                            enum amdgpu_interrupt_state state)
9106{
9107        switch (type) {
9108        case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9109                gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9110                break;
9111        case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9112                gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9113                break;
9114        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9115                gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9116                break;
9117        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9118                gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9119                break;
9120        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9121                gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9122                break;
9123        case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9124                gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9125                break;
9126        case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9127                gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9128                break;
9129        case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9130                gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9131                break;
9132        case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9133                gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9134                break;
9135        case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9136                gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9137                break;
9138        default:
9139                break;
9140        }
9141        return 0;
9142}
9143
9144static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9145                             struct amdgpu_irq_src *source,
9146                             struct amdgpu_iv_entry *entry)
9147{
9148        int i;
9149        u8 me_id, pipe_id, queue_id;
9150        struct amdgpu_ring *ring;
9151
9152        DRM_DEBUG("IH: CP EOP\n");
9153        me_id = (entry->ring_id & 0x0c) >> 2;
9154        pipe_id = (entry->ring_id & 0x03) >> 0;
9155        queue_id = (entry->ring_id & 0x70) >> 4;
9156
9157        switch (me_id) {
9158        case 0:
9159                if (pipe_id == 0)
9160                        amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9161                else
9162                        amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9163                break;
9164        case 1:
9165        case 2:
9166                for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9167                        ring = &adev->gfx.compute_ring[i];
9168                        /* Per-queue interrupt is supported for MEC starting from VI.
9169                          * The interrupt can only be enabled/disabled per pipe instead of per queue.
9170                          */
9171                        if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
9172                                amdgpu_fence_process(ring);
9173                }
9174                break;
9175        }
9176        return 0;
9177}
9178
9179static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9180                                              struct amdgpu_irq_src *source,
9181                                              unsigned type,
9182                                              enum amdgpu_interrupt_state state)
9183{
9184        switch (state) {
9185        case AMDGPU_IRQ_STATE_DISABLE:
9186        case AMDGPU_IRQ_STATE_ENABLE:
9187                WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9188                               PRIV_REG_INT_ENABLE,
9189                               state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9190                break;
9191        default:
9192                break;
9193        }
9194
9195        return 0;
9196}
9197
9198static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9199                                               struct amdgpu_irq_src *source,
9200                                               unsigned type,
9201                                               enum amdgpu_interrupt_state state)
9202{
9203        switch (state) {
9204        case AMDGPU_IRQ_STATE_DISABLE:
9205        case AMDGPU_IRQ_STATE_ENABLE:
9206                WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9207                               PRIV_INSTR_INT_ENABLE,
9208                               state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9209                break;
9210        default:
9211                break;
9212        }
9213
9214        return 0;
9215}
9216
9217static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9218                                        struct amdgpu_iv_entry *entry)
9219{
9220        u8 me_id, pipe_id, queue_id;
9221        struct amdgpu_ring *ring;
9222        int i;
9223
9224        me_id = (entry->ring_id & 0x0c) >> 2;
9225        pipe_id = (entry->ring_id & 0x03) >> 0;
9226        queue_id = (entry->ring_id & 0x70) >> 4;
9227
9228        switch (me_id) {
9229        case 0:
9230                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9231                        ring = &adev->gfx.gfx_ring[i];
9232                        /* we only enabled 1 gfx queue per pipe for now */
9233                        if (ring->me == me_id && ring->pipe == pipe_id)
9234                                drm_sched_fault(&ring->sched);
9235                }
9236                break;
9237        case 1:
9238        case 2:
9239                for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9240                        ring = &adev->gfx.compute_ring[i];
9241                        if (ring->me == me_id && ring->pipe == pipe_id &&
9242                            ring->queue == queue_id)
9243                                drm_sched_fault(&ring->sched);
9244                }
9245                break;
9246        default:
9247                BUG();
9248        }
9249}
9250
9251static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9252                                  struct amdgpu_irq_src *source,
9253                                  struct amdgpu_iv_entry *entry)
9254{
9255        DRM_ERROR("Illegal register access in command stream\n");
9256        gfx_v10_0_handle_priv_fault(adev, entry);
9257        return 0;
9258}
9259
9260static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9261                                   struct amdgpu_irq_src *source,
9262                                   struct amdgpu_iv_entry *entry)
9263{
9264        DRM_ERROR("Illegal instruction in command stream\n");
9265        gfx_v10_0_handle_priv_fault(adev, entry);
9266        return 0;
9267}
9268
9269static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9270                                             struct amdgpu_irq_src *src,
9271                                             unsigned int type,
9272                                             enum amdgpu_interrupt_state state)
9273{
9274        uint32_t tmp, target;
9275        struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9276
9277        if (ring->me == 1)
9278                target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9279        else
9280                target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9281        target += ring->pipe;
9282
9283        switch (type) {
9284        case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9285                if (state == AMDGPU_IRQ_STATE_DISABLE) {
9286                        tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9287                        tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9288                                            GENERIC2_INT_ENABLE, 0);
9289                        WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9290
9291                        tmp = RREG32_SOC15_IP(GC, target);
9292                        tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9293                                            GENERIC2_INT_ENABLE, 0);
9294                        WREG32_SOC15_IP(GC, target, tmp);
9295                } else {
9296                        tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9297                        tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9298                                            GENERIC2_INT_ENABLE, 1);
9299                        WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9300
9301                        tmp = RREG32_SOC15_IP(GC, target);
9302                        tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9303                                            GENERIC2_INT_ENABLE, 1);
9304                        WREG32_SOC15_IP(GC, target, tmp);
9305                }
9306                break;
9307        default:
9308                BUG(); /* kiq only support GENERIC2_INT now */
9309                break;
9310        }
9311        return 0;
9312}
9313
9314static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9315                             struct amdgpu_irq_src *source,
9316                             struct amdgpu_iv_entry *entry)
9317{
9318        u8 me_id, pipe_id, queue_id;
9319        struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9320
9321        me_id = (entry->ring_id & 0x0c) >> 2;
9322        pipe_id = (entry->ring_id & 0x03) >> 0;
9323        queue_id = (entry->ring_id & 0x70) >> 4;
9324        DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9325                   me_id, pipe_id, queue_id);
9326
9327        amdgpu_fence_process(ring);
9328        return 0;
9329}
9330
9331static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9332{
9333        const unsigned int gcr_cntl =
9334                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9335                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9336                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9337                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9338                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9339                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9340                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9341                        PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9342
9343        /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9344        amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9345        amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9346        amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9347        amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9348        amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9349        amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9350        amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9351        amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9352}
9353
9354static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9355        .name = "gfx_v10_0",
9356        .early_init = gfx_v10_0_early_init,
9357        .late_init = gfx_v10_0_late_init,
9358        .sw_init = gfx_v10_0_sw_init,
9359        .sw_fini = gfx_v10_0_sw_fini,
9360        .hw_init = gfx_v10_0_hw_init,
9361        .hw_fini = gfx_v10_0_hw_fini,
9362        .suspend = gfx_v10_0_suspend,
9363        .resume = gfx_v10_0_resume,
9364        .is_idle = gfx_v10_0_is_idle,
9365        .wait_for_idle = gfx_v10_0_wait_for_idle,
9366        .soft_reset = gfx_v10_0_soft_reset,
9367        .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9368        .set_powergating_state = gfx_v10_0_set_powergating_state,
9369        .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9370};
9371
9372static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9373        .type = AMDGPU_RING_TYPE_GFX,
9374        .align_mask = 0xff,
9375        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9376        .support_64bit_ptrs = true,
9377        .vmhub = AMDGPU_GFXHUB_0,
9378        .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9379        .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9380        .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9381        .emit_frame_size = /* totally 242 maximum if 16 IBs */
9382                5 + /* COND_EXEC */
9383                7 + /* PIPELINE_SYNC */
9384                SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9385                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9386                2 + /* VM_FLUSH */
9387                8 + /* FENCE for VM_FLUSH */
9388                20 + /* GDS switch */
9389                4 + /* double SWITCH_BUFFER,
9390                     * the first COND_EXEC jump to the place
9391                     * just prior to this double SWITCH_BUFFER
9392                     */
9393                5 + /* COND_EXEC */
9394                7 + /* HDP_flush */
9395                4 + /* VGT_flush */
9396                14 + /* CE_META */
9397                31 + /* DE_META */
9398                3 + /* CNTX_CTRL */
9399                5 + /* HDP_INVL */
9400                8 + 8 + /* FENCE x2 */
9401                2 + /* SWITCH_BUFFER */
9402                8, /* gfx_v10_0_emit_mem_sync */
9403        .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9404        .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9405        .emit_fence = gfx_v10_0_ring_emit_fence,
9406        .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9407        .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9408        .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9409        .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9410        .test_ring = gfx_v10_0_ring_test_ring,
9411        .test_ib = gfx_v10_0_ring_test_ib,
9412        .insert_nop = amdgpu_ring_insert_nop,
9413        .pad_ib = amdgpu_ring_generic_pad_ib,
9414        .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9415        .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9416        .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9417        .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9418        .preempt_ib = gfx_v10_0_ring_preempt_ib,
9419        .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9420        .emit_wreg = gfx_v10_0_ring_emit_wreg,
9421        .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9422        .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9423        .soft_recovery = gfx_v10_0_ring_soft_recovery,
9424        .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9425};
9426
9427static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9428        .type = AMDGPU_RING_TYPE_COMPUTE,
9429        .align_mask = 0xff,
9430        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9431        .support_64bit_ptrs = true,
9432        .vmhub = AMDGPU_GFXHUB_0,
9433        .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9434        .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9435        .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9436        .emit_frame_size =
9437                20 + /* gfx_v10_0_ring_emit_gds_switch */
9438                7 + /* gfx_v10_0_ring_emit_hdp_flush */
9439                5 + /* hdp invalidate */
9440                7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9441                SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9442                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9443                2 + /* gfx_v10_0_ring_emit_vm_flush */
9444                8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9445                8, /* gfx_v10_0_emit_mem_sync */
9446        .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9447        .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9448        .emit_fence = gfx_v10_0_ring_emit_fence,
9449        .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9450        .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9451        .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9452        .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9453        .test_ring = gfx_v10_0_ring_test_ring,
9454        .test_ib = gfx_v10_0_ring_test_ib,
9455        .insert_nop = amdgpu_ring_insert_nop,
9456        .pad_ib = amdgpu_ring_generic_pad_ib,
9457        .emit_wreg = gfx_v10_0_ring_emit_wreg,
9458        .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9459        .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9460        .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9461};
9462
9463static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9464        .type = AMDGPU_RING_TYPE_KIQ,
9465        .align_mask = 0xff,
9466        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9467        .support_64bit_ptrs = true,
9468        .vmhub = AMDGPU_GFXHUB_0,
9469        .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9470        .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9471        .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9472        .emit_frame_size =
9473                20 + /* gfx_v10_0_ring_emit_gds_switch */
9474                7 + /* gfx_v10_0_ring_emit_hdp_flush */
9475                5 + /*hdp invalidate */
9476                7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9477                SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9478                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9479                2 + /* gfx_v10_0_ring_emit_vm_flush */
9480                8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9481        .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9482        .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9483        .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9484        .test_ring = gfx_v10_0_ring_test_ring,
9485        .test_ib = gfx_v10_0_ring_test_ib,
9486        .insert_nop = amdgpu_ring_insert_nop,
9487        .pad_ib = amdgpu_ring_generic_pad_ib,
9488        .emit_rreg = gfx_v10_0_ring_emit_rreg,
9489        .emit_wreg = gfx_v10_0_ring_emit_wreg,
9490        .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9491        .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9492};
9493
9494static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9495{
9496        int i;
9497
9498        adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9499
9500        for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9501                adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9502
9503        for (i = 0; i < adev->gfx.num_compute_rings; i++)
9504                adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9505}
9506
9507static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9508        .set = gfx_v10_0_set_eop_interrupt_state,
9509        .process = gfx_v10_0_eop_irq,
9510};
9511
9512static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9513        .set = gfx_v10_0_set_priv_reg_fault_state,
9514        .process = gfx_v10_0_priv_reg_irq,
9515};
9516
9517static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9518        .set = gfx_v10_0_set_priv_inst_fault_state,
9519        .process = gfx_v10_0_priv_inst_irq,
9520};
9521
9522static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9523        .set = gfx_v10_0_kiq_set_interrupt_state,
9524        .process = gfx_v10_0_kiq_irq,
9525};
9526
9527static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9528{
9529        adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9530        adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9531
9532        adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9533        adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9534
9535        adev->gfx.priv_reg_irq.num_types = 1;
9536        adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9537
9538        adev->gfx.priv_inst_irq.num_types = 1;
9539        adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9540}
9541
9542static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9543{
9544        switch (adev->asic_type) {
9545        case CHIP_NAVI10:
9546        case CHIP_NAVI14:
9547        case CHIP_NAVY_FLOUNDER:
9548        case CHIP_VANGOGH:
9549        case CHIP_DIMGREY_CAVEFISH:
9550        case CHIP_BEIGE_GOBY:
9551        case CHIP_YELLOW_CARP:
9552        case CHIP_CYAN_SKILLFISH:
9553                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9554                break;
9555        case CHIP_NAVI12:
9556        case CHIP_SIENNA_CICHLID:
9557                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9558                break;
9559        default:
9560                break;
9561        }
9562}
9563
9564static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9565{
9566        unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9567                            adev->gfx.config.max_sh_per_se *
9568                            adev->gfx.config.max_shader_engines;
9569
9570        adev->gds.gds_size = 0x10000;
9571        adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9572        adev->gds.gws_size = 64;
9573        adev->gds.oa_size = 16;
9574}
9575
9576static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9577                                                          u32 bitmap)
9578{
9579        u32 data;
9580
9581        if (!bitmap)
9582                return;
9583
9584        data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9585        data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9586
9587        WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9588}
9589
9590static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9591{
9592        u32 disabled_mask =
9593                ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9594        u32 efuse_setting = 0;
9595        u32 vbios_setting = 0;
9596
9597        efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9598        efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9599        efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9600
9601        vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9602        vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9603        vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9604
9605        disabled_mask |= efuse_setting | vbios_setting;
9606
9607        return (~disabled_mask);
9608}
9609
9610static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9611{
9612        u32 wgp_idx, wgp_active_bitmap;
9613        u32 cu_bitmap_per_wgp, cu_active_bitmap;
9614
9615        wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9616        cu_active_bitmap = 0;
9617
9618        for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9619                /* if there is one WGP enabled, it means 2 CUs will be enabled */
9620                cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9621                if (wgp_active_bitmap & (1 << wgp_idx))
9622                        cu_active_bitmap |= cu_bitmap_per_wgp;
9623        }
9624
9625        return cu_active_bitmap;
9626}
9627
9628static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9629                                 struct amdgpu_cu_info *cu_info)
9630{
9631        int i, j, k, counter, active_cu_number = 0;
9632        u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9633        unsigned disable_masks[4 * 2];
9634
9635        if (!adev || !cu_info)
9636                return -EINVAL;
9637
9638        amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9639
9640        mutex_lock(&adev->grbm_idx_mutex);
9641        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9642                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9643                        bitmap = i * adev->gfx.config.max_sh_per_se + j;
9644                        if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
9645                                (adev->asic_type == CHIP_YELLOW_CARP)) &&
9646                            ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9647                                continue;
9648                        mask = 1;
9649                        ao_bitmap = 0;
9650                        counter = 0;
9651                        gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9652                        if (i < 4 && j < 2)
9653                                gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9654                                        adev, disable_masks[i * 2 + j]);
9655                        bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9656                        cu_info->bitmap[i][j] = bitmap;
9657
9658                        for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9659                                if (bitmap & mask) {
9660                                        if (counter < adev->gfx.config.max_cu_per_sh)
9661                                                ao_bitmap |= mask;
9662                                        counter++;
9663                                }
9664                                mask <<= 1;
9665                        }
9666                        active_cu_number += counter;
9667                        if (i < 2 && j < 2)
9668                                ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9669                        cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9670                }
9671        }
9672        gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9673        mutex_unlock(&adev->grbm_idx_mutex);
9674
9675        cu_info->number = active_cu_number;
9676        cu_info->ao_cu_mask = ao_cu_mask;
9677        cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9678
9679        return 0;
9680}
9681
9682static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9683{
9684        uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9685
9686        efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9687        efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9688        efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9689
9690        vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9691        vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9692        vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9693
9694        max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9695                                                adev->gfx.config.max_shader_engines);
9696        disabled_sa = efuse_setting | vbios_setting;
9697        disabled_sa &= max_sa_mask;
9698
9699        return disabled_sa;
9700}
9701
9702static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9703{
9704        uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9705        uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9706
9707        disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9708
9709        max_sa_per_se = adev->gfx.config.max_sh_per_se;
9710        max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9711        max_shader_engines = adev->gfx.config.max_shader_engines;
9712
9713        for (se_index = 0; max_shader_engines > se_index; se_index++) {
9714                disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9715                disabled_sa_per_se &= max_sa_per_se_mask;
9716                if (disabled_sa_per_se == max_sa_per_se_mask) {
9717                        WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9718                        break;
9719                }
9720        }
9721}
9722
9723static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9724{
9725        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9726                     (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9727                     (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9728                     (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9729
9730        WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9731        WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9732                     (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9733                     (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9734                     (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9735                     (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9736
9737        WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9738                     (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9739                     (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9740                     (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9741
9742        WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9743
9744        WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9745                     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9746}
9747
9748const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9749{
9750        .type = AMD_IP_BLOCK_TYPE_GFX,
9751        .major = 10,
9752        .minor = 0,
9753        .rev = 0,
9754        .funcs = &gfx_v10_0_ip_funcs,
9755};
9756