LXR linux/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw

   1/*
   2* Copyright 2016-2020 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DC_HWSS_DCN10_H__
  27#define __DC_HWSS_DCN10_H__
  28
  29#include "core_types.h"
  30#include "hw_sequencer_private.h"
  31
  32struct dc;
  33
  34void dcn10_hw_sequencer_construct(struct dc *dc);
  35
  36int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
  37void dcn10_calc_vupdate_position(
  38                struct dc *dc,
  39                struct pipe_ctx *pipe_ctx,
  40                uint32_t *start_line,
  41                uint32_t *end_line);
  42void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
  43enum dc_status dcn10_enable_stream_timing(
  44                struct pipe_ctx *pipe_ctx,
  45                struct dc_state *context,
  46                struct dc *dc);
  47void dcn10_optimize_bandwidth(
  48                struct dc *dc,
  49                struct dc_state *context);
  50void dcn10_prepare_bandwidth(
  51                struct dc *dc,
  52                struct dc_state *context);
  53void dcn10_pipe_control_lock(
  54        struct dc *dc,
  55        struct pipe_ctx *pipe,
  56        bool lock);
  57void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
  58void dcn10_blank_pixel_data(
  59                struct dc *dc,
  60                struct pipe_ctx *pipe_ctx,
  61                bool blank);
  62void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
  63                struct dc_link_settings *link_settings);
  64void dcn10_program_output_csc(struct dc *dc,
  65                struct pipe_ctx *pipe_ctx,
  66                enum dc_color_space colorspace,
  67                uint16_t *matrix,
  68                int opp_id);
  69bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  70                                const struct dc_stream_state *stream);
  71bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  72                        const struct dc_plane_state *plane_state);
  73void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
  74void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
  75void dcn10_reset_hw_ctx_wrap(
  76                struct dc *dc,
  77                struct dc_state *context);
  78void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
  79void dcn10_lock_all_pipes(
  80                struct dc *dc,
  81                struct dc_state *context,
  82                bool lock);
  83void dcn10_post_unlock_program_front_end(
  84                struct dc *dc,
  85                struct dc_state *context);
  86void dcn10_hubp_pg_control(
  87                struct dce_hwseq *hws,
  88                unsigned int hubp_inst,
  89                bool power_on);
  90void dcn10_dpp_pg_control(
  91                struct dce_hwseq *hws,
  92                unsigned int dpp_inst,
  93                bool power_on);
  94void dcn10_enable_power_gating_plane(
  95        struct dce_hwseq *hws,
  96        bool enable);
  97void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
  98void dcn10_disable_vga(
  99        struct dce_hwseq *hws);
 100void dcn10_program_pipe(
 101                struct dc *dc,
 102                struct pipe_ctx *pipe_ctx,
 103                struct dc_state *context);
 104void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
 105void dcn10_init_hw(struct dc *dc);
 106void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
 107void dcn10_power_down_on_boot(struct dc *dc);
 108enum dc_status dce110_apply_ctx_to_hw(
 109                struct dc *dc,
 110                struct dc_state *context);
 111void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
 112void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
 113void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);
 114void dce110_power_down(struct dc *dc);
 115void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
 116void dcn10_enable_timing_synchronization(
 117                struct dc *dc,
 118                int group_index,
 119                int group_size,
 120                struct pipe_ctx *grouped_pipes[]);
 121void dcn10_enable_vblanks_synchronization(
 122                struct dc *dc,
 123                int group_index,
 124                int group_size,
 125                struct pipe_ctx *grouped_pipes[]);
 126void dcn10_enable_per_frame_crtc_position_reset(
 127                struct dc *dc,
 128                int group_size,
 129                struct pipe_ctx *grouped_pipes[]);
 130void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
 131void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
 132                const uint8_t *custom_sdp_message,
 133                unsigned int sdp_message_size);
 134void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
 135void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
 136void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
 137bool dcn10_dummy_display_power_gating(
 138                struct dc *dc,
 139                uint8_t controller_id,
 140                struct dc_bios *dcb,
 141                enum pipe_gating_control power_gating);
 142void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
 143                int num_pipes, struct dc_crtc_timing_adjust adjust);
 144void dcn10_get_position(struct pipe_ctx **pipe_ctx,
 145                int num_pipes,
 146                struct crtc_position *position);
 147void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
 148                int num_pipes, const struct dc_static_screen_params *params);
 149void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
 150void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
 151void dcn10_log_hw_state(struct dc *dc,
 152                struct dc_log_buffer_ctx *log_ctx);
 153void dcn10_get_hw_state(struct dc *dc,
 154                char *pBuf,
 155                unsigned int bufSize,
 156                unsigned int mask);
 157void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
 158void dcn10_wait_for_mpcc_disconnect(
 159                struct dc *dc,
 160                struct resource_pool *res_pool,
 161                struct pipe_ctx *pipe_ctx);
 162void dce110_edp_backlight_control(
 163                struct dc_link *link,
 164                bool enable);
 165void dce110_edp_wait_for_T12(
 166                struct dc_link *link);
 167void dce110_edp_power_control(
 168                struct dc_link *link,
 169                bool power_up);
 170void dce110_edp_wait_for_hpd_ready(
 171                struct dc_link *link,
 172                bool power_up);
 173void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);
 174void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
 175void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
 176void dcn10_setup_periodic_interrupt(
 177                struct dc *dc,
 178                struct pipe_ctx *pipe_ctx,
 179                enum vline_select vline);
 180enum dc_status dcn10_set_clock(struct dc *dc,
 181                enum dc_clock_type clock_type,
 182                uint32_t clk_khz,
 183                uint32_t stepping);
 184void dcn10_get_clock(struct dc *dc,
 185                enum dc_clock_type clock_type,
 186                struct dc_clock_config *clock_cfg);
 187bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
 188void dcn10_bios_golden_init(struct dc *dc);
 189void dcn10_plane_atomic_power_down(struct dc *dc,
 190                struct dpp *dpp,
 191                struct hubp *hubp);
 192bool dcn10_disconnect_pipes(
 193                struct dc *dc,
 194                struct dc_state *context);
 195
 196void dcn10_wait_for_pending_cleared(struct dc *dc,
 197                struct dc_state *context);
 198void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
 199void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 200
 201void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
 202
 203void dcn10_update_visual_confirm_color(
 204                struct dc *dc,
 205                struct pipe_ctx *pipe_ctx,
 206                struct tg_color *color,
 207                int mpcc_id);
 208
 209#endif /* __DC_HWSS_DCN10_H__ */
 210