LXR linux/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer

   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DC_HW_SEQUENCER_PRIVATE_H__
  27#define __DC_HW_SEQUENCER_PRIVATE_H__
  28
  29#include "dc_types.h"
  30
  31enum pipe_gating_control {
  32        PIPE_GATING_CONTROL_DISABLE = 0,
  33        PIPE_GATING_CONTROL_ENABLE,
  34        PIPE_GATING_CONTROL_INIT
  35};
  36
  37struct dce_hwseq_wa {
  38        bool blnd_crtc_trigger;
  39        bool DEGVIDCN10_253;
  40        bool false_optc_underflow;
  41        bool DEGVIDCN10_254;
  42        bool DEGVIDCN21;
  43        bool disallow_self_refresh_during_multi_plane_transition;
  44};
  45
  46struct hwseq_wa_state {
  47        bool DEGVIDCN10_253_applied;
  48        bool disallow_self_refresh_during_multi_plane_transition_applied;
  49        unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
  50};
  51
  52struct pipe_ctx;
  53struct dc_state;
  54struct dc_stream_status;
  55struct dc_writeback_info;
  56struct dchub_init_data;
  57struct dc_static_screen_params;
  58struct resource_pool;
  59struct resource_context;
  60struct stream_resource;
  61struct dc_phy_addr_space_config;
  62struct dc_virtual_addr_space_config;
  63struct hubp;
  64struct dpp;
  65struct dce_hwseq;
  66struct timing_generator;
  67struct tg_color;
  68struct output_pixel_processor;
  69
  70struct hwseq_private_funcs {
  71
  72        void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  73        void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  74        void (*init_pipes)(struct dc *dc, struct dc_state *context);
  75        void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
  76        void (*update_plane_addr)(const struct dc *dc,
  77                        struct pipe_ctx *pipe_ctx);
  78        void (*plane_atomic_disconnect)(struct dc *dc,
  79                        struct pipe_ctx *pipe_ctx);
  80        void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  81        bool (*set_input_transfer_func)(struct dc *dc,
  82                                struct pipe_ctx *pipe_ctx,
  83                                const struct dc_plane_state *plane_state);
  84        bool (*set_output_transfer_func)(struct dc *dc,
  85                                struct pipe_ctx *pipe_ctx,
  86                                const struct dc_stream_state *stream);
  87        void (*power_down)(struct dc *dc);
  88        void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
  89                                        bool clock_gating);
  90        bool (*enable_display_power_gating)(struct dc *dc,
  91                                        uint8_t controller_id,
  92                                        struct dc_bios *dcb,
  93                                        enum pipe_gating_control power_gating);
  94        void (*blank_pixel_data)(struct dc *dc,
  95                        struct pipe_ctx *pipe_ctx,
  96                        bool blank);
  97        enum dc_status (*enable_stream_timing)(
  98                        struct pipe_ctx *pipe_ctx,
  99                        struct dc_state *context,
 100                        struct dc *dc);
 101        void (*edp_backlight_control)(struct dc_link *link,
 102                        bool enable);
 103        void (*setup_vupdate_interrupt)(struct dc *dc,
 104                        struct pipe_ctx *pipe_ctx);
 105        bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 106        void (*init_blank)(struct dc *dc, struct timing_generator *tg);
 107        void (*disable_vga)(struct dce_hwseq *hws);
 108        void (*bios_golden_init)(struct dc *dc);
 109        void (*plane_atomic_power_down)(struct dc *dc,
 110                        struct dpp *dpp,
 111                        struct hubp *hubp);
 112        void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 113        void (*enable_power_gating_plane)(struct dce_hwseq *hws,
 114                bool enable);
 115        void (*dpp_pg_control)(struct dce_hwseq *hws,
 116                        unsigned int dpp_inst,
 117                        bool power_on);
 118        void (*hubp_pg_control)(struct dce_hwseq *hws,
 119                        unsigned int hubp_inst,
 120                        bool power_on);
 121        void (*dsc_pg_control)(struct dce_hwseq *hws,
 122                        unsigned int dsc_inst,
 123                        bool power_on);
 124        void (*update_odm)(struct dc *dc, struct dc_state *context,
 125                        struct pipe_ctx *pipe_ctx);
 126        void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
 127                        const struct dc_stream_state *stream,
 128                        struct dc_state *context);
 129        bool (*s0i3_golden_init_wa)(struct dc *dc);
 130        void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
 131        void (*verify_allow_pstate_change_high)(struct dc *dc);
 132        void (*program_pipe)(struct dc *dc,
 133                        struct pipe_ctx *pipe_ctx,
 134                        struct dc_state *context);
 135        bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
 136        void (*dccg_init)(struct dce_hwseq *hws);
 137        bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
 138                        const struct dc_plane_state *plane_state);
 139        bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
 140                        const struct dc_plane_state *plane_state);
 141        void (*PLAT_58856_wa)(struct dc_state *context,
 142                        struct pipe_ctx *pipe_ctx);
 143};
 144
 145struct dce_hwseq {
 146        struct dc_context *ctx;
 147        const struct dce_hwseq_registers *regs;
 148        const struct dce_hwseq_shift *shifts;
 149        const struct dce_hwseq_mask *masks;
 150        struct dce_hwseq_wa wa;
 151        struct hwseq_wa_state wa_state;
 152        struct hwseq_private_funcs funcs;
 153
 154};
 155
 156#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */
 157