1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31#include <linux/export.h>
32#include <linux/pci.h>
33
34#include <drm/drm_atomic.h>
35#include <drm/drm_atomic_helper.h>
36#include <drm/drm_atomic_state_helper.h>
37#include <drm/drm_crtc.h>
38#include <drm/drm_crtc_helper.h>
39#include <drm/drm_fourcc.h>
40#include <drm/drm_gem_atomic_helper.h>
41#include <drm/drm_gem_framebuffer_helper.h>
42#include <drm/drm_gem_vram_helper.h>
43#include <drm/drm_plane_helper.h>
44#include <drm/drm_probe_helper.h>
45#include <drm/drm_simple_kms_helper.h>
46
47#include "ast_drv.h"
48#include "ast_tables.h"
49
50static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
51static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
52
53static inline void ast_load_palette_index(struct ast_private *ast,
54 u8 index, u8 red, u8 green,
55 u8 blue)
56{
57 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, red);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61 ast_io_write8(ast, AST_IO_DAC_DATA, green);
62 ast_io_read8(ast, AST_IO_SEQ_PORT);
63 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
64 ast_io_read8(ast, AST_IO_SEQ_PORT);
65}
66
67static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
68{
69 u16 *r, *g, *b;
70 int i;
71
72 if (!crtc->enabled)
73 return;
74
75 r = crtc->gamma_store;
76 g = r + crtc->gamma_size;
77 b = g + crtc->gamma_size;
78
79 for (i = 0; i < 256; i++)
80 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
81}
82
83static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
84 const struct drm_display_mode *mode,
85 struct drm_display_mode *adjusted_mode,
86 struct ast_vbios_mode_info *vbios_mode)
87{
88 u32 refresh_rate_index = 0, refresh_rate;
89 const struct ast_vbios_enhtable *best = NULL;
90 u32 hborder, vborder;
91 bool check_sync;
92
93 switch (format->cpp[0] * 8) {
94 case 8:
95 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
96 break;
97 case 16:
98 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
99 break;
100 case 24:
101 case 32:
102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
103 break;
104 default:
105 return false;
106 }
107
108 switch (mode->crtc_hdisplay) {
109 case 640:
110 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
111 break;
112 case 800:
113 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
114 break;
115 case 1024:
116 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
117 break;
118 case 1280:
119 if (mode->crtc_vdisplay == 800)
120 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
121 else
122 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
123 break;
124 case 1360:
125 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
126 break;
127 case 1440:
128 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
129 break;
130 case 1600:
131 if (mode->crtc_vdisplay == 900)
132 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
133 else
134 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
135 break;
136 case 1680:
137 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
138 break;
139 case 1920:
140 if (mode->crtc_vdisplay == 1080)
141 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
142 else
143 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
144 break;
145 default:
146 return false;
147 }
148
149 refresh_rate = drm_mode_vrefresh(mode);
150 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
151
152 while (1) {
153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
154
155 while (loop->refresh_rate != 0xff) {
156 if ((check_sync) &&
157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
158 (loop->flags & PVSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
160 (loop->flags & NVSync)) ||
161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
162 (loop->flags & PHSync)) ||
163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
164 (loop->flags & NHSync)))) {
165 loop++;
166 continue;
167 }
168 if (loop->refresh_rate <= refresh_rate
169 && (!best || loop->refresh_rate > best->refresh_rate))
170 best = loop;
171 loop++;
172 }
173 if (best || !check_sync)
174 break;
175 check_sync = 0;
176 }
177
178 if (best)
179 vbios_mode->enh_table = best;
180
181 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
182 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
183
184 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
185 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
186 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
187 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
188 vbios_mode->enh_table->hfp;
189 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
190 vbios_mode->enh_table->hfp +
191 vbios_mode->enh_table->hsync);
192
193 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
194 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
195 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
196 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
197 vbios_mode->enh_table->vfp;
198 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
199 vbios_mode->enh_table->vfp +
200 vbios_mode->enh_table->vsync);
201
202 return true;
203}
204
205static void ast_set_vbios_color_reg(struct ast_private *ast,
206 const struct drm_format_info *format,
207 const struct ast_vbios_mode_info *vbios_mode)
208{
209 u32 color_index;
210
211 switch (format->cpp[0]) {
212 case 1:
213 color_index = VGAModeIndex - 1;
214 break;
215 case 2:
216 color_index = HiCModeIndex;
217 break;
218 case 3:
219 case 4:
220 color_index = TrueCModeIndex;
221 break;
222 default:
223 return;
224 }
225
226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
227
228 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
229
230 if (vbios_mode->enh_table->flags & NewModeInfo) {
231 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
232 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
233 }
234}
235
236static void ast_set_vbios_mode_reg(struct ast_private *ast,
237 const struct drm_display_mode *adjusted_mode,
238 const struct ast_vbios_mode_info *vbios_mode)
239{
240 u32 refresh_rate_index, mode_id;
241
242 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
243 mode_id = vbios_mode->enh_table->mode_id;
244
245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
247
248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
249
250 if (vbios_mode->enh_table->flags & NewModeInfo) {
251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
257 }
258}
259
260static void ast_set_std_reg(struct ast_private *ast,
261 struct drm_display_mode *mode,
262 struct ast_vbios_mode_info *vbios_mode)
263{
264 const struct ast_vbios_stdtable *stdtable;
265 u32 i;
266 u8 jreg;
267
268 stdtable = vbios_mode->std_table;
269
270 jreg = stdtable->misc;
271 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
272
273
274 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
275 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
276 for (i = 1; i < 4; i++) {
277 jreg = stdtable->seq[i];
278 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1), jreg);
279 }
280
281
282 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
283 for (i = 0; i < 12; i++)
284 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
285 for (i = 14; i < 19; i++)
286 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
287 for (i = 20; i < 25; i++)
288 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
289
290
291 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
292 for (i = 0; i < 20; i++) {
293 jreg = stdtable->ar[i];
294 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
295 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
296 }
297 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
298 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
299
300 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
301 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
302
303
304 for (i = 0; i < 9; i++)
305 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
306}
307
308static void ast_set_crtc_reg(struct ast_private *ast,
309 struct drm_display_mode *mode,
310 struct ast_vbios_mode_info *vbios_mode)
311{
312 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
313 u16 temp, precache = 0;
314
315 if ((ast->chip == AST2500) &&
316 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
317 precache = 40;
318
319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
320
321 temp = (mode->crtc_htotal >> 3) - 5;
322 if (temp & 0x100)
323 jregAC |= 0x01;
324 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
325
326 temp = (mode->crtc_hdisplay >> 3) - 1;
327 if (temp & 0x100)
328 jregAC |= 0x04;
329 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
330
331 temp = (mode->crtc_hblank_start >> 3) - 1;
332 if (temp & 0x100)
333 jregAC |= 0x10;
334 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
335
336 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
337 if (temp & 0x20)
338 jreg05 |= 0x80;
339 if (temp & 0x40)
340 jregAD |= 0x01;
341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
342
343 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
344 if (temp & 0x100)
345 jregAC |= 0x40;
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
347
348 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
349 if (temp & 0x20)
350 jregAD |= 0x04;
351 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
352
353 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
355
356
357 temp = (mode->crtc_vtotal) - 2;
358 if (temp & 0x100)
359 jreg07 |= 0x01;
360 if (temp & 0x200)
361 jreg07 |= 0x20;
362 if (temp & 0x400)
363 jregAE |= 0x01;
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
365
366 temp = (mode->crtc_vsync_start) - 1;
367 if (temp & 0x100)
368 jreg07 |= 0x04;
369 if (temp & 0x200)
370 jreg07 |= 0x80;
371 if (temp & 0x400)
372 jregAE |= 0x08;
373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
374
375 temp = (mode->crtc_vsync_end - 1) & 0x3f;
376 if (temp & 0x10)
377 jregAE |= 0x20;
378 if (temp & 0x20)
379 jregAE |= 0x40;
380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
381
382 temp = mode->crtc_vdisplay - 1;
383 if (temp & 0x100)
384 jreg07 |= 0x02;
385 if (temp & 0x200)
386 jreg07 |= 0x40;
387 if (temp & 0x400)
388 jregAE |= 0x02;
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
390
391 temp = mode->crtc_vblank_start - 1;
392 if (temp & 0x100)
393 jreg07 |= 0x08;
394 if (temp & 0x200)
395 jreg09 |= 0x20;
396 if (temp & 0x400)
397 jregAE |= 0x04;
398 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
399
400 temp = mode->crtc_vblank_end - 1;
401 if (temp & 0x100)
402 jregAE |= 0x10;
403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
404
405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
408
409 if (precache)
410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
411 else
412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
413
414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
415}
416
417static void ast_set_offset_reg(struct ast_private *ast,
418 struct drm_framebuffer *fb)
419{
420 u16 offset;
421
422 offset = fb->pitches[0] >> 3;
423 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
424 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
425}
426
427static void ast_set_dclk_reg(struct ast_private *ast,
428 struct drm_display_mode *mode,
429 struct ast_vbios_mode_info *vbios_mode)
430{
431 const struct ast_vbios_dclk_info *clk_info;
432
433 if (ast->chip == AST2500)
434 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
435 else
436 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
437
438 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
441 (clk_info->param3 & 0xc0) |
442 ((clk_info->param3 & 0x3) << 4));
443}
444
445static void ast_set_color_reg(struct ast_private *ast,
446 const struct drm_format_info *format)
447{
448 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
449
450 switch (format->cpp[0] * 8) {
451 case 8:
452 jregA0 = 0x70;
453 jregA3 = 0x01;
454 jregA8 = 0x00;
455 break;
456 case 15:
457 case 16:
458 jregA0 = 0x70;
459 jregA3 = 0x04;
460 jregA8 = 0x02;
461 break;
462 case 32:
463 jregA0 = 0x70;
464 jregA3 = 0x08;
465 jregA8 = 0x02;
466 break;
467 }
468
469 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
470 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
471 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
472}
473
474static void ast_set_crtthd_reg(struct ast_private *ast)
475{
476
477 if (ast->chip == AST2300 || ast->chip == AST2400 ||
478 ast->chip == AST2500) {
479 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
480 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
481 } else if (ast->chip == AST2100 ||
482 ast->chip == AST1100 ||
483 ast->chip == AST2200 ||
484 ast->chip == AST2150) {
485 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
487 } else {
488 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
489 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
490 }
491}
492
493static void ast_set_sync_reg(struct ast_private *ast,
494 struct drm_display_mode *mode,
495 struct ast_vbios_mode_info *vbios_mode)
496{
497 u8 jreg;
498
499 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
500 jreg &= ~0xC0;
501 if (vbios_mode->enh_table->flags & NVSync)
502 jreg |= 0x80;
503 if (vbios_mode->enh_table->flags & NHSync)
504 jreg |= 0x40;
505 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
506}
507
508static void ast_set_start_address_crt1(struct ast_private *ast,
509 unsigned int offset)
510{
511 u32 addr;
512
513 addr = offset >> 2;
514 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
515 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
516 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
517
518}
519
520static void ast_wait_for_vretrace(struct ast_private *ast)
521{
522 unsigned long timeout = jiffies + HZ;
523 u8 vgair1;
524
525 do {
526 vgair1 = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
527 } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
528}
529
530
531
532
533
534static const uint32_t ast_primary_plane_formats[] = {
535 DRM_FORMAT_XRGB8888,
536 DRM_FORMAT_RGB565,
537 DRM_FORMAT_C8,
538};
539
540static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
541 struct drm_atomic_state *state)
542{
543 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
544 plane);
545 struct drm_crtc_state *crtc_state;
546 struct ast_crtc_state *ast_crtc_state;
547 int ret;
548
549 if (!new_plane_state->crtc)
550 return 0;
551
552 crtc_state = drm_atomic_get_new_crtc_state(state,
553 new_plane_state->crtc);
554
555 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
556 DRM_PLANE_HELPER_NO_SCALING,
557 DRM_PLANE_HELPER_NO_SCALING,
558 false, true);
559 if (ret)
560 return ret;
561
562 if (!new_plane_state->visible)
563 return 0;
564
565 ast_crtc_state = to_ast_crtc_state(crtc_state);
566
567 ast_crtc_state->format = new_plane_state->fb->format;
568
569 return 0;
570}
571
572static void
573ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
574 struct drm_atomic_state *state)
575{
576 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
577 plane);
578 struct drm_device *dev = plane->dev;
579 struct ast_private *ast = to_ast_private(dev);
580 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
581 plane);
582 struct drm_gem_vram_object *gbo;
583 s64 gpu_addr;
584 struct drm_framebuffer *fb = new_state->fb;
585 struct drm_framebuffer *old_fb = old_state->fb;
586
587 if (!old_fb || (fb->format != old_fb->format)) {
588 struct drm_crtc_state *crtc_state = new_state->crtc->state;
589 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
590 struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
591
592 ast_set_color_reg(ast, fb->format);
593 ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info);
594 }
595
596 gbo = drm_gem_vram_of_gem(fb->obj[0]);
597 gpu_addr = drm_gem_vram_offset(gbo);
598 if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
599 return;
600
601 ast_set_offset_reg(ast, fb);
602 ast_set_start_address_crt1(ast, (u32)gpu_addr);
603
604 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
605}
606
607static void
608ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
609 struct drm_atomic_state *state)
610{
611 struct ast_private *ast = to_ast_private(plane->dev);
612
613 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
614}
615
616static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
617 DRM_GEM_VRAM_PLANE_HELPER_FUNCS,
618 .atomic_check = ast_primary_plane_helper_atomic_check,
619 .atomic_update = ast_primary_plane_helper_atomic_update,
620 .atomic_disable = ast_primary_plane_helper_atomic_disable,
621};
622
623static const struct drm_plane_funcs ast_primary_plane_funcs = {
624 .update_plane = drm_atomic_helper_update_plane,
625 .disable_plane = drm_atomic_helper_disable_plane,
626 .destroy = drm_plane_cleanup,
627 .reset = drm_atomic_helper_plane_reset,
628 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
629 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
630};
631
632static int ast_primary_plane_init(struct ast_private *ast)
633{
634 struct drm_device *dev = &ast->base;
635 struct drm_plane *primary_plane = &ast->primary_plane;
636 int ret;
637
638 ret = drm_universal_plane_init(dev, primary_plane, 0x01,
639 &ast_primary_plane_funcs,
640 ast_primary_plane_formats,
641 ARRAY_SIZE(ast_primary_plane_formats),
642 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
643 if (ret) {
644 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
645 return ret;
646 }
647 drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs);
648
649 return 0;
650}
651
652
653
654
655
656static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height)
657{
658 union {
659 u32 ul;
660 u8 b[4];
661 } srcdata32[2], data32;
662 union {
663 u16 us;
664 u8 b[2];
665 } data16;
666 u32 csum = 0;
667 s32 alpha_dst_delta, last_alpha_dst_delta;
668 u8 __iomem *dstxor;
669 const u8 *srcxor;
670 int i, j;
671 u32 per_pixel_copy, two_pixel_copy;
672
673 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
674 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
675
676 srcxor = src;
677 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
678 per_pixel_copy = width & 1;
679 two_pixel_copy = width >> 1;
680
681 for (j = 0; j < height; j++) {
682 for (i = 0; i < two_pixel_copy; i++) {
683 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
684 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
685 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
686 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
687 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
688 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
689
690 writel(data32.ul, dstxor);
691 csum += data32.ul;
692
693 dstxor += 4;
694 srcxor += 8;
695
696 }
697
698 for (i = 0; i < per_pixel_copy; i++) {
699 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
700 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
701 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
702 writew(data16.us, dstxor);
703 csum += (u32)data16.us;
704
705 dstxor += 2;
706 srcxor += 4;
707 }
708 dstxor += last_alpha_dst_delta;
709 }
710
711
712 dst += AST_HWC_SIZE;
713 writel(csum, dst);
714 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
715 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
716 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
717 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
718}
719
720static void ast_set_cursor_base(struct ast_private *ast, u64 address)
721{
722 u8 addr0 = (address >> 3) & 0xff;
723 u8 addr1 = (address >> 11) & 0xff;
724 u8 addr2 = (address >> 19) & 0xff;
725
726 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
727 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
728 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
729}
730
731static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y,
732 u8 x_offset, u8 y_offset)
733{
734 u8 x0 = (x & 0x00ff);
735 u8 x1 = (x & 0x0f00) >> 8;
736 u8 y0 = (y & 0x00ff);
737 u8 y1 = (y & 0x0700) >> 8;
738
739 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
740 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
741 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0);
742 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1);
743 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0);
744 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1);
745}
746
747static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled)
748{
749 static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP |
750 AST_IO_VGACRCB_HWC_ENABLED);
751
752 u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP;
753
754 if (enabled)
755 vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED;
756
757 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb);
758}
759
760static const uint32_t ast_cursor_plane_formats[] = {
761 DRM_FORMAT_ARGB8888,
762};
763
764static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
765 struct drm_atomic_state *state)
766{
767 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
768 plane);
769 struct drm_framebuffer *fb = new_plane_state->fb;
770 struct drm_crtc_state *crtc_state;
771 int ret;
772
773 if (!new_plane_state->crtc)
774 return 0;
775
776 crtc_state = drm_atomic_get_new_crtc_state(state,
777 new_plane_state->crtc);
778
779 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
780 DRM_PLANE_HELPER_NO_SCALING,
781 DRM_PLANE_HELPER_NO_SCALING,
782 true, true);
783 if (ret)
784 return ret;
785
786 if (!new_plane_state->visible)
787 return 0;
788
789 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
790 return -EINVAL;
791
792 return 0;
793}
794
795static void
796ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
797 struct drm_atomic_state *state)
798{
799 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
800 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
801 plane);
802 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
803 plane);
804 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state);
805 struct drm_framebuffer *fb = new_state->fb;
806 struct ast_private *ast = to_ast_private(plane->dev);
807 struct dma_buf_map dst_map =
808 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map;
809 u64 dst_off =
810 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off;
811 struct dma_buf_map src_map = shadow_plane_state->data[0];
812 unsigned int offset_x, offset_y;
813 u16 x, y;
814 u8 x_offset, y_offset;
815 u8 __iomem *dst;
816 u8 __iomem *sig;
817 const u8 *src;
818
819 src = src_map.vaddr;
820 dst = dst_map.vaddr_iomem;
821 sig = dst + AST_HWC_SIZE;
822
823
824
825
826
827
828 ast_update_cursor_image(dst, src, fb->width, fb->height);
829
830 if (new_state->fb != old_state->fb) {
831 ast_set_cursor_base(ast, dst_off);
832
833 ++ast_cursor_plane->next_hwc_index;
834 ast_cursor_plane->next_hwc_index %= ARRAY_SIZE(ast_cursor_plane->hwc);
835 }
836
837
838
839
840
841 writel(new_state->crtc_x, sig + AST_HWC_SIGNATURE_X);
842 writel(new_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
843
844 offset_x = AST_MAX_HWC_WIDTH - fb->width;
845 offset_y = AST_MAX_HWC_HEIGHT - fb->height;
846
847 if (new_state->crtc_x < 0) {
848 x_offset = (-new_state->crtc_x) + offset_x;
849 x = 0;
850 } else {
851 x_offset = offset_x;
852 x = new_state->crtc_x;
853 }
854 if (new_state->crtc_y < 0) {
855 y_offset = (-new_state->crtc_y) + offset_y;
856 y = 0;
857 } else {
858 y_offset = offset_y;
859 y = new_state->crtc_y;
860 }
861
862 ast_set_cursor_location(ast, x, y, x_offset, y_offset);
863
864
865 ast_set_cursor_enabled(ast, true);
866}
867
868static void
869ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
870 struct drm_atomic_state *state)
871{
872 struct ast_private *ast = to_ast_private(plane->dev);
873
874 ast_set_cursor_enabled(ast, false);
875}
876
877static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
878 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
879 .atomic_check = ast_cursor_plane_helper_atomic_check,
880 .atomic_update = ast_cursor_plane_helper_atomic_update,
881 .atomic_disable = ast_cursor_plane_helper_atomic_disable,
882};
883
884static void ast_cursor_plane_destroy(struct drm_plane *plane)
885{
886 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
887 size_t i;
888 struct drm_gem_vram_object *gbo;
889 struct dma_buf_map map;
890
891 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
892 gbo = ast_cursor_plane->hwc[i].gbo;
893 map = ast_cursor_plane->hwc[i].map;
894 drm_gem_vram_vunmap(gbo, &map);
895 drm_gem_vram_unpin(gbo);
896 drm_gem_vram_put(gbo);
897 }
898
899 drm_plane_cleanup(plane);
900}
901
902static const struct drm_plane_funcs ast_cursor_plane_funcs = {
903 .update_plane = drm_atomic_helper_update_plane,
904 .disable_plane = drm_atomic_helper_disable_plane,
905 .destroy = ast_cursor_plane_destroy,
906 DRM_GEM_SHADOW_PLANE_FUNCS,
907};
908
909static int ast_cursor_plane_init(struct ast_private *ast)
910{
911 struct drm_device *dev = &ast->base;
912 struct ast_cursor_plane *ast_cursor_plane = &ast->cursor_plane;
913 struct drm_plane *cursor_plane = &ast_cursor_plane->base;
914 size_t size, i;
915 struct drm_gem_vram_object *gbo;
916 struct dma_buf_map map;
917 int ret;
918 s64 off;
919
920
921
922
923
924
925 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
926
927 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
928 gbo = drm_gem_vram_create(dev, size, 0);
929 if (IS_ERR(gbo)) {
930 ret = PTR_ERR(gbo);
931 goto err_hwc;
932 }
933 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
934 DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
935 if (ret)
936 goto err_drm_gem_vram_put;
937 ret = drm_gem_vram_vmap(gbo, &map);
938 if (ret)
939 goto err_drm_gem_vram_unpin;
940 off = drm_gem_vram_offset(gbo);
941 if (off < 0) {
942 ret = off;
943 goto err_drm_gem_vram_vunmap;
944 }
945 ast_cursor_plane->hwc[i].gbo = gbo;
946 ast_cursor_plane->hwc[i].map = map;
947 ast_cursor_plane->hwc[i].off = off;
948 }
949
950
951
952
953
954
955 ret = drm_universal_plane_init(dev, cursor_plane, 0x01,
956 &ast_cursor_plane_funcs,
957 ast_cursor_plane_formats,
958 ARRAY_SIZE(ast_cursor_plane_formats),
959 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
960 if (ret) {
961 drm_err(dev, "drm_universal_plane failed(): %d\n", ret);
962 goto err_hwc;
963 }
964 drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs);
965
966 return 0;
967
968err_hwc:
969 while (i) {
970 --i;
971 gbo = ast_cursor_plane->hwc[i].gbo;
972 map = ast_cursor_plane->hwc[i].map;
973err_drm_gem_vram_vunmap:
974 drm_gem_vram_vunmap(gbo, &map);
975err_drm_gem_vram_unpin:
976 drm_gem_vram_unpin(gbo);
977err_drm_gem_vram_put:
978 drm_gem_vram_put(gbo);
979 }
980 return ret;
981}
982
983
984
985
986
987static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
988{
989 struct ast_private *ast = to_ast_private(crtc->dev);
990
991
992
993
994 switch (mode) {
995 case DRM_MODE_DPMS_ON:
996 case DRM_MODE_DPMS_STANDBY:
997 case DRM_MODE_DPMS_SUSPEND:
998 if (ast->tx_chip_type == AST_TX_DP501)
999 ast_set_dp501_video_output(crtc->dev, 1);
1000 break;
1001 case DRM_MODE_DPMS_OFF:
1002 if (ast->tx_chip_type == AST_TX_DP501)
1003 ast_set_dp501_video_output(crtc->dev, 0);
1004 break;
1005 }
1006}
1007
1008static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
1009 struct drm_atomic_state *state)
1010{
1011 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1012 crtc);
1013 struct drm_device *dev = crtc->dev;
1014 struct ast_crtc_state *ast_state;
1015 const struct drm_format_info *format;
1016 bool succ;
1017
1018 if (!crtc_state->enable)
1019 return 0;
1020
1021 ast_state = to_ast_crtc_state(crtc_state);
1022
1023 format = ast_state->format;
1024 if (drm_WARN_ON_ONCE(dev, !format))
1025 return -EINVAL;
1026
1027 succ = ast_get_vbios_mode_info(format, &crtc_state->mode,
1028 &crtc_state->adjusted_mode,
1029 &ast_state->vbios_mode_info);
1030 if (!succ)
1031 return -EINVAL;
1032
1033 return 0;
1034}
1035
1036static void
1037ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
1038 struct drm_atomic_state *state)
1039{
1040 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1041 crtc);
1042 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1043 crtc);
1044 struct ast_private *ast = to_ast_private(crtc->dev);
1045 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1046 struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
1047
1048
1049
1050
1051
1052 if (old_ast_crtc_state->format != ast_crtc_state->format)
1053 ast_crtc_load_lut(ast, crtc);
1054}
1055
1056static void
1057ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
1058 struct drm_atomic_state *state)
1059{
1060 struct drm_device *dev = crtc->dev;
1061 struct ast_private *ast = to_ast_private(dev);
1062 struct drm_crtc_state *crtc_state = crtc->state;
1063 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1064 struct ast_vbios_mode_info *vbios_mode_info =
1065 &ast_crtc_state->vbios_mode_info;
1066 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1067
1068 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
1069 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
1070 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
1071 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
1072 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
1073 ast_set_crtthd_reg(ast);
1074 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
1075
1076 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1077}
1078
1079static void
1080ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
1081 struct drm_atomic_state *state)
1082{
1083 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1084 crtc);
1085 struct drm_device *dev = crtc->dev;
1086 struct ast_private *ast = to_ast_private(dev);
1087
1088 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1101
1102
1103
1104
1105
1106 ast_wait_for_vretrace(ast);
1107}
1108
1109static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
1110 .atomic_check = ast_crtc_helper_atomic_check,
1111 .atomic_flush = ast_crtc_helper_atomic_flush,
1112 .atomic_enable = ast_crtc_helper_atomic_enable,
1113 .atomic_disable = ast_crtc_helper_atomic_disable,
1114};
1115
1116static void ast_crtc_reset(struct drm_crtc *crtc)
1117{
1118 struct ast_crtc_state *ast_state =
1119 kzalloc(sizeof(*ast_state), GFP_KERNEL);
1120
1121 if (crtc->state)
1122 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
1123
1124 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
1125}
1126
1127static struct drm_crtc_state *
1128ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1129{
1130 struct ast_crtc_state *new_ast_state, *ast_state;
1131 struct drm_device *dev = crtc->dev;
1132
1133 if (drm_WARN_ON(dev, !crtc->state))
1134 return NULL;
1135
1136 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
1137 if (!new_ast_state)
1138 return NULL;
1139 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
1140
1141 ast_state = to_ast_crtc_state(crtc->state);
1142
1143 new_ast_state->format = ast_state->format;
1144 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
1145 sizeof(new_ast_state->vbios_mode_info));
1146
1147 return &new_ast_state->base;
1148}
1149
1150static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1151 struct drm_crtc_state *state)
1152{
1153 struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
1154
1155 __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
1156 kfree(ast_state);
1157}
1158
1159static const struct drm_crtc_funcs ast_crtc_funcs = {
1160 .reset = ast_crtc_reset,
1161 .destroy = drm_crtc_cleanup,
1162 .set_config = drm_atomic_helper_set_config,
1163 .page_flip = drm_atomic_helper_page_flip,
1164 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
1165 .atomic_destroy_state = ast_crtc_atomic_destroy_state,
1166};
1167
1168static int ast_crtc_init(struct drm_device *dev)
1169{
1170 struct ast_private *ast = to_ast_private(dev);
1171 struct drm_crtc *crtc = &ast->crtc;
1172 int ret;
1173
1174 ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane,
1175 &ast->cursor_plane.base, &ast_crtc_funcs,
1176 NULL);
1177 if (ret)
1178 return ret;
1179
1180 drm_mode_crtc_set_gamma_size(crtc, 256);
1181 drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs);
1182
1183 return 0;
1184}
1185
1186
1187
1188
1189
1190static int ast_encoder_init(struct drm_device *dev)
1191{
1192 struct ast_private *ast = to_ast_private(dev);
1193 struct drm_encoder *encoder = &ast->encoder;
1194 int ret;
1195
1196 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
1197 if (ret)
1198 return ret;
1199
1200 encoder->possible_crtcs = 1;
1201
1202 return 0;
1203}
1204
1205
1206
1207
1208
1209static int ast_get_modes(struct drm_connector *connector)
1210{
1211 struct ast_connector *ast_connector = to_ast_connector(connector);
1212 struct ast_private *ast = to_ast_private(connector->dev);
1213 struct edid *edid;
1214 int ret;
1215 bool flags = false;
1216
1217 if (ast->tx_chip_type == AST_TX_DP501) {
1218 ast->dp501_maxclk = 0xff;
1219 edid = kmalloc(128, GFP_KERNEL);
1220 if (!edid)
1221 return -ENOMEM;
1222
1223 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1224 if (flags)
1225 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1226 else
1227 kfree(edid);
1228 }
1229 if (!flags)
1230 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1231 if (edid) {
1232 drm_connector_update_edid_property(&ast_connector->base, edid);
1233 ret = drm_add_edid_modes(connector, edid);
1234 kfree(edid);
1235 return ret;
1236 }
1237 drm_connector_update_edid_property(&ast_connector->base, NULL);
1238 return 0;
1239}
1240
1241static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1242 struct drm_display_mode *mode)
1243{
1244 struct ast_private *ast = to_ast_private(connector->dev);
1245 int flags = MODE_NOMODE;
1246 uint32_t jtemp;
1247
1248 if (ast->support_wide_screen) {
1249 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1250 return MODE_OK;
1251 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1252 return MODE_OK;
1253 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1254 return MODE_OK;
1255 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1256 return MODE_OK;
1257 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1258 return MODE_OK;
1259
1260 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1261 (ast->chip == AST2300) || (ast->chip == AST2400) ||
1262 (ast->chip == AST2500)) {
1263 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1264 return MODE_OK;
1265
1266 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1267 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1268 if (jtemp & 0x01)
1269 return MODE_NOMODE;
1270 else
1271 return MODE_OK;
1272 }
1273 }
1274 }
1275 switch (mode->hdisplay) {
1276 case 640:
1277 if (mode->vdisplay == 480)
1278 flags = MODE_OK;
1279 break;
1280 case 800:
1281 if (mode->vdisplay == 600)
1282 flags = MODE_OK;
1283 break;
1284 case 1024:
1285 if (mode->vdisplay == 768)
1286 flags = MODE_OK;
1287 break;
1288 case 1280:
1289 if (mode->vdisplay == 1024)
1290 flags = MODE_OK;
1291 break;
1292 case 1600:
1293 if (mode->vdisplay == 1200)
1294 flags = MODE_OK;
1295 break;
1296 default:
1297 return flags;
1298 }
1299
1300 return flags;
1301}
1302
1303static void ast_connector_destroy(struct drm_connector *connector)
1304{
1305 struct ast_connector *ast_connector = to_ast_connector(connector);
1306
1307 ast_i2c_destroy(ast_connector->i2c);
1308 drm_connector_cleanup(connector);
1309}
1310
1311static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1312 .get_modes = ast_get_modes,
1313 .mode_valid = ast_mode_valid,
1314};
1315
1316static const struct drm_connector_funcs ast_connector_funcs = {
1317 .reset = drm_atomic_helper_connector_reset,
1318 .fill_modes = drm_helper_probe_single_connector_modes,
1319 .destroy = ast_connector_destroy,
1320 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1321 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1322};
1323
1324static int ast_connector_init(struct drm_device *dev)
1325{
1326 struct ast_private *ast = to_ast_private(dev);
1327 struct ast_connector *ast_connector = &ast->connector;
1328 struct drm_connector *connector = &ast_connector->base;
1329 struct drm_encoder *encoder = &ast->encoder;
1330
1331 ast_connector->i2c = ast_i2c_create(dev);
1332 if (!ast_connector->i2c)
1333 drm_err(dev, "failed to add ddc bus for connector\n");
1334
1335 drm_connector_init_with_ddc(dev, connector,
1336 &ast_connector_funcs,
1337 DRM_MODE_CONNECTOR_VGA,
1338 &ast_connector->i2c->adapter);
1339
1340 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1341
1342 connector->interlace_allowed = 0;
1343 connector->doublescan_allowed = 0;
1344
1345 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1346
1347 drm_connector_attach_encoder(connector, encoder);
1348
1349 return 0;
1350}
1351
1352
1353
1354
1355
1356static const struct drm_mode_config_helper_funcs
1357ast_mode_config_helper_funcs = {
1358 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
1359};
1360
1361static const struct drm_mode_config_funcs ast_mode_config_funcs = {
1362 .fb_create = drm_gem_fb_create,
1363 .mode_valid = drm_vram_helper_mode_valid,
1364 .atomic_check = drm_atomic_helper_check,
1365 .atomic_commit = drm_atomic_helper_commit,
1366};
1367
1368int ast_mode_config_init(struct ast_private *ast)
1369{
1370 struct drm_device *dev = &ast->base;
1371 struct pci_dev *pdev = to_pci_dev(dev->dev);
1372 int ret;
1373
1374 ret = drmm_mode_config_init(dev);
1375 if (ret)
1376 return ret;
1377
1378 dev->mode_config.funcs = &ast_mode_config_funcs;
1379 dev->mode_config.min_width = 0;
1380 dev->mode_config.min_height = 0;
1381 dev->mode_config.preferred_depth = 24;
1382 dev->mode_config.prefer_shadow = 1;
1383 dev->mode_config.fb_base = pci_resource_start(pdev, 0);
1384
1385 if (ast->chip == AST2100 ||
1386 ast->chip == AST2200 ||
1387 ast->chip == AST2300 ||
1388 ast->chip == AST2400 ||
1389 ast->chip == AST2500) {
1390 dev->mode_config.max_width = 1920;
1391 dev->mode_config.max_height = 2048;
1392 } else {
1393 dev->mode_config.max_width = 1600;
1394 dev->mode_config.max_height = 1200;
1395 }
1396
1397 dev->mode_config.helper_private = &ast_mode_config_helper_funcs;
1398
1399
1400 ret = ast_primary_plane_init(ast);
1401 if (ret)
1402 return ret;
1403
1404 ret = ast_cursor_plane_init(ast);
1405 if (ret)
1406 return ret;
1407
1408 ast_crtc_init(dev);
1409 ast_encoder_init(dev);
1410 ast_connector_init(dev);
1411
1412 drm_mode_config_reset(dev);
1413
1414 return 0;
1415}
1416
1417static int get_clock(void *i2c_priv)
1418{
1419 struct ast_i2c_chan *i2c = i2c_priv;
1420 struct ast_private *ast = to_ast_private(i2c->dev);
1421 uint32_t val, val2, count, pass;
1422
1423 count = 0;
1424 pass = 0;
1425 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1426 do {
1427 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1428 if (val == val2) {
1429 pass++;
1430 } else {
1431 pass = 0;
1432 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1433 }
1434 } while ((pass < 5) && (count++ < 0x10000));
1435
1436 return val & 1 ? 1 : 0;
1437}
1438
1439static int get_data(void *i2c_priv)
1440{
1441 struct ast_i2c_chan *i2c = i2c_priv;
1442 struct ast_private *ast = to_ast_private(i2c->dev);
1443 uint32_t val, val2, count, pass;
1444
1445 count = 0;
1446 pass = 0;
1447 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1448 do {
1449 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1450 if (val == val2) {
1451 pass++;
1452 } else {
1453 pass = 0;
1454 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1455 }
1456 } while ((pass < 5) && (count++ < 0x10000));
1457
1458 return val & 1 ? 1 : 0;
1459}
1460
1461static void set_clock(void *i2c_priv, int clock)
1462{
1463 struct ast_i2c_chan *i2c = i2c_priv;
1464 struct ast_private *ast = to_ast_private(i2c->dev);
1465 int i;
1466 u8 ujcrb7, jtemp;
1467
1468 for (i = 0; i < 0x10000; i++) {
1469 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1470 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1471 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1472 if (ujcrb7 == jtemp)
1473 break;
1474 }
1475}
1476
1477static void set_data(void *i2c_priv, int data)
1478{
1479 struct ast_i2c_chan *i2c = i2c_priv;
1480 struct ast_private *ast = to_ast_private(i2c->dev);
1481 int i;
1482 u8 ujcrb7, jtemp;
1483
1484 for (i = 0; i < 0x10000; i++) {
1485 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1486 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1487 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1488 if (ujcrb7 == jtemp)
1489 break;
1490 }
1491}
1492
1493static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1494{
1495 struct ast_i2c_chan *i2c;
1496 int ret;
1497
1498 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1499 if (!i2c)
1500 return NULL;
1501
1502 i2c->adapter.owner = THIS_MODULE;
1503 i2c->adapter.class = I2C_CLASS_DDC;
1504 i2c->adapter.dev.parent = dev->dev;
1505 i2c->dev = dev;
1506 i2c_set_adapdata(&i2c->adapter, i2c);
1507 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1508 "AST i2c bit bus");
1509 i2c->adapter.algo_data = &i2c->bit;
1510
1511 i2c->bit.udelay = 20;
1512 i2c->bit.timeout = 2;
1513 i2c->bit.data = i2c;
1514 i2c->bit.setsda = set_data;
1515 i2c->bit.setscl = set_clock;
1516 i2c->bit.getsda = get_data;
1517 i2c->bit.getscl = get_clock;
1518 ret = i2c_bit_add_bus(&i2c->adapter);
1519 if (ret) {
1520 drm_err(dev, "Failed to register bit i2c\n");
1521 goto out_free;
1522 }
1523
1524 return i2c;
1525out_free:
1526 kfree(i2c);
1527 return NULL;
1528}
1529
1530static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1531{
1532 if (!i2c)
1533 return;
1534 i2c_del_adapter(&i2c->adapter);
1535 kfree(i2c);
1536}
1537
