1
2
3
4
5
6#include "i915_drv.h"
7#include "intel_ddi.h"
8#include "intel_ddi_buf_trans.h"
9#include "intel_de.h"
10#include "intel_display_types.h"
11
12
13
14
15
16static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = {
17 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
18 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
19 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
20 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
21 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
22 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
23 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
24 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
25 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
26};
27
28static const struct intel_ddi_buf_trans hsw_ddi_translations_dp = {
29 .entries = _hsw_ddi_translations_dp,
30 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_dp),
31};
32
33static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = {
34 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
35 { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } },
36 { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } },
37 { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } },
38 { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } },
39 { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } },
40 { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } },
41 { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } },
42 { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } },
43};
44
45static const struct intel_ddi_buf_trans hsw_ddi_translations_fdi = {
46 .entries = _hsw_ddi_translations_fdi,
47 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_fdi),
48};
49
50static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = {
51
52 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
53 { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } },
54 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
55 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
56 { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } },
57 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
58 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
59 { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } },
60 { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } },
61 { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } },
62 { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } },
63 { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } },
64};
65
66static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = {
67 .entries = _hsw_ddi_translations_hdmi,
68 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi),
69 .hdmi_default_entry = 6,
70};
71
72static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = {
73 { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } },
74 { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } },
75 { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } },
76 { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } },
77 { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } },
78 { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } },
79 { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } },
80 { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } },
81 { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } },
82};
83
84static const struct intel_ddi_buf_trans bdw_ddi_translations_edp = {
85 .entries = _bdw_ddi_translations_edp,
86 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_edp),
87};
88
89static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = {
90 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
91 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },
92 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },
93 { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } },
94 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },
95 { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } },
96 { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } },
97 { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } },
98 { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } },
99};
100
101static const struct intel_ddi_buf_trans bdw_ddi_translations_dp = {
102 .entries = _bdw_ddi_translations_dp,
103 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_dp),
104};
105
106static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = {
107 { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } },
108 { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } },
109 { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } },
110 { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } },
111 { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } },
112 { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } },
113 { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } },
114 { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } },
115 { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } },
116};
117
118static const struct intel_ddi_buf_trans bdw_ddi_translations_fdi = {
119 .entries = _bdw_ddi_translations_fdi,
120 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_fdi),
121};
122
123static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = {
124
125 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
126 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },
127 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },
128 { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } },
129 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },
130 { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } },
131 { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } },
132 { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } },
133 { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } },
134 { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } },
135};
136
137static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = {
138 .entries = _bdw_ddi_translations_hdmi,
139 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi),
140 .hdmi_default_entry = 7,
141};
142
143
144static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = {
145 { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
146 { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
147 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
148 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
149 { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
150 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
151 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
152 { .hsw = { 0x00002016, 0x000000DF, 0x0 } },
153 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
154};
155
156static const struct intel_ddi_buf_trans skl_ddi_translations_dp = {
157 .entries = _skl_ddi_translations_dp,
158 .num_entries = ARRAY_SIZE(_skl_ddi_translations_dp),
159};
160
161
162static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = {
163 { .hsw = { 0x0000201B, 0x000000A2, 0x0 } },
164 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
165 { .hsw = { 0x80007011, 0x000000CD, 0x1 } },
166 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
167 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
168 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
169 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
170 { .hsw = { 0x00002016, 0x00000088, 0x0 } },
171 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
172};
173
174static const struct intel_ddi_buf_trans skl_u_ddi_translations_dp = {
175 .entries = _skl_u_ddi_translations_dp,
176 .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_dp),
177};
178
179
180static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = {
181 { .hsw = { 0x00000018, 0x000000A2, 0x0 } },
182 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
183 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
184 { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
185 { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
186 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
187 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
188 { .hsw = { 0x00000018, 0x00000088, 0x0 } },
189 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
190};
191
192static const struct intel_ddi_buf_trans skl_y_ddi_translations_dp = {
193 .entries = _skl_y_ddi_translations_dp,
194 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_dp),
195};
196
197
198static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = {
199 { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
200 { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
201 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
202 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
203 { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
204 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
205 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
206 { .hsw = { 0x00002016, 0x00000097, 0x0 } },
207 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
208};
209
210static const struct intel_ddi_buf_trans kbl_ddi_translations_dp = {
211 .entries = _kbl_ddi_translations_dp,
212 .num_entries = ARRAY_SIZE(_kbl_ddi_translations_dp),
213};
214
215
216static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = {
217 { .hsw = { 0x0000201B, 0x000000A1, 0x0 } },
218 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
219 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
220 { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
221 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
222 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
223 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
224 { .hsw = { 0x00002016, 0x0000004F, 0x0 } },
225 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
226};
227
228static const struct intel_ddi_buf_trans kbl_u_ddi_translations_dp = {
229 .entries = _kbl_u_ddi_translations_dp,
230 .num_entries = ARRAY_SIZE(_kbl_u_ddi_translations_dp),
231};
232
233
234static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = {
235 { .hsw = { 0x00001017, 0x000000A1, 0x0 } },
236 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
237 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
238 { .hsw = { 0x8000800F, 0x000000C0, 0x3 } },
239 { .hsw = { 0x00001017, 0x0000009D, 0x0 } },
240 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
241 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
242 { .hsw = { 0x00001017, 0x0000004C, 0x0 } },
243 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
244};
245
246static const struct intel_ddi_buf_trans kbl_y_ddi_translations_dp = {
247 .entries = _kbl_y_ddi_translations_dp,
248 .num_entries = ARRAY_SIZE(_kbl_y_ddi_translations_dp),
249};
250
251
252
253
254
255static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = {
256 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
257 { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
258 { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
259 { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
260 { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
261 { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
262 { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
263 { .hsw = { 0x00000018, 0x000000AB, 0x0 } },
264 { .hsw = { 0x00007013, 0x0000009F, 0x0 } },
265 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
266};
267
268static const struct intel_ddi_buf_trans skl_ddi_translations_edp = {
269 .entries = _skl_ddi_translations_edp,
270 .num_entries = ARRAY_SIZE(_skl_ddi_translations_edp),
271};
272
273
274
275
276
277static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = {
278 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
279 { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
280 { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
281 { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
282 { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
283 { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
284 { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
285 { .hsw = { 0x00002016, 0x000000AB, 0x0 } },
286 { .hsw = { 0x00005013, 0x0000009F, 0x0 } },
287 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
288};
289
290static const struct intel_ddi_buf_trans skl_u_ddi_translations_edp = {
291 .entries = _skl_u_ddi_translations_edp,
292 .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_edp),
293};
294
295
296
297
298
299static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = {
300 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
301 { .hsw = { 0x00004013, 0x000000AB, 0x0 } },
302 { .hsw = { 0x00007011, 0x000000A4, 0x0 } },
303 { .hsw = { 0x00009010, 0x000000DF, 0x0 } },
304 { .hsw = { 0x00000018, 0x000000AA, 0x0 } },
305 { .hsw = { 0x00006013, 0x000000A4, 0x0 } },
306 { .hsw = { 0x00007011, 0x0000009D, 0x0 } },
307 { .hsw = { 0x00000018, 0x000000A0, 0x0 } },
308 { .hsw = { 0x00006012, 0x000000DF, 0x0 } },
309 { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
310};
311
312static const struct intel_ddi_buf_trans skl_y_ddi_translations_edp = {
313 .entries = _skl_y_ddi_translations_edp,
314 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_edp),
315};
316
317
318static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = {
319 { .hsw = { 0x00000018, 0x000000AC, 0x0 } },
320 { .hsw = { 0x00005012, 0x0000009D, 0x0 } },
321 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
322 { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
323 { .hsw = { 0x00000018, 0x00000098, 0x0 } },
324 { .hsw = { 0x00004013, 0x00000088, 0x0 } },
325 { .hsw = { 0x80006012, 0x000000CD, 0x1 } },
326 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
327 { .hsw = { 0x80003015, 0x000000CD, 0x1 } },
328 { .hsw = { 0x80003015, 0x000000C0, 0x1 } },
329 { .hsw = { 0x80000018, 0x000000C0, 0x1 } },
330};
331
332static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = {
333 .entries = _skl_ddi_translations_hdmi,
334 .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi),
335 .hdmi_default_entry = 8,
336};
337
338
339static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = {
340 { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
341 { .hsw = { 0x00005012, 0x000000DF, 0x0 } },
342 { .hsw = { 0x80007011, 0x000000CB, 0x3 } },
343 { .hsw = { 0x00000018, 0x000000A4, 0x0 } },
344 { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
345 { .hsw = { 0x00004013, 0x00000080, 0x0 } },
346 { .hsw = { 0x80006013, 0x000000C0, 0x3 } },
347 { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
348 { .hsw = { 0x80003015, 0x000000C0, 0x3 } },
349 { .hsw = { 0x80003015, 0x000000C0, 0x3 } },
350 { .hsw = { 0x80000018, 0x000000C0, 0x3 } },
351};
352
353static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = {
354 .entries = _skl_y_ddi_translations_hdmi,
355 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi),
356 .hdmi_default_entry = 8,
357};
358
359static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = {
360
361 { .bxt = { 52, 0x9A, 0, 128, } },
362 { .bxt = { 78, 0x9A, 0, 85, } },
363 { .bxt = { 104, 0x9A, 0, 64, } },
364 { .bxt = { 154, 0x9A, 0, 43, } },
365 { .bxt = { 77, 0x9A, 0, 128, } },
366 { .bxt = { 116, 0x9A, 0, 85, } },
367 { .bxt = { 154, 0x9A, 0, 64, } },
368 { .bxt = { 102, 0x9A, 0, 128, } },
369 { .bxt = { 154, 0x9A, 0, 85, } },
370 { .bxt = { 154, 0x9A, 1, 128, } },
371};
372
373static const struct intel_ddi_buf_trans bxt_ddi_translations_dp = {
374 .entries = _bxt_ddi_translations_dp,
375 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_dp),
376};
377
378static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = {
379
380 { .bxt = { 26, 0, 0, 128, } },
381 { .bxt = { 38, 0, 0, 112, } },
382 { .bxt = { 48, 0, 0, 96, } },
383 { .bxt = { 54, 0, 0, 69, } },
384 { .bxt = { 32, 0, 0, 128, } },
385 { .bxt = { 48, 0, 0, 104, } },
386 { .bxt = { 54, 0, 0, 85, } },
387 { .bxt = { 43, 0, 0, 128, } },
388 { .bxt = { 54, 0, 0, 101, } },
389 { .bxt = { 48, 0, 0, 128, } },
390};
391
392static const struct intel_ddi_buf_trans bxt_ddi_translations_edp = {
393 .entries = _bxt_ddi_translations_edp,
394 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_edp),
395};
396
397
398
399
400static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = {
401
402 { .bxt = { 52, 0x9A, 0, 128, } },
403 { .bxt = { 52, 0x9A, 0, 85, } },
404 { .bxt = { 52, 0x9A, 0, 64, } },
405 { .bxt = { 42, 0x9A, 0, 43, } },
406 { .bxt = { 77, 0x9A, 0, 128, } },
407 { .bxt = { 77, 0x9A, 0, 85, } },
408 { .bxt = { 77, 0x9A, 0, 64, } },
409 { .bxt = { 102, 0x9A, 0, 128, } },
410 { .bxt = { 102, 0x9A, 0, 85, } },
411 { .bxt = { 154, 0x9A, 1, 128, } },
412};
413
414static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = {
415 .entries = _bxt_ddi_translations_hdmi,
416 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi),
417 .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
418};
419
420
421static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = {
422
423 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
424 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
425 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },
426 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },
427 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },
428 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },
429 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },
430 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },
431 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
432 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
433};
434
435static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = {
436 .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
437 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3),
438};
439
440static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = {
441
442 { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } },
443 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },
444 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },
445 { .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } },
446 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
447 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },
448 { .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } },
449 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },
450 { .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },
451 { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } },
452};
453
454static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = {
455 .entries = _icl_combo_phy_ddi_translations_edp_hbr2,
456 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2),
457};
458
459static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = {
460
461 { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },
462 { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },
463 { .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },
464 { .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },
465 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },
466 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
467 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
468};
469
470static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
471 .entries = _icl_combo_phy_ddi_translations_hdmi,
472 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi),
473 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1,
474};
475
476static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = {
477
478 { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } },
479 { .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } },
480 { .icl = { 0xC, 0x64, 0x34, 0x00, 0x0B } },
481 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },
482 { .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } },
483 { .icl = { 0xC, 0x64, 0x38, 0x00, 0x07 } },
484 { .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } },
485 { .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } },
486 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },
487 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
488};
489
490static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = {
491 .entries = _ehl_combo_phy_ddi_translations_dp,
492 .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_dp),
493};
494
495static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = {
496
497 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
498 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
499 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },
500 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },
501 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
502 { .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } },
503 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },
504 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },
505 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },
506 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
507};
508
509static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = {
510 .entries = _ehl_combo_phy_ddi_translations_edp_hbr2,
511 .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_edp_hbr2),
512};
513
514static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = {
515
516 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
517 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },
518 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },
519 { .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } },
520 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
521 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },
522 { .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } },
523 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },
524 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },
525 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
526};
527
528static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = {
529 .entries = _jsl_combo_phy_ddi_translations_edp_hbr,
530 .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr),
531};
532
533static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = {
534
535 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
536 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
537 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },
538 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },
539 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },
540 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },
541 { .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } },
542 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },
543 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },
544 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
545};
546
547static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = {
548 .entries = _jsl_combo_phy_ddi_translations_edp_hbr2,
549 .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr2),
550};
551
552static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = {
553
554 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },
555 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },
556 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },
557 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },
558 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },
559 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },
560 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },
561 { .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } },
562 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },
563 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
564};
565
566static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = {
567 .entries = _dg1_combo_phy_ddi_translations_dp_rbr_hbr,
568 .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_rbr_hbr),
569};
570
571static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
572
573 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },
574 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },
575 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },
576 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },
577 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },
578 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },
579 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },
580 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },
581 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
582 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
583};
584
585static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
586 .entries = _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3,
587 .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_hbr2_hbr3),
588};
589
590static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hbr[] = {
591
592 { .mg = { 0x18, 0x00, 0x00 } },
593 { .mg = { 0x1D, 0x00, 0x05 } },
594 { .mg = { 0x24, 0x00, 0x0C } },
595 { .mg = { 0x2B, 0x00, 0x14 } },
596 { .mg = { 0x21, 0x00, 0x00 } },
597 { .mg = { 0x2B, 0x00, 0x08 } },
598 { .mg = { 0x30, 0x00, 0x0F } },
599 { .mg = { 0x31, 0x00, 0x03 } },
600 { .mg = { 0x34, 0x00, 0x0B } },
601 { .mg = { 0x3F, 0x00, 0x00 } },
602};
603
604static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr = {
605 .entries = _icl_mg_phy_ddi_translations_rbr_hbr,
606 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_rbr_hbr),
607};
608
609static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
610
611 { .mg = { 0x18, 0x00, 0x00 } },
612 { .mg = { 0x1D, 0x00, 0x05 } },
613 { .mg = { 0x24, 0x00, 0x0C } },
614 { .mg = { 0x2B, 0x00, 0x14 } },
615 { .mg = { 0x26, 0x00, 0x00 } },
616 { .mg = { 0x2C, 0x00, 0x07 } },
617 { .mg = { 0x33, 0x00, 0x0C } },
618 { .mg = { 0x2E, 0x00, 0x00 } },
619 { .mg = { 0x36, 0x00, 0x09 } },
620 { .mg = { 0x3F, 0x00, 0x00 } },
621};
622
623static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3 = {
624 .entries = _icl_mg_phy_ddi_translations_hbr2_hbr3,
625 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hbr2_hbr3),
626};
627
628static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] = {
629
630 { .mg = { 0x1A, 0x0, 0x0 } },
631 { .mg = { 0x20, 0x0, 0x0 } },
632 { .mg = { 0x29, 0x0, 0x0 } },
633 { .mg = { 0x32, 0x0, 0x0 } },
634 { .mg = { 0x3F, 0x0, 0x0 } },
635 { .mg = { 0x3A, 0x0, 0x5 } },
636 { .mg = { 0x39, 0x0, 0x6 } },
637 { .mg = { 0x38, 0x0, 0x7 } },
638 { .mg = { 0x37, 0x0, 0x8 } },
639 { .mg = { 0x36, 0x0, 0x9 } },
640};
641
642static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = {
643 .entries = _icl_mg_phy_ddi_translations_hdmi,
644 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi),
645 .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1,
646};
647
648static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = {
649
650 { .dkl = { 0x7, 0x0, 0x00 } },
651 { .dkl = { 0x5, 0x0, 0x05 } },
652 { .dkl = { 0x2, 0x0, 0x0B } },
653 { .dkl = { 0x0, 0x0, 0x18 } },
654 { .dkl = { 0x5, 0x0, 0x00 } },
655 { .dkl = { 0x2, 0x0, 0x08 } },
656 { .dkl = { 0x0, 0x0, 0x14 } },
657 { .dkl = { 0x2, 0x0, 0x00 } },
658 { .dkl = { 0x0, 0x0, 0x0B } },
659 { .dkl = { 0x0, 0x0, 0x00 } },
660};
661
662static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr = {
663 .entries = _tgl_dkl_phy_ddi_translations_dp_hbr,
664 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr),
665};
666
667static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr2[] = {
668
669 { .dkl = { 0x7, 0x0, 0x00 } },
670 { .dkl = { 0x5, 0x0, 0x05 } },
671 { .dkl = { 0x2, 0x0, 0x0B } },
672 { .dkl = { 0x0, 0x0, 0x19 } },
673 { .dkl = { 0x5, 0x0, 0x00 } },
674 { .dkl = { 0x2, 0x0, 0x08 } },
675 { .dkl = { 0x0, 0x0, 0x14 } },
676 { .dkl = { 0x2, 0x0, 0x00 } },
677 { .dkl = { 0x0, 0x0, 0x0B } },
678 { .dkl = { 0x0, 0x0, 0x00 } },
679};
680
681static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr2 = {
682 .entries = _tgl_dkl_phy_ddi_translations_dp_hbr2,
683 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr2),
684};
685
686static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[] = {
687
688 { .dkl = { 0x7, 0x0, 0x0 } },
689 { .dkl = { 0x6, 0x0, 0x0 } },
690 { .dkl = { 0x4, 0x0, 0x0 } },
691 { .dkl = { 0x2, 0x0, 0x0 } },
692 { .dkl = { 0x0, 0x0, 0x0 } },
693 { .dkl = { 0x0, 0x0, 0x5 } },
694 { .dkl = { 0x0, 0x0, 0x6 } },
695 { .dkl = { 0x0, 0x0, 0x7 } },
696 { .dkl = { 0x0, 0x0, 0x8 } },
697 { .dkl = { 0x0, 0x0, 0xA } },
698};
699
700static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = {
701 .entries = _tgl_dkl_phy_ddi_translations_hdmi,
702 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi),
703 .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1,
704};
705
706static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = {
707
708 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },
709 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
710 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },
711 { .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } },
712 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },
713 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },
714 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },
715 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },
716 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
717 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
718};
719
720static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = {
721 .entries = _tgl_combo_phy_ddi_translations_dp_hbr,
722 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr),
723};
724
725static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = {
726
727 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
728 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
729 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },
730 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },
731 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },
732 { .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } },
733 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },
734 { .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },
735 { .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },
736 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
737};
738
739static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = {
740 .entries = _tgl_combo_phy_ddi_translations_dp_hbr2,
741 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr2),
742};
743
744static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
745
746 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
747 { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } },
748 { .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } },
749 { .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } },
750 { .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } },
751 { .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } },
752 { .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },
753 { .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } },
754 { .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } },
755 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
756};
757
758static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = {
759 .entries = _tgl_uy_combo_phy_ddi_translations_dp_hbr2,
760 .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_ddi_translations_dp_hbr2),
761};
762
763
764
765
766
767static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
768
769 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
770 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
771 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
772 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
773 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
774 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
775 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
776 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
777 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
778};
779
780static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = {
781 .entries = _tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
782 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_edp_hbr2_hobl),
783};
784
785static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = {
786
787 { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } },
788 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
789 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },
790 { .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } },
791 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },
792 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },
793 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },
794 { .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } },
795 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
796 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
797};
798
799static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = {
800 .entries = _rkl_combo_phy_ddi_translations_dp_hbr,
801 .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr),
802};
803
804static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
805
806 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
807 { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } },
808 { .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } },
809 { .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },
810 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },
811 { .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } },
812 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },
813 { .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } },
814 { .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } },
815 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
816};
817
818static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
819 .entries = _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3,
820 .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3),
821};
822
823static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
824
825 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
826 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
827 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } },
828 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },
829 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },
830 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },
831 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } },
832 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },
833 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
834 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
835};
836
837static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
838 .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3,
839 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3),
840};
841
842static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = {
843
844 { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } },
845 { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } },
846 { .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } },
847 { .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } },
848 { .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } },
849 { .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } },
850 { .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },
851 { .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } },
852 { .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },
853 { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } },
854};
855
856static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = {
857 .entries = _adls_combo_phy_ddi_translations_edp_hbr2,
858 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2),
859};
860
861static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = {
862
863 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
864 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
865 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } },
866 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },
867 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },
868 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },
869 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } },
870 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },
871 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
872 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
873};
874
875static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = {
876 .entries = _adls_combo_phy_ddi_translations_edp_hbr3,
877 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3),
878};
879
880static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_hdmi[] = {
881
882 { .icl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } },
883 { .icl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } },
884 { .icl = { 0xA, 0x73, 0x3F, 0x00, 0x00 } },
885 { .icl = { 0xA, 0x78, 0x3F, 0x00, 0x00 } },
886 { .icl = { 0xB, 0x7F, 0x3F, 0x00, 0x00 } },
887 { .icl = { 0xB, 0x7F, 0x3B, 0x00, 0x04 } },
888 { .icl = { 0xB, 0x7F, 0x39, 0x00, 0x06 } },
889 { .icl = { 0xB, 0x7F, 0x37, 0x00, 0x08 } },
890 { .icl = { 0xB, 0x7F, 0x35, 0x00, 0x0A } },
891 { .icl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } },
892};
893
894static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_hdmi = {
895 .entries = _adlp_combo_phy_ddi_translations_hdmi,
896 .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi),
897 .hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi) - 1,
898};
899
900static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr[] = {
901
902 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
903 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
904 { .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } },
905 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },
906 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },
907 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },
908 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },
909 { .icl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } },
910 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },
911 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
912};
913
914static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr = {
915 .entries = _adlp_combo_phy_ddi_translations_dp_hbr,
916 .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr),
917};
918
919static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
920
921 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },
922 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },
923 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },
924 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },
925 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },
926 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },
927 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },
928 { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } },
929 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },
930 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },
931};
932
933static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
934 .entries = _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3,
935 .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr2_hbr3),
936};
937
938static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_hbr3 = {
939 .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
940 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3),
941};
942
943static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_up_to_hbr2 = {
944 .entries = _icl_combo_phy_ddi_translations_edp_hbr2,
945 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2),
946};
947
948static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr[] = {
949
950 { .dkl = { 0x7, 0x0, 0x01 } },
951 { .dkl = { 0x5, 0x0, 0x06 } },
952 { .dkl = { 0x2, 0x0, 0x0B } },
953 { .dkl = { 0x0, 0x0, 0x17 } },
954 { .dkl = { 0x5, 0x0, 0x00 } },
955 { .dkl = { 0x2, 0x0, 0x08 } },
956 { .dkl = { 0x0, 0x0, 0x14 } },
957 { .dkl = { 0x2, 0x0, 0x00 } },
958 { .dkl = { 0x0, 0x0, 0x0B } },
959 { .dkl = { 0x0, 0x0, 0x00 } },
960};
961
962static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr = {
963 .entries = _adlp_dkl_phy_ddi_translations_dp_hbr,
964 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr),
965};
966
967static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3[] = {
968
969 { .dkl = { 0x7, 0x0, 0x00 } },
970 { .dkl = { 0x5, 0x0, 0x04 } },
971 { .dkl = { 0x2, 0x0, 0x0A } },
972 { .dkl = { 0x0, 0x0, 0x18 } },
973 { .dkl = { 0x5, 0x0, 0x00 } },
974 { .dkl = { 0x2, 0x0, 0x06 } },
975 { .dkl = { 0x0, 0x0, 0x14 } },
976 { .dkl = { 0x2, 0x0, 0x00 } },
977 { .dkl = { 0x0, 0x0, 0x09 } },
978 { .dkl = { 0x0, 0x0, 0x00 } },
979};
980
981static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3 = {
982 .entries = _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3,
983 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3),
984};
985
986bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
987{
988 return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
989}
990
991static const struct intel_ddi_buf_trans *
992intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries)
993{
994 *num_entries = ddi_translations->num_entries;
995 return ddi_translations;
996}
997
998static const struct intel_ddi_buf_trans *
999hsw_get_buf_trans(struct intel_encoder *encoder,
1000 const struct intel_crtc_state *crtc_state,
1001 int *n_entries)
1002{
1003 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1004 return intel_get_buf_trans(&hsw_ddi_translations_fdi, n_entries);
1005 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1006 return intel_get_buf_trans(&hsw_ddi_translations_hdmi, n_entries);
1007 else
1008 return intel_get_buf_trans(&hsw_ddi_translations_dp, n_entries);
1009}
1010
1011static const struct intel_ddi_buf_trans *
1012bdw_get_buf_trans(struct intel_encoder *encoder,
1013 const struct intel_crtc_state *crtc_state,
1014 int *n_entries)
1015{
1016 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1017
1018 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1019 return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries);
1020 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1021 return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries);
1022 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1023 i915->vbt.edp.low_vswing)
1024 return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries);
1025 else
1026 return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries);
1027}
1028
1029static int skl_buf_trans_num_entries(enum port port, int n_entries)
1030{
1031
1032 if (port == PORT_A || port == PORT_E)
1033 return min(n_entries, 10);
1034 else
1035 return min(n_entries, 9);
1036}
1037
1038static const struct intel_ddi_buf_trans *
1039_skl_get_buf_trans_dp(struct intel_encoder *encoder,
1040 const struct intel_ddi_buf_trans *ddi_translations,
1041 int *n_entries)
1042{
1043 ddi_translations = intel_get_buf_trans(ddi_translations, n_entries);
1044 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
1045 return ddi_translations;
1046}
1047
1048static const struct intel_ddi_buf_trans *
1049skl_y_get_buf_trans(struct intel_encoder *encoder,
1050 const struct intel_crtc_state *crtc_state,
1051 int *n_entries)
1052{
1053 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1054
1055 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1056 return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries);
1057 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1058 i915->vbt.edp.low_vswing)
1059 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries);
1060 else
1061 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries);
1062}
1063
1064static const struct intel_ddi_buf_trans *
1065skl_u_get_buf_trans(struct intel_encoder *encoder,
1066 const struct intel_crtc_state *crtc_state,
1067 int *n_entries)
1068{
1069 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1070
1071 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1072 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
1073 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1074 i915->vbt.edp.low_vswing)
1075 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries);
1076 else
1077 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries);
1078}
1079
1080static const struct intel_ddi_buf_trans *
1081skl_get_buf_trans(struct intel_encoder *encoder,
1082 const struct intel_crtc_state *crtc_state,
1083 int *n_entries)
1084{
1085 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1086
1087 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1088 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
1089 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1090 i915->vbt.edp.low_vswing)
1091 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries);
1092 else
1093 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries);
1094}
1095
1096static const struct intel_ddi_buf_trans *
1097kbl_y_get_buf_trans(struct intel_encoder *encoder,
1098 const struct intel_crtc_state *crtc_state,
1099 int *n_entries)
1100{
1101 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1102
1103 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1104 return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries);
1105 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1106 i915->vbt.edp.low_vswing)
1107 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries);
1108 else
1109 return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries);
1110}
1111
1112static const struct intel_ddi_buf_trans *
1113kbl_u_get_buf_trans(struct intel_encoder *encoder,
1114 const struct intel_crtc_state *crtc_state,
1115 int *n_entries)
1116{
1117 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1118
1119 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1120 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
1121 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1122 i915->vbt.edp.low_vswing)
1123 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries);
1124 else
1125 return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries);
1126}
1127
1128static const struct intel_ddi_buf_trans *
1129kbl_get_buf_trans(struct intel_encoder *encoder,
1130 const struct intel_crtc_state *crtc_state,
1131 int *n_entries)
1132{
1133 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1134
1135 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1136 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
1137 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1138 i915->vbt.edp.low_vswing)
1139 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries);
1140 else
1141 return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries);
1142}
1143
1144static const struct intel_ddi_buf_trans *
1145bxt_get_buf_trans(struct intel_encoder *encoder,
1146 const struct intel_crtc_state *crtc_state,
1147 int *n_entries)
1148{
1149 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1150
1151 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1152 return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries);
1153 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1154 i915->vbt.edp.low_vswing)
1155 return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries);
1156 else
1157 return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries);
1158}
1159
1160static const struct intel_ddi_buf_trans *
1161icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1162 const struct intel_crtc_state *crtc_state,
1163 int *n_entries)
1164{
1165 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
1166 n_entries);
1167}
1168
1169static const struct intel_ddi_buf_trans *
1170icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1171 const struct intel_crtc_state *crtc_state,
1172 int *n_entries)
1173{
1174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1175
1176 if (crtc_state->port_clock > 540000) {
1177 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
1178 n_entries);
1179 } else if (dev_priv->vbt.edp.low_vswing) {
1180 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
1181 n_entries);
1182 }
1183
1184 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1185}
1186
1187static const struct intel_ddi_buf_trans *
1188icl_get_combo_buf_trans(struct intel_encoder *encoder,
1189 const struct intel_crtc_state *crtc_state,
1190 int *n_entries)
1191{
1192 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1193 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
1194 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1195 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1196 else
1197 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1198}
1199
1200static const struct intel_ddi_buf_trans *
1201icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1202 const struct intel_crtc_state *crtc_state,
1203 int *n_entries)
1204{
1205 if (crtc_state->port_clock > 270000) {
1206 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hbr2_hbr3,
1207 n_entries);
1208 } else {
1209 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_rbr_hbr,
1210 n_entries);
1211 }
1212}
1213
1214static const struct intel_ddi_buf_trans *
1215icl_get_mg_buf_trans(struct intel_encoder *encoder,
1216 const struct intel_crtc_state *crtc_state,
1217 int *n_entries)
1218{
1219 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1220 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, n_entries);
1221 else
1222 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1223}
1224
1225static const struct intel_ddi_buf_trans *
1226ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1227 const struct intel_crtc_state *crtc_state,
1228 int *n_entries)
1229{
1230 if (crtc_state->port_clock > 270000)
1231 return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, n_entries);
1232 else
1233 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries);
1234}
1235
1236static const struct intel_ddi_buf_trans *
1237ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1238 const struct intel_crtc_state *crtc_state,
1239 int *n_entries)
1240{
1241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1242
1243 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1244 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
1245 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1246 dev_priv->vbt.edp.low_vswing)
1247 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1248 else
1249 return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, n_entries);
1250}
1251
1252static const struct intel_ddi_buf_trans *
1253jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1254 const struct intel_crtc_state *crtc_state,
1255 int *n_entries)
1256{
1257 if (crtc_state->port_clock > 270000)
1258 return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, n_entries);
1259 else
1260 return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, n_entries);
1261}
1262
1263static const struct intel_ddi_buf_trans *
1264jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1265 const struct intel_crtc_state *crtc_state,
1266 int *n_entries)
1267{
1268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1269
1270 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1271 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
1272 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1273 dev_priv->vbt.edp.low_vswing)
1274 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1275 else
1276 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries);
1277}
1278
1279static const struct intel_ddi_buf_trans *
1280tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1281 const struct intel_crtc_state *crtc_state,
1282 int *n_entries)
1283{
1284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1285
1286 if (crtc_state->port_clock > 270000) {
1287 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1288 return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2,
1289 n_entries);
1290 } else {
1291 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr2,
1292 n_entries);
1293 }
1294 } else {
1295 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr,
1296 n_entries);
1297 }
1298}
1299
1300static const struct intel_ddi_buf_trans *
1301tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1302 const struct intel_crtc_state *crtc_state,
1303 int *n_entries)
1304{
1305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1306 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1307
1308 if (crtc_state->port_clock > 540000) {
1309 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
1310 n_entries);
1311 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
1312 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
1313 n_entries);
1314 } else if (dev_priv->vbt.edp.low_vswing) {
1315 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
1316 n_entries);
1317 }
1318
1319 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1320}
1321
1322static const struct intel_ddi_buf_trans *
1323tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1324 const struct intel_crtc_state *crtc_state,
1325 int *n_entries)
1326{
1327 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1328 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
1329 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1330 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1331 else
1332 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1333}
1334
1335static const struct intel_ddi_buf_trans *
1336dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1337 const struct intel_crtc_state *crtc_state,
1338 int *n_entries)
1339{
1340 if (crtc_state->port_clock > 270000)
1341 return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3,
1342 n_entries);
1343 else
1344 return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr,
1345 n_entries);
1346}
1347
1348static const struct intel_ddi_buf_trans *
1349dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1350 const struct intel_crtc_state *crtc_state,
1351 int *n_entries)
1352{
1353 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1354 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1355
1356 if (crtc_state->port_clock > 540000)
1357 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
1358 n_entries);
1359 else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed)
1360 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
1361 n_entries);
1362 else if (dev_priv->vbt.edp.low_vswing)
1363 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
1364 n_entries);
1365 else
1366 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1367}
1368
1369static const struct intel_ddi_buf_trans *
1370dg1_get_combo_buf_trans(struct intel_encoder *encoder,
1371 const struct intel_crtc_state *crtc_state,
1372 int *n_entries)
1373{
1374 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1375 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
1376 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1377 return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1378 else
1379 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1380}
1381
1382static const struct intel_ddi_buf_trans *
1383rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1384 const struct intel_crtc_state *crtc_state,
1385 int *n_entries)
1386{
1387 if (crtc_state->port_clock > 270000)
1388 return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries);
1389 else
1390 return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries);
1391}
1392
1393static const struct intel_ddi_buf_trans *
1394rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1395 const struct intel_crtc_state *crtc_state,
1396 int *n_entries)
1397{
1398 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1399 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1400
1401 if (crtc_state->port_clock > 540000) {
1402 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
1403 n_entries);
1404 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
1405 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
1406 n_entries);
1407 } else if (dev_priv->vbt.edp.low_vswing) {
1408 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
1409 n_entries);
1410 }
1411
1412 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1413}
1414
1415static const struct intel_ddi_buf_trans *
1416rkl_get_combo_buf_trans(struct intel_encoder *encoder,
1417 const struct intel_crtc_state *crtc_state,
1418 int *n_entries)
1419{
1420 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1421 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
1422 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1423 return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1424 else
1425 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1426}
1427
1428static const struct intel_ddi_buf_trans *
1429adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1430 const struct intel_crtc_state *crtc_state,
1431 int *n_entries)
1432{
1433 if (crtc_state->port_clock > 270000)
1434 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries);
1435 else
1436 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries);
1437}
1438
1439static const struct intel_ddi_buf_trans *
1440adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1441 const struct intel_crtc_state *crtc_state,
1442 int *n_entries)
1443{
1444 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1445 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1446
1447 if (crtc_state->port_clock > 540000)
1448 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries);
1449 else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed)
1450 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries);
1451 else if (i915->vbt.edp.low_vswing)
1452 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries);
1453 else
1454 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1455}
1456
1457static const struct intel_ddi_buf_trans *
1458adls_get_combo_buf_trans(struct intel_encoder *encoder,
1459 const struct intel_crtc_state *crtc_state,
1460 int *n_entries)
1461{
1462 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1463 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
1464 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1465 return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1466 else
1467 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1468}
1469
1470static const struct intel_ddi_buf_trans *
1471adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1472 const struct intel_crtc_state *crtc_state,
1473 int *n_entries)
1474{
1475 if (crtc_state->port_clock > 270000)
1476 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries);
1477 else
1478 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr, n_entries);
1479}
1480
1481static const struct intel_ddi_buf_trans *
1482adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1483 const struct intel_crtc_state *crtc_state,
1484 int *n_entries)
1485{
1486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1487 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1488
1489 if (crtc_state->port_clock > 540000) {
1490 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_hbr3,
1491 n_entries);
1492 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
1493 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
1494 n_entries);
1495 } else if (dev_priv->vbt.edp.low_vswing) {
1496 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_up_to_hbr2,
1497 n_entries);
1498 }
1499
1500 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1501}
1502
1503static const struct intel_ddi_buf_trans *
1504adlp_get_combo_buf_trans(struct intel_encoder *encoder,
1505 const struct intel_crtc_state *crtc_state,
1506 int *n_entries)
1507{
1508 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1509 return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_hdmi, n_entries);
1510 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1511 return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1512 else
1513 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1514}
1515
1516static const struct intel_ddi_buf_trans *
1517tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1518 const struct intel_crtc_state *crtc_state,
1519 int *n_entries)
1520{
1521 if (crtc_state->port_clock > 270000) {
1522 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr2,
1523 n_entries);
1524 } else {
1525 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr,
1526 n_entries);
1527 }
1528}
1529
1530static const struct intel_ddi_buf_trans *
1531tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1532 const struct intel_crtc_state *crtc_state,
1533 int *n_entries)
1534{
1535 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1536 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries);
1537 else
1538 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1539}
1540
1541static const struct intel_ddi_buf_trans *
1542adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1543 const struct intel_crtc_state *crtc_state,
1544 int *n_entries)
1545{
1546 if (crtc_state->port_clock > 270000) {
1547 return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3,
1548 n_entries);
1549 } else {
1550 return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr,
1551 n_entries);
1552 }
1553}
1554
1555static const struct intel_ddi_buf_trans *
1556adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
1557 const struct intel_crtc_state *crtc_state,
1558 int *n_entries)
1559{
1560 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1561 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries);
1562 else
1563 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1564}
1565
1566int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
1567 const struct intel_crtc_state *crtc_state,
1568 int *default_entry)
1569{
1570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1571 const struct intel_ddi_buf_trans *ddi_translations;
1572 int n_entries;
1573
1574 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1575
1576 if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) {
1577 *default_entry = 0;
1578 return 0;
1579 }
1580
1581 *default_entry = ddi_translations->hdmi_default_entry;
1582
1583 return n_entries;
1584}
1585
1586void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
1587{
1588 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1589 enum phy phy = intel_port_to_phy(i915, encoder->port);
1590
1591 if (IS_ALDERLAKE_P(i915)) {
1592 if (intel_phy_is_combo(i915, phy))
1593 encoder->get_buf_trans = adlp_get_combo_buf_trans;
1594 else
1595 encoder->get_buf_trans = adlp_get_dkl_buf_trans;
1596 } else if (IS_ALDERLAKE_S(i915)) {
1597 encoder->get_buf_trans = adls_get_combo_buf_trans;
1598 } else if (IS_ROCKETLAKE(i915)) {
1599 encoder->get_buf_trans = rkl_get_combo_buf_trans;
1600 } else if (IS_DG1(i915)) {
1601 encoder->get_buf_trans = dg1_get_combo_buf_trans;
1602 } else if (DISPLAY_VER(i915) >= 12) {
1603 if (intel_phy_is_combo(i915, phy))
1604 encoder->get_buf_trans = tgl_get_combo_buf_trans;
1605 else
1606 encoder->get_buf_trans = tgl_get_dkl_buf_trans;
1607 } else if (DISPLAY_VER(i915) == 11) {
1608 if (IS_PLATFORM(i915, INTEL_JASPERLAKE))
1609 encoder->get_buf_trans = jsl_get_combo_buf_trans;
1610 else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
1611 encoder->get_buf_trans = ehl_get_combo_buf_trans;
1612 else if (intel_phy_is_combo(i915, phy))
1613 encoder->get_buf_trans = icl_get_combo_buf_trans;
1614 else
1615 encoder->get_buf_trans = icl_get_mg_buf_trans;
1616 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1617 encoder->get_buf_trans = bxt_get_buf_trans;
1618 } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
1619 encoder->get_buf_trans = kbl_y_get_buf_trans;
1620 } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
1621 encoder->get_buf_trans = kbl_u_get_buf_trans;
1622 } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
1623 encoder->get_buf_trans = kbl_get_buf_trans;
1624 } else if (IS_SKL_ULX(i915)) {
1625 encoder->get_buf_trans = skl_y_get_buf_trans;
1626 } else if (IS_SKL_ULT(i915)) {
1627 encoder->get_buf_trans = skl_u_get_buf_trans;
1628 } else if (IS_SKYLAKE(i915)) {
1629 encoder->get_buf_trans = skl_get_buf_trans;
1630 } else if (IS_BROADWELL(i915)) {
1631 encoder->get_buf_trans = bdw_get_buf_trans;
1632 } else {
1633 encoder->get_buf_trans = hsw_get_buf_trans;
1634 }
1635}
1636