1config DRM_ZYNQMP_DPSUB 2 tristate "ZynqMP DisplayPort Controller Driver" 3 depends on ARCH_ZYNQMP || COMPILE_TEST 4 depends on COMMON_CLK && DRM && OF 5 depends on DMADEVICES 6 depends on DRM_XLNX 7 select VIDEOMODE_HELPERS 8 select XILINX_DMA_ENGINES 9 select PHY_XILINX_ZYNQMP 10 select XILINX_ZYNQMP_DPDMA 11 select MFD_SYSCON 12 help 13 This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose 14 this option if you have a Xilinx ZynqMP SoC with DisplayPort 15 subsystem. 16 17config DRM_XLNX 18 tristate "Xilinx DRM KMS Driver" 19 depends on DRM && OF 20 select DRM_KMS_HELPER 21 select DRM_KMS_CMA_HELPER 22 select DRM_GEM_CMA_HELPER 23 select SND_PCM_ELD 24 help 25 Xilinx DRM KMS driver. Choose this option if you have 26 a Xilinx SoCs with hardened display pipeline or soft 27 display pipeline using Xilinx IPs in FPGA. This module 28 provides the kernel mode setting functionalities 29 for Xilinx display drivers. 30 31config DRM_XLNX_BRIDGE 32 tristate "Xilinx DRM KMS bridge" 33 depends on DRM_XLNX 34 help 35 Xilinx DRM KMS bridge. This module provides some interfaces 36 to enable inter-module communication. Choose this option 37 from the provider driver when the Xilinx bridge interface is 38 needed. 39 40config DRM_XLNX_BRIDGE_DEBUG_FS 41 bool "Xilinx DRM KMS bridge debugfs" 42 depends on DEBUG_FS && DRM_XLNX_BRIDGE 43 help 44 Enable the debugfs code for Xilinx bridge. The debugfs code 45 enables debugging or testing related features. It exposes some 46 low level controls to the user space to help testing automation, 47 as well as can enable additional diagnostic or statistical 48 information. 49 50config DRM_XLNX_DPTX 51 tristate "Xilinx DRM DisplayPort Subsystem Driver" 52 depends on DRM_XLNX 53 help 54 DRM driver for Xilinx DisplayPort Tx Subsystem for FPGA. Choose 55 this option if you have a FPGA display pipeline that includes 56 the Xilinx DisplayPort Tx Subsystem IP. The driver provides 57 the kernel mode setting functionalities for the IP. 58 59config DRM_XLNX_DSI 60 tristate "Xilinx DRM DSI Subsystem Driver" 61 depends on DRM_XLNX 62 select DRM_MIPI_DSI 63 select DRM_PANEL 64 select BACKLIGHT_LCD_SUPPORT 65 select BACKLIGHT_CLASS_DEVICE 66 help 67 DRM driver for Xilinx MIPI-DSI. 68 69config DRM_XLNX_HDMITX 70 tristate "Xilinx DRM HDMI Subsystem Driver" 71 depends on DRM_XLNX 72 help 73 DRM driver for Xilinx HDMI Tx Subsystem for FPGA. Choose 74 this option if you have a FPGA display pipeline that includes 75 the Xilinx HDMI Tx Subsystem IP. The driver provides 76 the kernel mode setting functionalities for the IP. 77 78config DRM_XLNX_MIXER 79 tristate "Xilinx DRM Mixer Driver" 80 depends on DRM_XLNX 81 select VIDEOMODE_HELPERS 82 help 83 DRM driver for Xilinx Mixer driver. 84 85config DRM_XLNX_PL_DISP 86 tristate "Xilinx DRM PL display driver" 87 depends on DRM_XLNX && XILINX_FRMBUF 88 select VIDEOMODE_HELPERS 89 help 90 DRM driver for Xilinx PL display driver, provides drm 91 crtc and plane object to display pipeline. You need to 92 choose this option if your display pipeline needs one 93 crtc and plane object with single DMA connected. 94 95config DRM_XLNX_SDI 96 tristate "Xilinx DRM SDI Subsystem Driver" 97 depends on DRM_XLNX 98 help 99 DRM driver for Xilinx SDI Tx Subsystem. 100 101config DRM_XLNX_BRIDGE_CSC 102 tristate "Xilinx DRM CSC Driver" 103 depends on DRM_XLNX_BRIDGE 104 help 105 DRM brige driver for color space converter of VPSS. Choose 106 this option if color space converter is connected to an encoder. 107 The driver provides set/get resolution and color format 108 functionality through bridge layer. 109 110config DRM_XLNX_BRIDGE_SCALER 111 tristate "Xilinx DRM Scaler Driver" 112 depends on DRM_XLNX_BRIDGE 113 help 114 DRM brige driver for scaler of VPSS. Choose this option 115 if scaler is connected to an encoder. The driver provides 116 upscaling, down scaling and no scaling functionality through 117 bridge layer. 118 119config DRM_XLNX_BRIDGE_VTC 120 tristate "Xilinx DRM VTC Driver" 121 depends on DRM_XLNX_BRIDGE 122 help 123 DRM brige driver for Xilinx Video Timing Controller. Choose 124 this option to make VTC a part of the CRTC in display pipeline. 125 Currently the support is added to the Xilinx Video Mixer and 126 Xilinx PL display CRTC drivers. This driver provides ability 127 to generate timings through the bridge layer. 128