1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * ZynqMP Display Controller Driver - Register Definitions 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12#ifndef _ZYNQMP_DISP_REGS_H_ 13#define _ZYNQMP_DISP_REGS_H_ 14 15#include <linux/bits.h> 16 17/* Blender registers */ 18#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0 19#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4 20#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8 21#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff 22#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc 23#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe 24#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff 25#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(n) ((n) << 1) 26#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN BIT(0) 27#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14 28#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0 29#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444 0x1 30#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 0x2 31#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 32#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4 33#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4) 34#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE BIT(4) 35#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18 36#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US BIT(0) 37#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1) 38#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8) 39#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9 40#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20 41#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24 42#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28 43#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c 44#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30 45#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34 46#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38 47#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c 48#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40 49#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0 0x44 50#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1 0x48 51#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2 0x4c 52#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3 0x50 53#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF4 0x54 54#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF5 0x58 55#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF6 0x5c 56#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF7 0x60 57#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF8 0x64 58#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET 3 59#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(n) (0x20 + ((n) * 4)) 60#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(n) (0x44 + ((n) * 4)) 61#define ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(n) (0x68 + ((n) * 4)) 62#define ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(n) (0x74 + ((n) * 4)) 63#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(n) (0x80 + ((n) * 4)) 64#define ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(n) (0xa4 + ((n) * 4)) 65#define ZYNQMP_DISP_V_BLEND_LUMA_IN1CSC_OFFSET 0x68 66#define ZYNQMP_DISP_V_BLEND_CR_IN1CSC_OFFSET 0x6c 67#define ZYNQMP_DISP_V_BLEND_CB_IN1CSC_OFFSET 0x70 68#define ZYNQMP_DISP_V_BLEND_LUMA_OUTCSC_OFFSET 0x74 69#define ZYNQMP_DISP_V_BLEND_CR_OUTCSC_OFFSET 0x78 70#define ZYNQMP_DISP_V_BLEND_CB_OUTCSC_OFFSET 0x7c 71#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF0 0x80 72#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF1 0x84 73#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF2 0x88 74#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF3 0x8c 75#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF4 0x90 76#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF5 0x94 77#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF6 0x98 78#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF7 0x9c 79#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF8 0xa0 80#define ZYNQMP_DISP_V_BLEND_LUMA_IN2CSC_OFFSET 0xa4 81#define ZYNQMP_DISP_V_BLEND_CR_IN2CSC_OFFSET 0xa8 82#define ZYNQMP_DISP_V_BLEND_CB_IN2CSC_OFFSET 0xac 83#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_ENABLE 0x1d0 84#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP1 0x1d4 85#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP2 0x1d8 86#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP3 0x1dc 87 88/* AV buffer manager registers */ 89#define ZYNQMP_DISP_AV_BUF_FMT 0x0 90#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_SHIFT 0 91#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK (0x1f << 0) 92#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_UYVY (0 << 0) 93#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY (1 << 0) 94#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YVYU (2 << 0) 95#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV (3 << 0) 96#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16 (4 << 0) 97#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24 (5 << 0) 98#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI (6 << 0) 99#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO (7 << 0) 100#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2 (8 << 0) 101#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444 (9 << 0) 102#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888 (10 << 0) 103#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880 (11 << 0) 104#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10 (12 << 0) 105#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10 (13 << 0) 106#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_10 (14 << 0) 107#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10 (15 << 0) 108#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_10 (16 << 0) 109#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10 (17 << 0) 110#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10 (18 << 0) 111#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420 (19 << 0) 112#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420 (20 << 0) 113#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420 (21 << 0) 114#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420_10 (22 << 0) 115#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10 (23 << 0) 116#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420_10 (24 << 0) 117#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_SHIFT 8 118#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK (0xf << 8) 119#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888 (0 << 8) 120#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888 (1 << 8) 121#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888 (2 << 8) 122#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888 (3 << 8) 123#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551 (4 << 8) 124#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444 (5 << 8) 125#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565 (6 << 8) 126#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_8BPP (7 << 8) 127#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_4BPP (8 << 8) 128#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_2BPP (9 << 8) 129#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_1BPP (10 << 8) 130#define ZYNQMP_DISP_AV_BUF_NON_LIVE_LATENCY 0x8 131#define ZYNQMP_DISP_AV_BUF_CHBUF 0x10 132#define ZYNQMP_DISP_AV_BUF_CHBUF_EN BIT(0) 133#define ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH BIT(1) 134#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT 2 135#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MASK (0xf << 2) 136#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX 0xf 137#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX 0x3 138#define ZYNQMP_DISP_AV_BUF_STATUS 0x28 139#define ZYNQMP_DISP_AV_BUF_STC_CTRL 0x2c 140#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EN BIT(0) 141#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_SHIFT 1 142#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VSYNC 0 143#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VID 1 144#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_AUD 2 145#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_INT_VSYNC 3 146#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE0 0x30 147#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE1 0x34 148#define ZYNQMP_DISP_AV_BUF_STC_ADJ 0x38 149#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS0 0x3c 150#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS1 0x40 151#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS0 0x44 152#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS1 0x48 153#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS0 0x4c 154#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS1 0x50 155#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS0 0x54 156#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS1 0x58 157#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT0 0x60 158#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT1 0x64 159#define ZYNQMP_DISP_AV_BUF_OUTPUT 0x70 160#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT 0 161#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK (0x3 << 0) 162#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE (0 << 0) 163#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM (1 << 0) 164#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN (2 << 0) 165#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE (3 << 0) 166#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT 2 167#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK (0x3 << 2) 168#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE (0 << 2) 169#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM (1 << 2) 170#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE (2 << 2) 171#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_NONE (3 << 2) 172#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT 4 173#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK (0x3 << 4) 174#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PL (0 << 4) 175#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM (1 << 4) 176#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PATTERN (2 << 4) 177#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE (3 << 4) 178#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN BIT(6) 179#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT0 0x74 180#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT1 0x78 181#define ZYNQMP_DISP_AV_BUF_PATTERN_GEN_SELECT 0x100 182#define ZYNQMP_DISP_AV_BUF_CLK_SRC 0x120 183#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS BIT(0) 184#define ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS BIT(1) 185#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING BIT(2) 186#define ZYNQMP_DISP_AV_BUF_SRST_REG 0x124 187#define ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST BIT(1) 188#define ZYNQMP_DISP_AV_BUF_AUDIO_CH_CONFIG 0x12c 189#define ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(n) (0x200 + ((n) * 4)) 190#define ZYNQMP_DISP_AV_BUF_GFX_COMP0_SF 0x200 191#define ZYNQMP_DISP_AV_BUF_GFX_COMP1_SF 0x204 192#define ZYNQMP_DISP_AV_BUF_GFX_COMP2_SF 0x208 193#define ZYNQMP_DISP_AV_BUF_VID_COMP_SF(n) (0x20c + ((n) * 4)) 194#define ZYNQMP_DISP_AV_BUF_VID_COMP0_SF 0x20c 195#define ZYNQMP_DISP_AV_BUF_VID_COMP1_SF 0x210 196#define ZYNQMP_DISP_AV_BUF_VID_COMP2_SF 0x214 197#define ZYNQMP_DISP_AV_BUF_LIVD_VID_COMP_SF(n) (0x218 + ((n) * 4)) 198#define ZYNQMP_DISP_AV_BUF_LIVE_VID_COMP0_SF 0x218 199#define ZYNQMP_DISP_AV_BUF_LIVE_VID_COMP1_SF 0x21c 200#define ZYNQMP_DISP_AV_BUF_LIVE_VID_COMP2_SF 0x220 201#define ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG 0x224 202#define ZYNQMP_DISP_AV_BUF_LIVD_GFX_COMP_SF(n) (0x228 + ((n) * 4)) 203#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_COMP0_SF 0x228 204#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_COMP1_SF 0x22c 205#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_COMP2_SF 0x230 206#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG 0x234 207#define ZYNQMP_DISP_AV_BUF_4BIT_SF 0x11111 208#define ZYNQMP_DISP_AV_BUF_5BIT_SF 0x10842 209#define ZYNQMP_DISP_AV_BUF_6BIT_SF 0x10410 210#define ZYNQMP_DISP_AV_BUF_8BIT_SF 0x10101 211#define ZYNQMP_DISP_AV_BUF_10BIT_SF 0x10040 212#define ZYNQMP_DISP_AV_BUF_NULL_SF 0 213#define ZYNQMP_DISP_AV_BUF_NUM_SF 3 214#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 0x0 215#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 0x1 216#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 0x2 217#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3 218#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0) 219#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB 0x00 220#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 0x10 221#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 0x20 222#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY 0x30 223#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4) 224#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST BIT(8) 225#define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY 0x400 226 227/* Audio registers */ 228#define ZYNQMP_DISP_AUD_MIXER_VOLUME 0x0 229#define ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE 0x20002000 230#define ZYNQMP_DISP_AUD_MIXER_META_DATA 0x4 231#define ZYNQMP_DISP_AUD_CH_STATUS0 0x8 232#define ZYNQMP_DISP_AUD_CH_STATUS1 0xc 233#define ZYNQMP_DISP_AUD_CH_STATUS2 0x10 234#define ZYNQMP_DISP_AUD_CH_STATUS3 0x14 235#define ZYNQMP_DISP_AUD_CH_STATUS4 0x18 236#define ZYNQMP_DISP_AUD_CH_STATUS5 0x1c 237#define ZYNQMP_DISP_AUD_CH_A_DATA0 0x20 238#define ZYNQMP_DISP_AUD_CH_A_DATA1 0x24 239#define ZYNQMP_DISP_AUD_CH_A_DATA2 0x28 240#define ZYNQMP_DISP_AUD_CH_A_DATA3 0x2c 241#define ZYNQMP_DISP_AUD_CH_A_DATA4 0x30 242#define ZYNQMP_DISP_AUD_CH_A_DATA5 0x34 243#define ZYNQMP_DISP_AUD_CH_B_DATA0 0x38 244#define ZYNQMP_DISP_AUD_CH_B_DATA1 0x3c 245#define ZYNQMP_DISP_AUD_CH_B_DATA2 0x40 246#define ZYNQMP_DISP_AUD_CH_B_DATA3 0x44 247#define ZYNQMP_DISP_AUD_CH_B_DATA4 0x48 248#define ZYNQMP_DISP_AUD_CH_B_DATA5 0x4c 249#define ZYNQMP_DISP_AUD_SOFT_RESET 0xc00 250#define ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST BIT(0) 251 252#endif /* _ZYNQMP_DISP_REGS_H_ */ 253