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10#ifndef BNXT_PTP_H
11#define BNXT_PTP_H
12
13#define BNXT_PTP_GRC_WIN 6
14#define BNXT_PTP_GRC_WIN_BASE 0x6000
15
16#define BNXT_MAX_PHC_DRIFT 31000000
17#define BNXT_LO_TIMER_MASK 0x0000ffffffffUL
18#define BNXT_HI_TIMER_MASK 0xffff00000000UL
19
20#define BNXT_PTP_QTS_TIMEOUT 1000
21#define BNXT_PTP_QTS_TX_ENABLES (PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID | \
22 PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT | \
23 PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET)
24
25struct pps_pin {
26 u8 event;
27 u8 usage;
28 u8 state;
29};
30
31#define TSIO_PIN_VALID(pin) ((pin) < (BNXT_MAX_TSIO_PINS))
32
33#define EVENT_DATA2_PPS_EVENT_TYPE(data2) \
34 ((data2) & ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE)
35
36#define EVENT_DATA2_PPS_PIN_NUM(data2) \
37 (((data2) & \
38 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK) >>\
39 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT)
40
41#define BNXT_DATA2_UPPER_MSK \
42 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK
43
44#define BNXT_DATA2_UPPER_SFT \
45 (32 - \
46 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT)
47
48#define BNXT_DATA1_LOWER_MSK \
49 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK
50
51#define BNXT_DATA1_LOWER_SFT \
52 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT
53
54#define EVENT_PPS_TS(data2, data1) \
55 (((u64)((data2) & BNXT_DATA2_UPPER_MSK) << BNXT_DATA2_UPPER_SFT) |\
56 (((data1) & BNXT_DATA1_LOWER_MSK) >> BNXT_DATA1_LOWER_SFT))
57
58#define BNXT_PPS_PIN_DISABLE 0
59#define BNXT_PPS_PIN_ENABLE 1
60#define BNXT_PPS_PIN_NONE 0
61#define BNXT_PPS_PIN_PPS_IN 1
62#define BNXT_PPS_PIN_PPS_OUT 2
63#define BNXT_PPS_PIN_SYNC_IN 3
64#define BNXT_PPS_PIN_SYNC_OUT 4
65
66#define BNXT_PPS_EVENT_INTERNAL 1
67#define BNXT_PPS_EVENT_EXTERNAL 2
68
69struct bnxt_pps {
70 u8 num_pins;
71#define BNXT_MAX_TSIO_PINS 4
72 struct pps_pin pins[BNXT_MAX_TSIO_PINS];
73};
74
75struct bnxt_ptp_cfg {
76 struct ptp_clock_info ptp_info;
77 struct ptp_clock *ptp_clock;
78 struct cyclecounter cc;
79 struct timecounter tc;
80 struct bnxt_pps pps_info;
81
82 spinlock_t ptp_lock;
83 struct sk_buff *tx_skb;
84 u64 current_time;
85 u64 old_time;
86 unsigned long next_period;
87 unsigned long next_overflow_check;
88
89 #define BNXT_PHC_OVERFLOW_PERIOD (19 * 3600 * HZ)
90
91 u16 tx_seqid;
92 u16 tx_hdr_off;
93 struct bnxt *bp;
94 atomic_t tx_avail;
95#define BNXT_MAX_TX_TS 1
96 u16 rxctl;
97#define BNXT_PTP_MSG_SYNC (1 << 0)
98#define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
99#define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
100#define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
101#define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
102#define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
103#define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
104#define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
105#define BNXT_PTP_MSG_SIGNALING (1 << 12)
106#define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
107#define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
108 BNXT_PTP_MSG_DELAY_REQ | \
109 BNXT_PTP_MSG_PDELAY_REQ | \
110 BNXT_PTP_MSG_PDELAY_RESP)
111 u8 tx_tstamp_en:1;
112 int rx_filter;
113
114 u32 refclk_regs[2];
115 u32 refclk_mapped_regs[2];
116};
117
118#if BITS_PER_LONG == 32
119#define BNXT_READ_TIME64(ptp, dst, src) \
120do { \
121 spin_lock_bh(&(ptp)->ptp_lock); \
122 (dst) = (src); \
123 spin_unlock_bh(&(ptp)->ptp_lock); \
124} while (0)
125#else
126#define BNXT_READ_TIME64(ptp, dst, src) \
127 ((dst) = READ_ONCE(src))
128#endif
129
130int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off);
131void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2);
132void bnxt_ptp_reapply_pps(struct bnxt *bp);
133int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr);
134int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);
135int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb);
136int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts);
137int bnxt_ptp_init(struct bnxt *bp);
138void bnxt_ptp_clear(struct bnxt *bp);
139#endif
140
