LXR linux/drivers/net/ethernet/intel/ice/ice

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2018, Intel Corporation. */
   3
   4#ifndef _ICE_CONTROLQ_H_
   5#define _ICE_CONTROLQ_H_
   6
   7#include "ice_adminq_cmd.h"
   8
   9/* Maximum buffer lengths for all control queue types */
  10#define ICE_AQ_MAX_BUF_LEN 4096
  11#define ICE_MBXQ_MAX_BUF_LEN 4096
  12#define ICE_SBQ_MAX_BUF_LEN 512
  13
  14#define ICE_CTL_Q_DESC(R, i) \
  15        (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
  16
  17#define ICE_CTL_Q_DESC_UNUSED(R) \
  18        ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  19               (R)->next_to_clean - (R)->next_to_use - 1))
  20
  21/* Defines that help manage the driver vs FW API checks.
  22 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
  23 */
  24#define EXP_FW_API_VER_BRANCH           0x00
  25#define EXP_FW_API_VER_MAJOR            0x01
  26#define EXP_FW_API_VER_MINOR            0x05
  27
  28/* Different control queue types: These are mainly for SW consumption. */
  29enum ice_ctl_q {
  30        ICE_CTL_Q_UNKNOWN = 0,
  31        ICE_CTL_Q_ADMIN,
  32        ICE_CTL_Q_MAILBOX,
  33        ICE_CTL_Q_SB,
  34};
  35
  36/* Control Queue timeout settings - max delay 1s */
  37#define ICE_CTL_Q_SQ_CMD_TIMEOUT        10000 /* Count 10000 times */
  38#define ICE_CTL_Q_SQ_CMD_USEC           100   /* Check every 100usec */
  39#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT    10    /* Count 10 times */
  40#define ICE_CTL_Q_ADMIN_INIT_MSEC       100   /* Check every 100msec */
  41
  42struct ice_ctl_q_ring {
  43        void *dma_head;                 /* Virtual address to DMA head */
  44        struct ice_dma_mem desc_buf;    /* descriptor ring memory */
  45        void *cmd_buf;                  /* command buffer memory */
  46
  47        union {
  48                struct ice_dma_mem *sq_bi;
  49                struct ice_dma_mem *rq_bi;
  50        } r;
  51
  52        u16 count;              /* Number of descriptors */
  53
  54        /* used for interrupt processing */
  55        u16 next_to_use;
  56        u16 next_to_clean;
  57
  58        /* used for queue tracking */
  59        u32 head;
  60        u32 tail;
  61        u32 len;
  62        u32 bah;
  63        u32 bal;
  64        u32 len_mask;
  65        u32 len_ena_mask;
  66        u32 len_crit_mask;
  67        u32 head_mask;
  68};
  69
  70/* sq transaction details */
  71struct ice_sq_cd {
  72        struct ice_aq_desc *wb_desc;
  73};
  74
  75#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
  76
  77/* rq event information */
  78struct ice_rq_event_info {
  79        struct ice_aq_desc desc;
  80        u16 msg_len;
  81        u16 buf_len;
  82        u8 *msg_buf;
  83};
  84
  85/* Control Queue information */
  86struct ice_ctl_q_info {
  87        enum ice_ctl_q qtype;
  88        struct ice_ctl_q_ring rq;       /* receive queue */
  89        struct ice_ctl_q_ring sq;       /* send queue */
  90        u32 sq_cmd_timeout;             /* send queue cmd write back timeout */
  91        u16 num_rq_entries;             /* receive queue depth */
  92        u16 num_sq_entries;             /* send queue depth */
  93        u16 rq_buf_size;                /* receive queue buffer size */
  94        u16 sq_buf_size;                /* send queue buffer size */
  95        enum ice_aq_err sq_last_status; /* last status on send queue */
  96        struct mutex sq_lock;           /* Send queue lock */
  97        struct mutex rq_lock;           /* Receive queue lock */
  98};
  99
 100#endif /* _ICE_CONTROLQ_H_ */
 101