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7
8#include <linux/etherdevice.h>
9#include <linux/module.h>
10#include <linux/pci.h>
11
12#include "otx2_common.h"
13#include "otx2_reg.h"
14#include "cn10k.h"
15
16#define DRV_NAME "rvu_nicvf"
17#define DRV_STRING "Marvell RVU NIC Virtual Function Driver"
18
19static const struct pci_device_id otx2_vf_id_table[] = {
20 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) },
21 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) },
22 { }
23};
24
25MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
26MODULE_DESCRIPTION(DRV_STRING);
27MODULE_LICENSE("GPL v2");
28MODULE_DEVICE_TABLE(pci, otx2_vf_id_table);
29
30
31enum {
32 RVU_VF_INT_VEC_MBOX = 0x0,
33};
34
35static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf,
36 struct mbox_msghdr *msg)
37{
38 if (msg->id >= MBOX_MSG_MAX) {
39 dev_err(vf->dev,
40 "Mbox msg with unknown ID %d\n", msg->id);
41 return;
42 }
43
44 if (msg->sig != OTX2_MBOX_RSP_SIG) {
45 dev_err(vf->dev,
46 "Mbox msg with wrong signature %x, ID %d\n",
47 msg->sig, msg->id);
48 return;
49 }
50
51 if (msg->rc == MBOX_MSG_INVALID) {
52 dev_err(vf->dev,
53 "PF/AF says the sent msg(s) %d were invalid\n",
54 msg->id);
55 return;
56 }
57
58 switch (msg->id) {
59 case MBOX_MSG_READY:
60 vf->pcifunc = msg->pcifunc;
61 break;
62 case MBOX_MSG_MSIX_OFFSET:
63 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg);
64 break;
65 case MBOX_MSG_NPA_LF_ALLOC:
66 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg);
67 break;
68 case MBOX_MSG_NIX_LF_ALLOC:
69 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg);
70 break;
71 case MBOX_MSG_NIX_TXSCH_ALLOC:
72 mbox_handler_nix_txsch_alloc(vf,
73 (struct nix_txsch_alloc_rsp *)msg);
74 break;
75 case MBOX_MSG_NIX_BP_ENABLE:
76 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg);
77 break;
78 default:
79 if (msg->rc)
80 dev_err(vf->dev,
81 "Mbox msg response has err %d, ID %d\n",
82 msg->rc, msg->id);
83 }
84}
85
86static void otx2vf_vfaf_mbox_handler(struct work_struct *work)
87{
88 struct otx2_mbox_dev *mdev;
89 struct mbox_hdr *rsp_hdr;
90 struct mbox_msghdr *msg;
91 struct otx2_mbox *mbox;
92 struct mbox *af_mbox;
93 int offset, id;
94
95 af_mbox = container_of(work, struct mbox, mbox_wrk);
96 mbox = &af_mbox->mbox;
97 mdev = &mbox->dev[0];
98 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
99 if (af_mbox->num_msgs == 0)
100 return;
101 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
102
103 for (id = 0; id < af_mbox->num_msgs; id++) {
104 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
105 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg);
106 offset = mbox->rx_start + msg->next_msgoff;
107 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
108 __otx2_mbox_reset(mbox, 0);
109 mdev->msgs_acked++;
110 }
111}
112
113static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf,
114 struct mbox_msghdr *req)
115{
116 struct msg_rsp *rsp;
117 int err;
118
119
120 if (req->sig != OTX2_MBOX_REQ_SIG) {
121 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
122 return -ENODEV;
123 }
124
125 switch (req->id) {
126 case MBOX_MSG_CGX_LINK_EVENT:
127 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(
128 &vf->mbox.mbox_up, 0,
129 sizeof(struct msg_rsp));
130 if (!rsp)
131 return -ENOMEM;
132
133 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
134 rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
135 rsp->hdr.pcifunc = 0;
136 rsp->hdr.rc = 0;
137 err = otx2_mbox_up_handler_cgx_link_event(
138 vf, (struct cgx_link_info_msg *)req, rsp);
139 return err;
140 default:
141 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
142 return -ENODEV;
143 }
144 return 0;
145}
146
147static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work)
148{
149 struct otx2_mbox_dev *mdev;
150 struct mbox_hdr *rsp_hdr;
151 struct mbox_msghdr *msg;
152 struct otx2_mbox *mbox;
153 struct mbox *vf_mbox;
154 struct otx2_nic *vf;
155 int offset, id;
156
157 vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
158 vf = vf_mbox->pfvf;
159 mbox = &vf_mbox->mbox_up;
160 mdev = &mbox->dev[0];
161
162 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
163 if (vf_mbox->up_num_msgs == 0)
164 return;
165
166 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
167
168 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
169 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
170 otx2vf_process_mbox_msg_up(vf, msg);
171 offset = mbox->rx_start + msg->next_msgoff;
172 }
173
174 otx2_mbox_msg_send(mbox, 0);
175}
176
177static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq)
178{
179 struct otx2_nic *vf = (struct otx2_nic *)vf_irq;
180 struct otx2_mbox_dev *mdev;
181 struct otx2_mbox *mbox;
182 struct mbox_hdr *hdr;
183
184
185 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
186
187
188 smp_rmb();
189
190
191 mbox = &vf->mbox.mbox;
192 mdev = &mbox->dev[0];
193 otx2_sync_mbox_bbuf(mbox, 0);
194
195 trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0));
196
197 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
198 if (hdr->num_msgs) {
199 vf->mbox.num_msgs = hdr->num_msgs;
200 hdr->num_msgs = 0;
201 memset(mbox->hwbase + mbox->rx_start, 0,
202 ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
203 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk);
204 }
205
206 mbox = &vf->mbox.mbox_up;
207 mdev = &mbox->dev[0];
208 otx2_sync_mbox_bbuf(mbox, 0);
209
210 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
211 if (hdr->num_msgs) {
212 vf->mbox.up_num_msgs = hdr->num_msgs;
213 hdr->num_msgs = 0;
214 memset(mbox->hwbase + mbox->rx_start, 0,
215 ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
216 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk);
217 }
218
219 return IRQ_HANDLED;
220}
221
222static void otx2vf_disable_mbox_intr(struct otx2_nic *vf)
223{
224 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX);
225
226
227 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0));
228 free_irq(vector, vf);
229}
230
231static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
232{
233 struct otx2_hw *hw = &vf->hw;
234 struct msg_req *req;
235 char *irq_name;
236 int err;
237
238
239 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE];
240 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox");
241 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX),
242 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf);
243 if (err) {
244 dev_err(vf->dev,
245 "RVUPF: IRQ registration failed for VFAF mbox irq\n");
246 return err;
247 }
248
249
250
251
252 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
253 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0));
254
255 if (!probe_pf)
256 return 0;
257
258
259 req = otx2_mbox_alloc_msg_ready(&vf->mbox);
260 if (!req) {
261 otx2vf_disable_mbox_intr(vf);
262 return -ENOMEM;
263 }
264
265 err = otx2_sync_mbox_msg(&vf->mbox);
266 if (err) {
267 dev_warn(vf->dev,
268 "AF not responding to mailbox, deferring probe\n");
269 otx2vf_disable_mbox_intr(vf);
270 return -EPROBE_DEFER;
271 }
272 return 0;
273}
274
275static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf)
276{
277 struct mbox *mbox = &vf->mbox;
278
279 if (vf->mbox_wq) {
280 flush_workqueue(vf->mbox_wq);
281 destroy_workqueue(vf->mbox_wq);
282 vf->mbox_wq = NULL;
283 }
284
285 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
286 iounmap((void __iomem *)mbox->mbox.hwbase);
287
288 otx2_mbox_destroy(&mbox->mbox);
289 otx2_mbox_destroy(&mbox->mbox_up);
290}
291
292static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf)
293{
294 struct mbox *mbox = &vf->mbox;
295 void __iomem *hwbase;
296 int err;
297
298 mbox->pfvf = vf;
299 vf->mbox_wq = alloc_workqueue("otx2_vfaf_mailbox",
300 WQ_UNBOUND | WQ_HIGHPRI |
301 WQ_MEM_RECLAIM, 1);
302 if (!vf->mbox_wq)
303 return -ENOMEM;
304
305 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) {
306
307
308
309 hwbase = vf->reg_base + RVU_VF_MBOX_REGION;
310 } else {
311
312
313
314
315 hwbase = ioremap_wc(pci_resource_start(vf->pdev,
316 PCI_MBOX_BAR_NUM),
317 pci_resource_len(vf->pdev,
318 PCI_MBOX_BAR_NUM));
319 if (!hwbase) {
320 dev_err(vf->dev, "Unable to map VFAF mailbox region\n");
321 err = -ENOMEM;
322 goto exit;
323 }
324 }
325
326 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base,
327 MBOX_DIR_VFPF, 1);
328 if (err)
329 goto exit;
330
331 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base,
332 MBOX_DIR_VFPF_UP, 1);
333 if (err)
334 goto exit;
335
336 err = otx2_mbox_bbuf_init(mbox, vf->pdev);
337 if (err)
338 goto exit;
339
340 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler);
341 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler);
342 mutex_init(&mbox->lock);
343
344 return 0;
345exit:
346 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
347 iounmap(hwbase);
348 destroy_workqueue(vf->mbox_wq);
349 return err;
350}
351
352static int otx2vf_open(struct net_device *netdev)
353{
354 struct otx2_nic *vf;
355 int err;
356
357 err = otx2_open(netdev);
358 if (err)
359 return err;
360
361
362 vf = netdev_priv(netdev);
363 if (is_otx2_lbkvf(vf->pdev)) {
364 pr_info("%s NIC Link is UP\n", netdev->name);
365 netif_carrier_on(netdev);
366 netif_tx_start_all_queues(netdev);
367 }
368
369 return 0;
370}
371
372static int otx2vf_stop(struct net_device *netdev)
373{
374 return otx2_stop(netdev);
375}
376
377static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev)
378{
379 struct otx2_nic *vf = netdev_priv(netdev);
380 int qidx = skb_get_queue_mapping(skb);
381 struct otx2_snd_queue *sq;
382 struct netdev_queue *txq;
383
384 sq = &vf->qset.sq[qidx];
385 txq = netdev_get_tx_queue(netdev, qidx);
386
387 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
388 netif_tx_stop_queue(txq);
389
390
391 smp_mb();
392 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
393 > sq->sqe_thresh)
394 netif_tx_wake_queue(txq);
395
396 return NETDEV_TX_BUSY;
397 }
398
399 return NETDEV_TX_OK;
400}
401
402static void otx2vf_set_rx_mode(struct net_device *netdev)
403{
404 struct otx2_nic *vf = netdev_priv(netdev);
405
406 queue_work(vf->otx2_wq, &vf->rx_mode_work);
407}
408
409static void otx2vf_do_set_rx_mode(struct work_struct *work)
410{
411 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work);
412 struct net_device *netdev = vf->netdev;
413 unsigned int flags = netdev->flags;
414 struct nix_rx_mode *req;
415
416 mutex_lock(&vf->mbox.lock);
417
418 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox);
419 if (!req) {
420 mutex_unlock(&vf->mbox.lock);
421 return;
422 }
423
424 req->mode = NIX_RX_MODE_UCAST;
425
426 if (flags & IFF_PROMISC)
427 req->mode |= NIX_RX_MODE_PROMISC;
428 if (flags & (IFF_ALLMULTI | IFF_MULTICAST))
429 req->mode |= NIX_RX_MODE_ALLMULTI;
430
431 req->mode |= NIX_RX_MODE_USE_MCE;
432
433 otx2_sync_mbox_msg(&vf->mbox);
434
435 mutex_unlock(&vf->mbox.lock);
436}
437
438static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu)
439{
440 bool if_up = netif_running(netdev);
441 int err = 0;
442
443 if (if_up)
444 otx2vf_stop(netdev);
445
446 netdev_info(netdev, "Changing MTU from %d to %d\n",
447 netdev->mtu, new_mtu);
448 netdev->mtu = new_mtu;
449
450 if (if_up)
451 err = otx2vf_open(netdev);
452
453 return err;
454}
455
456static void otx2vf_reset_task(struct work_struct *work)
457{
458 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task);
459
460 rtnl_lock();
461
462 if (netif_running(vf->netdev)) {
463 otx2vf_stop(vf->netdev);
464 vf->reset_count++;
465 otx2vf_open(vf->netdev);
466 }
467
468 rtnl_unlock();
469}
470
471static int otx2vf_set_features(struct net_device *netdev,
472 netdev_features_t features)
473{
474 netdev_features_t changed = features ^ netdev->features;
475 bool ntuple_enabled = !!(features & NETIF_F_NTUPLE);
476 struct otx2_nic *vf = netdev_priv(netdev);
477
478 if (changed & NETIF_F_NTUPLE) {
479 if (!ntuple_enabled) {
480 otx2_mcam_flow_del(vf);
481 return 0;
482 }
483
484 if (!otx2_get_maxflows(vf->flow_cfg)) {
485 netdev_err(netdev,
486 "Can't enable NTUPLE, MCAM entries not allocated\n");
487 return -EINVAL;
488 }
489 }
490 return 0;
491}
492
493static const struct net_device_ops otx2vf_netdev_ops = {
494 .ndo_open = otx2vf_open,
495 .ndo_stop = otx2vf_stop,
496 .ndo_start_xmit = otx2vf_xmit,
497 .ndo_set_rx_mode = otx2vf_set_rx_mode,
498 .ndo_set_mac_address = otx2_set_mac_address,
499 .ndo_change_mtu = otx2vf_change_mtu,
500 .ndo_set_features = otx2vf_set_features,
501 .ndo_get_stats64 = otx2_get_stats64,
502 .ndo_tx_timeout = otx2_tx_timeout,
503};
504
505static int otx2_wq_init(struct otx2_nic *vf)
506{
507 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq");
508 if (!vf->otx2_wq)
509 return -ENOMEM;
510
511 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode);
512 INIT_WORK(&vf->reset_task, otx2vf_reset_task);
513 return 0;
514}
515
516static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf)
517{
518 struct otx2_hw *hw = &vf->hw;
519 int num_vec, err;
520
521 num_vec = hw->nix_msixoff;
522 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
523
524 otx2vf_disable_mbox_intr(vf);
525 pci_free_irq_vectors(hw->pdev);
526 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
527 if (err < 0) {
528 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n",
529 __func__, num_vec);
530 return err;
531 }
532
533 return otx2vf_register_mbox_intr(vf, false);
534}
535
536static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
537{
538 int num_vec = pci_msix_vec_count(pdev);
539 struct device *dev = &pdev->dev;
540 struct net_device *netdev;
541 struct otx2_nic *vf;
542 struct otx2_hw *hw;
543 int err, qcount;
544
545 err = pcim_enable_device(pdev);
546 if (err) {
547 dev_err(dev, "Failed to enable PCI device\n");
548 return err;
549 }
550
551 err = pci_request_regions(pdev, DRV_NAME);
552 if (err) {
553 dev_err(dev, "PCI request regions failed 0x%x\n", err);
554 return err;
555 }
556
557 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
558 if (err) {
559 dev_err(dev, "DMA mask config failed, abort\n");
560 goto err_release_regions;
561 }
562
563 pci_set_master(pdev);
564
565 qcount = num_online_cpus();
566 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount, qcount);
567 if (!netdev) {
568 err = -ENOMEM;
569 goto err_release_regions;
570 }
571
572 pci_set_drvdata(pdev, netdev);
573 SET_NETDEV_DEV(netdev, &pdev->dev);
574 vf = netdev_priv(netdev);
575 vf->netdev = netdev;
576 vf->pdev = pdev;
577 vf->dev = dev;
578 vf->iommu_domain = iommu_get_domain_for_dev(dev);
579
580 vf->flags |= OTX2_FLAG_INTF_DOWN;
581 hw = &vf->hw;
582 hw->pdev = vf->pdev;
583 hw->rx_queues = qcount;
584 hw->tx_queues = qcount;
585 hw->max_queues = qcount;
586
587 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
588 GFP_KERNEL);
589 if (!hw->irq_name) {
590 err = -ENOMEM;
591 goto err_free_netdev;
592 }
593
594 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
595 sizeof(cpumask_var_t), GFP_KERNEL);
596 if (!hw->affinity_mask) {
597 err = -ENOMEM;
598 goto err_free_netdev;
599 }
600
601 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
602 if (err < 0) {
603 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
604 __func__, num_vec);
605 goto err_free_netdev;
606 }
607
608 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
609 if (!vf->reg_base) {
610 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
611 err = -ENOMEM;
612 goto err_free_irq_vectors;
613 }
614
615 otx2_setup_dev_hw_settings(vf);
616
617 err = otx2vf_vfaf_mbox_init(vf);
618 if (err)
619 goto err_free_irq_vectors;
620
621
622 err = otx2vf_register_mbox_intr(vf, true);
623 if (err)
624 goto err_mbox_destroy;
625
626
627 err = otx2_attach_npa_nix(vf);
628 if (err)
629 goto err_disable_mbox_intr;
630
631 err = otx2vf_realloc_msix_vectors(vf);
632 if (err)
633 goto err_mbox_destroy;
634
635 err = otx2_set_real_num_queues(netdev, qcount, qcount);
636 if (err)
637 goto err_detach_rsrc;
638
639 err = cn10k_lmtst_init(vf);
640 if (err)
641 goto err_detach_rsrc;
642
643
644 otx2_get_mac_from_af(netdev);
645
646 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
647 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
648 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
649 NETIF_F_GSO_UDP_L4;
650 netdev->features = netdev->hw_features;
651
652 netdev->vlan_features |= netdev->features;
653 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
654 NETIF_F_HW_VLAN_STAG_TX;
655 netdev->features |= netdev->hw_features;
656
657 netdev->hw_features |= NETIF_F_NTUPLE;
658 netdev->hw_features |= NETIF_F_RXALL;
659
660 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS;
661 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
662
663 netdev->netdev_ops = &otx2vf_netdev_ops;
664
665 netdev->min_mtu = OTX2_MIN_MTU;
666 netdev->max_mtu = otx2_get_max_mtu(vf);
667
668
669 if (is_otx2_lbkvf(vf->pdev)) {
670 int n;
671
672 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK;
673
674 n -= 1;
675 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n);
676 }
677
678 err = register_netdev(netdev);
679 if (err) {
680 dev_err(dev, "Failed to register netdevice\n");
681 goto err_detach_rsrc;
682 }
683
684 err = otx2_wq_init(vf);
685 if (err)
686 goto err_unreg_netdev;
687
688 otx2vf_set_ethtool_ops(netdev);
689
690 err = otx2vf_mcam_flow_init(vf);
691 if (err)
692 goto err_unreg_netdev;
693
694 err = otx2_register_dl(vf);
695 if (err)
696 goto err_unreg_netdev;
697
698
699 vf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED;
700 vf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED;
701
702 return 0;
703
704err_unreg_netdev:
705 unregister_netdev(netdev);
706err_detach_rsrc:
707 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
708 qmem_free(vf->dev, vf->dync_lmt);
709 otx2_detach_resources(&vf->mbox);
710err_disable_mbox_intr:
711 otx2vf_disable_mbox_intr(vf);
712err_mbox_destroy:
713 otx2vf_vfaf_mbox_destroy(vf);
714err_free_irq_vectors:
715 pci_free_irq_vectors(hw->pdev);
716err_free_netdev:
717 pci_set_drvdata(pdev, NULL);
718 free_netdev(netdev);
719err_release_regions:
720 pci_release_regions(pdev);
721 return err;
722}
723
724static void otx2vf_remove(struct pci_dev *pdev)
725{
726 struct net_device *netdev = pci_get_drvdata(pdev);
727 struct otx2_nic *vf;
728
729 if (!netdev)
730 return;
731
732 vf = netdev_priv(netdev);
733
734 cancel_work_sync(&vf->reset_task);
735 otx2_unregister_dl(vf);
736 unregister_netdev(netdev);
737 if (vf->otx2_wq)
738 destroy_workqueue(vf->otx2_wq);
739 otx2vf_disable_mbox_intr(vf);
740 otx2_detach_resources(&vf->mbox);
741 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
742 qmem_free(vf->dev, vf->dync_lmt);
743 otx2vf_vfaf_mbox_destroy(vf);
744 pci_free_irq_vectors(vf->pdev);
745 pci_set_drvdata(pdev, NULL);
746 free_netdev(netdev);
747
748 pci_release_regions(pdev);
749}
750
751static struct pci_driver otx2vf_driver = {
752 .name = DRV_NAME,
753 .id_table = otx2_vf_id_table,
754 .probe = otx2vf_probe,
755 .remove = otx2vf_remove,
756 .shutdown = otx2vf_remove,
757};
758
759static int __init otx2vf_init_module(void)
760{
761 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
762
763 return pci_register_driver(&otx2vf_driver);
764}
765
766static void __exit otx2vf_cleanup_module(void)
767{
768 pci_unregister_driver(&otx2vf_driver);
769}
770
771module_init(otx2vf_init_module);
772module_exit(otx2vf_cleanup_module);
773
