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8#include <linux/bitops.h>
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/iopoll.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/of_irq.h>
18#include <linux/pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22
23#include "pcie-designware.h"
24
25#define PCL_PINCTRL0 0x002c
26#define PCL_PERST_PLDN_REGEN BIT(12)
27#define PCL_PERST_NOE_REGEN BIT(11)
28#define PCL_PERST_OUT_REGEN BIT(8)
29#define PCL_PERST_PLDN_REGVAL BIT(4)
30#define PCL_PERST_NOE_REGVAL BIT(3)
31#define PCL_PERST_OUT_REGVAL BIT(0)
32
33#define PCL_PIPEMON 0x0044
34#define PCL_PCLK_ALIVE BIT(15)
35
36#define PCL_MODE 0x8000
37#define PCL_MODE_REGEN BIT(8)
38#define PCL_MODE_REGVAL BIT(0)
39
40#define PCL_APP_READY_CTRL 0x8008
41#define PCL_APP_LTSSM_ENABLE BIT(0)
42
43#define PCL_APP_PM0 0x8078
44#define PCL_SYS_AUX_PWR_DET BIT(8)
45
46#define PCL_RCV_INT 0x8108
47#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
48#define PCL_CFG_BW_MGT_STATUS BIT(4)
49#define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
50#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
51#define PCL_CFG_PME_MSI_STATUS BIT(1)
52
53#define PCL_RCV_INTX 0x810c
54#define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)
55#define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)
56#define PCL_RCV_INTX_MASK_SHIFT 8
57#define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
58#define PCL_RCV_INTX_STATUS_SHIFT 0
59
60#define PCL_STATUS_LINK 0x8140
61#define PCL_RDLH_LINK_UP BIT(1)
62#define PCL_XMLH_LINK_UP BIT(0)
63
64struct uniphier_pcie_priv {
65 void __iomem *base;
66 struct dw_pcie pci;
67 struct clk *clk;
68 struct reset_control *rst;
69 struct phy *phy;
70 struct irq_domain *legacy_irq_domain;
71};
72
73#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
74
75static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
76 bool enable)
77{
78 u32 val;
79
80 val = readl(priv->base + PCL_APP_READY_CTRL);
81 if (enable)
82 val |= PCL_APP_LTSSM_ENABLE;
83 else
84 val &= ~PCL_APP_LTSSM_ENABLE;
85 writel(val, priv->base + PCL_APP_READY_CTRL);
86}
87
88static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
89{
90 u32 val;
91
92
93 val = readl(priv->base + PCL_MODE);
94 val |= PCL_MODE_REGEN;
95 val &= ~PCL_MODE_REGVAL;
96 writel(val, priv->base + PCL_MODE);
97
98
99 val = readl(priv->base + PCL_APP_PM0);
100 val |= PCL_SYS_AUX_PWR_DET;
101 writel(val, priv->base + PCL_APP_PM0);
102
103
104 val = readl(priv->base + PCL_PINCTRL0);
105 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
106 | PCL_PERST_PLDN_REGVAL);
107 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
108 | PCL_PERST_PLDN_REGEN;
109 writel(val, priv->base + PCL_PINCTRL0);
110
111 uniphier_pcie_ltssm_enable(priv, false);
112
113 usleep_range(100000, 200000);
114
115
116 val = readl(priv->base + PCL_PINCTRL0);
117 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
118 writel(val, priv->base + PCL_PINCTRL0);
119}
120
121static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
122{
123 u32 status;
124 int ret;
125
126
127 ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
128 status & PCL_PCLK_ALIVE, 100000, 1000000);
129 if (ret) {
130 dev_err(priv->pci.dev,
131 "Failed to initialize controller in RC mode\n");
132 return ret;
133 }
134
135 return 0;
136}
137
138static int uniphier_pcie_link_up(struct dw_pcie *pci)
139{
140 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
141 u32 val, mask;
142
143 val = readl(priv->base + PCL_STATUS_LINK);
144 mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
145
146 return (val & mask) == mask;
147}
148
149static int uniphier_pcie_start_link(struct dw_pcie *pci)
150{
151 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
152
153 uniphier_pcie_ltssm_enable(priv, true);
154
155 return 0;
156}
157
158static void uniphier_pcie_stop_link(struct dw_pcie *pci)
159{
160 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
161
162 uniphier_pcie_ltssm_enable(priv, false);
163}
164
165static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
166{
167 writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
168 writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
169}
170
171static void uniphier_pcie_irq_ack(struct irq_data *d)
172{
173 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
174 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
175 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
176 u32 val;
177
178 val = readl(priv->base + PCL_RCV_INTX);
179 val &= ~PCL_RCV_INTX_ALL_STATUS;
180 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
181 writel(val, priv->base + PCL_RCV_INTX);
182}
183
184static void uniphier_pcie_irq_mask(struct irq_data *d)
185{
186 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
187 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
188 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
189 u32 val;
190
191 val = readl(priv->base + PCL_RCV_INTX);
192 val &= ~PCL_RCV_INTX_ALL_MASK;
193 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
194 writel(val, priv->base + PCL_RCV_INTX);
195}
196
197static void uniphier_pcie_irq_unmask(struct irq_data *d)
198{
199 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
200 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
201 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
202 u32 val;
203
204 val = readl(priv->base + PCL_RCV_INTX);
205 val &= ~PCL_RCV_INTX_ALL_MASK;
206 val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
207 writel(val, priv->base + PCL_RCV_INTX);
208}
209
210static struct irq_chip uniphier_pcie_irq_chip = {
211 .name = "PCI",
212 .irq_ack = uniphier_pcie_irq_ack,
213 .irq_mask = uniphier_pcie_irq_mask,
214 .irq_unmask = uniphier_pcie_irq_unmask,
215};
216
217static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
218 irq_hw_number_t hwirq)
219{
220 irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
221 handle_level_irq);
222 irq_set_chip_data(irq, domain->host_data);
223
224 return 0;
225}
226
227static const struct irq_domain_ops uniphier_intx_domain_ops = {
228 .map = uniphier_pcie_intx_map,
229};
230
231static void uniphier_pcie_irq_handler(struct irq_desc *desc)
232{
233 struct pcie_port *pp = irq_desc_get_handler_data(desc);
234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
235 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
236 struct irq_chip *chip = irq_desc_get_chip(desc);
237 unsigned long reg;
238 u32 val, bit;
239
240
241 val = readl(priv->base + PCL_RCV_INT);
242
243 if (val & PCL_CFG_BW_MGT_STATUS)
244 dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
245 if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
246 dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
247 if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
248 dev_dbg(pci->dev, "Root Error\n");
249 if (val & PCL_CFG_PME_MSI_STATUS)
250 dev_dbg(pci->dev, "PME Interrupt\n");
251
252 writel(val, priv->base + PCL_RCV_INT);
253
254
255 chained_irq_enter(chip, desc);
256
257 val = readl(priv->base + PCL_RCV_INTX);
258 reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
259
260 for_each_set_bit(bit, ®, PCI_NUM_INTX)
261 generic_handle_domain_irq(priv->legacy_irq_domain, bit);
262
263 chained_irq_exit(chip, desc);
264}
265
266static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
267{
268 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
269 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
270 struct device_node *np = pci->dev->of_node;
271 struct device_node *np_intc;
272 int ret = 0;
273
274 np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
275 if (!np_intc) {
276 dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
277 return -EINVAL;
278 }
279
280 pp->irq = irq_of_parse_and_map(np_intc, 0);
281 if (!pp->irq) {
282 dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
283 ret = -EINVAL;
284 goto out_put_node;
285 }
286
287 priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
288 &uniphier_intx_domain_ops, pp);
289 if (!priv->legacy_irq_domain) {
290 dev_err(pci->dev, "Failed to get INTx domain\n");
291 ret = -ENODEV;
292 goto out_put_node;
293 }
294
295 irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
296 pp);
297
298out_put_node:
299 of_node_put(np_intc);
300 return ret;
301}
302
303static int uniphier_pcie_host_init(struct pcie_port *pp)
304{
305 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
306 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
307 int ret;
308
309 ret = uniphier_pcie_config_legacy_irq(pp);
310 if (ret)
311 return ret;
312
313 uniphier_pcie_irq_enable(priv);
314
315 return 0;
316}
317
318static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
319 .host_init = uniphier_pcie_host_init,
320};
321
322static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
323{
324 int ret;
325
326 ret = clk_prepare_enable(priv->clk);
327 if (ret)
328 return ret;
329
330 ret = reset_control_deassert(priv->rst);
331 if (ret)
332 goto out_clk_disable;
333
334 uniphier_pcie_init_rc(priv);
335
336 ret = phy_init(priv->phy);
337 if (ret)
338 goto out_rst_assert;
339
340 ret = uniphier_pcie_wait_rc(priv);
341 if (ret)
342 goto out_phy_exit;
343
344 return 0;
345
346out_phy_exit:
347 phy_exit(priv->phy);
348out_rst_assert:
349 reset_control_assert(priv->rst);
350out_clk_disable:
351 clk_disable_unprepare(priv->clk);
352
353 return ret;
354}
355
356static const struct dw_pcie_ops dw_pcie_ops = {
357 .start_link = uniphier_pcie_start_link,
358 .stop_link = uniphier_pcie_stop_link,
359 .link_up = uniphier_pcie_link_up,
360};
361
362static int uniphier_pcie_probe(struct platform_device *pdev)
363{
364 struct device *dev = &pdev->dev;
365 struct uniphier_pcie_priv *priv;
366 int ret;
367
368 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
369 if (!priv)
370 return -ENOMEM;
371
372 priv->pci.dev = dev;
373 priv->pci.ops = &dw_pcie_ops;
374
375 priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
376 if (IS_ERR(priv->base))
377 return PTR_ERR(priv->base);
378
379 priv->clk = devm_clk_get(dev, NULL);
380 if (IS_ERR(priv->clk))
381 return PTR_ERR(priv->clk);
382
383 priv->rst = devm_reset_control_get_shared(dev, NULL);
384 if (IS_ERR(priv->rst))
385 return PTR_ERR(priv->rst);
386
387 priv->phy = devm_phy_optional_get(dev, "pcie-phy");
388 if (IS_ERR(priv->phy))
389 return PTR_ERR(priv->phy);
390
391 platform_set_drvdata(pdev, priv);
392
393 ret = uniphier_pcie_host_enable(priv);
394 if (ret)
395 return ret;
396
397 priv->pci.pp.ops = &uniphier_pcie_host_ops;
398
399 return dw_pcie_host_init(&priv->pci.pp);
400}
401
402static const struct of_device_id uniphier_pcie_match[] = {
403 { .compatible = "socionext,uniphier-pcie", },
404 { },
405};
406
407static struct platform_driver uniphier_pcie_driver = {
408 .probe = uniphier_pcie_probe,
409 .driver = {
410 .name = "uniphier-pcie",
411 .of_match_table = uniphier_pcie_match,
412 },
413};
414builtin_platform_driver(uniphier_pcie_driver);
415
