LXR linux/drivers/scsi/mpi3mr/mpi3mr.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Driver for Broadcom MPI3 Storage Controllers
   4 *
   5 * Copyright (C) 2017-2021 Broadcom Inc.
   6 *  (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
   7 *
   8 */
   9
  10#ifndef MPI3MR_H_INCLUDED
  11#define MPI3MR_H_INCLUDED
  12
  13#include <linux/blkdev.h>
  14#include <linux/blk-mq.h>
  15#include <linux/blk-mq-pci.h>
  16#include <linux/delay.h>
  17#include <linux/dmapool.h>
  18#include <linux/errno.h>
  19#include <linux/init.h>
  20#include <linux/io.h>
  21#include <linux/interrupt.h>
  22#include <linux/kernel.h>
  23#include <linux/miscdevice.h>
  24#include <linux/module.h>
  25#include <linux/pci.h>
  26#include <linux/poll.h>
  27#include <linux/sched.h>
  28#include <linux/slab.h>
  29#include <linux/types.h>
  30#include <linux/uaccess.h>
  31#include <linux/utsname.h>
  32#include <linux/version.h>
  33#include <linux/workqueue.h>
  34#include <asm/unaligned.h>
  35#include <scsi/scsi.h>
  36#include <scsi/scsi_cmnd.h>
  37#include <scsi/scsi_dbg.h>
  38#include <scsi/scsi_device.h>
  39#include <scsi/scsi_host.h>
  40#include <scsi/scsi_tcq.h>
  41
  42#include "mpi/mpi30_transport.h"
  43#include "mpi/mpi30_cnfg.h"
  44#include "mpi/mpi30_image.h"
  45#include "mpi/mpi30_init.h"
  46#include "mpi/mpi30_ioc.h"
  47#include "mpi/mpi30_sas.h"
  48#include "mpi3mr_debug.h"
  49
  50/* Global list and lock for storing multiple adapters managed by the driver */
  51extern spinlock_t mrioc_list_lock;
  52extern struct list_head mrioc_list;
  53extern int prot_mask;
  54
  55#define MPI3MR_DRIVER_VERSION   "00.255.45.01"
  56#define MPI3MR_DRIVER_RELDATE   "12-December-2020"
  57
  58#define MPI3MR_DRIVER_NAME      "mpi3mr"
  59#define MPI3MR_DRIVER_LICENSE   "GPL"
  60#define MPI3MR_DRIVER_AUTHOR    "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
  61#define MPI3MR_DRIVER_DESC      "MPI3 Storage Controller Device Driver"
  62
  63#define MPI3MR_NAME_LENGTH      32
  64#define IOCNAME                 "%s: "
  65
  66/* Definitions for internal SGL and Chain SGL buffers */
  67#define MPI3MR_PAGE_SIZE_4K             4096
  68#define MPI3MR_SG_DEPTH         (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
  69
  70/* Definitions for MAX values for shost */
  71#define MPI3MR_MAX_CMDS_LUN     7
  72#define MPI3MR_MAX_CDB_LENGTH   32
  73
  74/* Admin queue management definitions */
  75#define MPI3MR_ADMIN_REQ_Q_SIZE         (2 * MPI3MR_PAGE_SIZE_4K)
  76#define MPI3MR_ADMIN_REPLY_Q_SIZE       (4 * MPI3MR_PAGE_SIZE_4K)
  77#define MPI3MR_ADMIN_REQ_FRAME_SZ       128
  78#define MPI3MR_ADMIN_REPLY_FRAME_SZ     16
  79
  80/* Operational queue management definitions */
  81#define MPI3MR_OP_REQ_Q_QD              512
  82#define MPI3MR_OP_REP_Q_QD              4096
  83#define MPI3MR_OP_REQ_Q_SEG_SIZE        4096
  84#define MPI3MR_OP_REP_Q_SEG_SIZE        4096
  85#define MPI3MR_MAX_SEG_LIST_SIZE        4096
  86
  87/* Reserved Host Tag definitions */
  88#define MPI3MR_HOSTTAG_INVALID          0xFFFF
  89#define MPI3MR_HOSTTAG_INITCMDS         1
  90#define MPI3MR_HOSTTAG_IOCTLCMDS        2
  91#define MPI3MR_HOSTTAG_BLK_TMS          5
  92
  93#define MPI3MR_NUM_DEVRMCMD             1
  94#define MPI3MR_HOSTTAG_DEVRMCMD_MIN     (MPI3MR_HOSTTAG_BLK_TMS + 1)
  95#define MPI3MR_HOSTTAG_DEVRMCMD_MAX     (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
  96                                                MPI3MR_NUM_DEVRMCMD - 1)
  97
  98#define MPI3MR_INTERNAL_CMDS_RESVD     MPI3MR_HOSTTAG_DEVRMCMD_MAX
  99
 100/* Reduced resource count definition for crash kernel */
 101#define MPI3MR_HOST_IOS_KDUMP           128
 102
 103/* command/controller interaction timeout definitions in seconds */
 104#define MPI3MR_INTADMCMD_TIMEOUT                10
 105#define MPI3MR_PORTENABLE_TIMEOUT               300
 106#define MPI3MR_ABORTTM_TIMEOUT                  30
 107#define MPI3MR_RESETTM_TIMEOUT                  30
 108#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT        5
 109#define MPI3MR_TSUPDATE_INTERVAL                900
 110#define MPI3MR_DEFAULT_SHUTDOWN_TIME            120
 111#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT        180
 112
 113#define MPI3MR_WATCHDOG_INTERVAL                1000 /* in milli seconds */
 114
 115/* Internal admin command state definitions*/
 116#define MPI3MR_CMD_NOTUSED      0x8000
 117#define MPI3MR_CMD_COMPLETE     0x0001
 118#define MPI3MR_CMD_PENDING      0x0002
 119#define MPI3MR_CMD_REPLY_VALID  0x0004
 120#define MPI3MR_CMD_RESET        0x0008
 121
 122/* Definitions for Event replies and sense buffer allocated per controller */
 123#define MPI3MR_NUM_EVT_REPLIES  64
 124#define MPI3MR_SENSEBUF_SZ      256
 125#define MPI3MR_SENSEBUF_FACTOR  3
 126#define MPI3MR_CHAINBUF_FACTOR  3
 127#define MPI3MR_CHAINBUFDIX_FACTOR       2
 128
 129/* Invalid target device handle */
 130#define MPI3MR_INVALID_DEV_HANDLE       0xFFFF
 131
 132/* Controller Reset related definitions */
 133#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT      5
 134#define MPI3MR_MAX_RESET_RETRY_COUNT            3
 135
 136/* ResponseCode definitions */
 137#define MPI3MR_RI_MASK_RESPCODE         (0x000000FF)
 138#define MPI3MR_RSP_TM_COMPLETE          0x00
 139#define MPI3MR_RSP_INVALID_FRAME        0x02
 140#define MPI3MR_RSP_TM_NOT_SUPPORTED     0x04
 141#define MPI3MR_RSP_TM_FAILED            0x05
 142#define MPI3MR_RSP_TM_SUCCEEDED         0x08
 143#define MPI3MR_RSP_TM_INVALID_LUN       0x09
 144#define MPI3MR_RSP_TM_OVERLAPPED_TAG    0x0A
 145#define MPI3MR_RSP_IO_QUEUED_ON_IOC \
 146                        MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
 147
 148#define MPI3MR_DEFAULT_MDTS     (128 * 1024)
 149/* Command retry count definitions */
 150#define MPI3MR_DEV_RMHS_RETRY_COUNT 3
 151
 152/* Default target device queue depth */
 153#define MPI3MR_DEFAULT_SDEV_QD  32
 154
 155/* Definitions for Threaded IRQ poll*/
 156#define MPI3MR_IRQ_POLL_SLEEP                   2
 157#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT         8
 158
 159/* Definitions for the controller security status*/
 160#define MPI3MR_CTLR_SECURITY_STATUS_MASK        0x0C
 161#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK      0x02
 162
 163#define MPI3MR_INVALID_DEVICE                   0x00
 164#define MPI3MR_CONFIG_SECURE_DEVICE             0x04
 165#define MPI3MR_HARD_SECURE_DEVICE               0x08
 166#define MPI3MR_TAMPERED_DEVICE                  0x0C
 167
 168/* SGE Flag definition */
 169#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
 170        (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
 171        MPI3_SGE_FLAGS_END_OF_LIST)
 172
 173/* MSI Index from Reply Queue Index */
 174#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset)       (qidx + offset)
 175
 176/* IOC State definitions */
 177enum mpi3mr_iocstate {
 178        MRIOC_STATE_READY = 1,
 179        MRIOC_STATE_RESET,
 180        MRIOC_STATE_FAULT,
 181        MRIOC_STATE_BECOMING_READY,
 182        MRIOC_STATE_RESET_REQUESTED,
 183        MRIOC_STATE_UNRECOVERABLE,
 184};
 185
 186/* Init type definitions */
 187enum mpi3mr_init_type {
 188        MPI3MR_IT_INIT = 0,
 189        MPI3MR_IT_RESET,
 190        MPI3MR_IT_RESUME,
 191};
 192
 193/* Cleanup reason definitions */
 194enum mpi3mr_cleanup_reason {
 195        MPI3MR_COMPLETE_CLEANUP = 0,
 196        MPI3MR_REINIT_FAILURE,
 197        MPI3MR_SUSPEND,
 198};
 199
 200/* Reset reason code definitions*/
 201enum mpi3mr_reset_reason {
 202        MPI3MR_RESET_FROM_BRINGUP = 1,
 203        MPI3MR_RESET_FROM_FAULT_WATCH = 2,
 204        MPI3MR_RESET_FROM_IOCTL = 3,
 205        MPI3MR_RESET_FROM_EH_HOS = 4,
 206        MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
 207        MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6,
 208        MPI3MR_RESET_FROM_MUR_FAILURE = 7,
 209        MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
 210        MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
 211        MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
 212        MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
 213        MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
 214        MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
 215        MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
 216        MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
 217        MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
 218        MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
 219        MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
 220        MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
 221        MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
 222        MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
 223        MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
 224        MPI3MR_RESET_FROM_SYSFS = 23,
 225        MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24
 226};
 227
 228/**
 229 * struct mpi3mr_compimg_ver - replica of component image
 230 * version defined in mpi30_image.h in host endianness
 231 *
 232 */
 233struct mpi3mr_compimg_ver {
 234        u16 build_num;
 235        u16 cust_id;
 236        u8 ph_minor;
 237        u8 ph_major;
 238        u8 gen_minor;
 239        u8 gen_major;
 240};
 241
 242/**
 243 * struct mpi3mr_ioc_facs - replica of component image version
 244 * defined in mpi30_ioc.h in host endianness
 245 *
 246 */
 247struct mpi3mr_ioc_facts {
 248        u32 ioc_capabilities;
 249        struct mpi3mr_compimg_ver fw_ver;
 250        u32 mpi_version;
 251        u16 max_reqs;
 252        u16 product_id;
 253        u16 op_req_sz;
 254        u16 reply_sz;
 255        u16 exceptions;
 256        u16 max_perids;
 257        u16 max_pds;
 258        u16 max_sasexpanders;
 259        u16 max_sasinitiators;
 260        u16 max_enclosures;
 261        u16 max_pcie_switches;
 262        u16 max_nvme;
 263        u16 max_vds;
 264        u16 max_hpds;
 265        u16 max_advhpds;
 266        u16 max_raidpds;
 267        u16 min_devhandle;
 268        u16 max_devhandle;
 269        u16 max_op_req_q;
 270        u16 max_op_reply_q;
 271        u16 shutdown_timeout;
 272        u8 ioc_num;
 273        u8 who_init;
 274        u16 max_msix_vectors;
 275        u8 personality;
 276        u8 dma_mask;
 277        u8 protocol_flags;
 278        u8 sge_mod_mask;
 279        u8 sge_mod_value;
 280        u8 sge_mod_shift;
 281};
 282
 283/**
 284 * struct segments - memory descriptor structure to store
 285 * virtual and dma addresses for operational queue segments.
 286 *
 287 * @segment: virtual address
 288 * @segment_dma: dma address
 289 */
 290struct segments {
 291        void *segment;
 292        dma_addr_t segment_dma;
 293};
 294
 295/**
 296 * struct op_req_qinfo -  Operational Request Queue Information
 297 *
 298 * @ci: consumer index
 299 * @pi: producer index
 300 * @num_request: Maximum number of entries in the queue
 301 * @qid: Queue Id starting from 1
 302 * @reply_qid: Associated reply queue Id
 303 * @num_segments: Number of discontiguous memory segments
 304 * @segment_qd: Depth of each segments
 305 * @q_lock: Concurrent queue access lock
 306 * @q_segments: Segment descriptor pointer
 307 * @q_segment_list: Segment list base virtual address
 308 * @q_segment_list_dma: Segment list base DMA address
 309 */
 310struct op_req_qinfo {
 311        u16 ci;
 312        u16 pi;
 313        u16 num_requests;
 314        u16 qid;
 315        u16 reply_qid;
 316        u16 num_segments;
 317        u16 segment_qd;
 318        spinlock_t q_lock;
 319        struct segments *q_segments;
 320        void *q_segment_list;
 321        dma_addr_t q_segment_list_dma;
 322};
 323
 324/**
 325 * struct op_reply_qinfo -  Operational Reply Queue Information
 326 *
 327 * @ci: consumer index
 328 * @qid: Queue Id starting from 1
 329 * @num_replies: Maximum number of entries in the queue
 330 * @num_segments: Number of discontiguous memory segments
 331 * @segment_qd: Depth of each segments
 332 * @q_segments: Segment descriptor pointer
 333 * @q_segment_list: Segment list base virtual address
 334 * @q_segment_list_dma: Segment list base DMA address
 335 * @ephase: Expected phased identifier for the reply queue
 336 * @pend_ios: Number of IOs pending in HW for this queue
 337 * @enable_irq_poll: Flag to indicate polling is enabled
 338 * @in_use: Queue is handled by poll/ISR
 339 */
 340struct op_reply_qinfo {
 341        u16 ci;
 342        u16 qid;
 343        u16 num_replies;
 344        u16 num_segments;
 345        u16 segment_qd;
 346        struct segments *q_segments;
 347        void *q_segment_list;
 348        dma_addr_t q_segment_list_dma;
 349        u8 ephase;
 350        atomic_t pend_ios;
 351        bool enable_irq_poll;
 352        atomic_t in_use;
 353};
 354
 355/**
 356 * struct mpi3mr_intr_info -  Interrupt cookie information
 357 *
 358 * @mrioc: Adapter instance reference
 359 * @msix_index: MSIx index
 360 * @op_reply_q: Associated operational reply queue
 361 * @name: Dev name for the irq claiming device
 362 */
 363struct mpi3mr_intr_info {
 364        struct mpi3mr_ioc *mrioc;
 365        u16 msix_index;
 366        struct op_reply_qinfo *op_reply_q;
 367        char name[MPI3MR_NAME_LENGTH];
 368};
 369
 370/**
 371 * struct tgt_dev_sas_sata - SAS/SATA device specific
 372 * information cached from firmware given data
 373 *
 374 * @sas_address: World wide unique SAS address
 375 * @dev_info: Device information bits
 376 */
 377struct tgt_dev_sas_sata {
 378        u64 sas_address;
 379        u16 dev_info;
 380};
 381
 382/**
 383 * struct tgt_dev_pcie - PCIe device specific information cached
 384 * from firmware given data
 385 *
 386 * @mdts: Maximum data transfer size
 387 * @capb: Device capabilities
 388 * @pgsz: Device page size
 389 * @abort_to: Timeout for abort TM
 390 * @reset_to: Timeout for Target/LUN reset TM
 391 */
 392struct tgt_dev_pcie {
 393        u32 mdts;
 394        u16 capb;
 395        u8 pgsz;
 396        u8 abort_to;
 397        u8 reset_to;
 398};
 399
 400/**
 401 * struct tgt_dev_volume - virtual device specific information
 402 * cached from firmware given data
 403 *
 404 * @state: State of the VD
 405 */
 406struct tgt_dev_volume {
 407        u8 state;
 408};
 409
 410/**
 411 * union _form_spec_inf - union of device specific information
 412 */
 413union _form_spec_inf {
 414        struct tgt_dev_sas_sata sas_sata_inf;
 415        struct tgt_dev_pcie pcie_inf;
 416        struct tgt_dev_volume vol_inf;
 417};
 418
 419
 420
 421/**
 422 * struct mpi3mr_tgt_dev - target device data structure
 423 *
 424 * @list: List pointer
 425 * @starget: Scsi_target pointer
 426 * @dev_handle: FW device handle
 427 * @parent_handle: FW parent device handle
 428 * @slot: Slot number
 429 * @encl_handle: FW enclosure handle
 430 * @perst_id: FW assigned Persistent ID
 431 * @dev_type: SAS/SATA/PCIE device type
 432 * @is_hidden: Should be exposed to upper layers or not
 433 * @host_exposed: Already exposed to host or not
 434 * @q_depth: Device specific Queue Depth
 435 * @wwid: World wide ID
 436 * @dev_spec: Device type specific information
 437 * @ref_count: Reference count
 438 */
 439struct mpi3mr_tgt_dev {
 440        struct list_head list;
 441        struct scsi_target *starget;
 442        u16 dev_handle;
 443        u16 parent_handle;
 444        u16 slot;
 445        u16 encl_handle;
 446        u16 perst_id;
 447        u8 dev_type;
 448        u8 is_hidden;
 449        u8 host_exposed;
 450        u16 q_depth;
 451        u64 wwid;
 452        union _form_spec_inf dev_spec;
 453        struct kref ref_count;
 454};
 455
 456/**
 457 * mpi3mr_tgtdev_get - k reference incrementor
 458 * @s: Target device reference
 459 *
 460 * Increment target device reference count.
 461 */
 462static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
 463{
 464        kref_get(&s->ref_count);
 465}
 466
 467/**
 468 * mpi3mr_free_tgtdev - target device memory dealloctor
 469 * @r: k reference pointer of the target device
 470 *
 471 * Free target device memory when no reference.
 472 */
 473static inline void mpi3mr_free_tgtdev(struct kref *r)
 474{
 475        kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
 476}
 477
 478/**
 479 * mpi3mr_tgtdev_put - k reference decrementor
 480 * @s: Target device reference
 481 *
 482 * Decrement target device reference count.
 483 */
 484static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
 485{
 486        kref_put(&s->ref_count, mpi3mr_free_tgtdev);
 487}
 488
 489
 490/**
 491 * struct mpi3mr_stgt_priv_data - SCSI target private structure
 492 *
 493 * @starget: Scsi_target pointer
 494 * @dev_handle: FW device handle
 495 * @perst_id: FW assigned Persistent ID
 496 * @num_luns: Number of Logical Units
 497 * @block_io: I/O blocked to the device or not
 498 * @dev_removed: Device removed in the Firmware
 499 * @dev_removedelay: Device is waiting to be removed in FW
 500 * @dev_type: Device type
 501 * @tgt_dev: Internal target device pointer
 502 */
 503struct mpi3mr_stgt_priv_data {
 504        struct scsi_target *starget;
 505        u16 dev_handle;
 506        u16 perst_id;
 507        u32 num_luns;
 508        atomic_t block_io;
 509        u8 dev_removed;
 510        u8 dev_removedelay;
 511        u8 dev_type;
 512        struct mpi3mr_tgt_dev *tgt_dev;
 513};
 514
 515/**
 516 * struct mpi3mr_stgt_priv_data - SCSI device private structure
 517 *
 518 * @tgt_priv_data: Scsi_target private data pointer
 519 * @lun_id: LUN ID of the device
 520 * @ncq_prio_enable: NCQ priority enable for SATA device
 521 */
 522struct mpi3mr_sdev_priv_data {
 523        struct mpi3mr_stgt_priv_data *tgt_priv_data;
 524        u32 lun_id;
 525        u8 ncq_prio_enable;
 526};
 527
 528/**
 529 * struct mpi3mr_drv_cmd - Internal command tracker
 530 *
 531 * @mutex: Command mutex
 532 * @done: Completeor for wakeup
 533 * @reply: Firmware reply for internal commands
 534 * @sensebuf: Sensebuf for SCSI IO commands
 535 * @iou_rc: IO Unit control reason code
 536 * @state: Command State
 537 * @dev_handle: Firmware handle for device specific commands
 538 * @ioc_status: IOC status from the firmware
 539 * @ioc_loginfo:IOC log info from the firmware
 540 * @is_waiting: Is the command issued in block mode
 541 * @retry_count: Retry count for retriable commands
 542 * @host_tag: Host tag used by the command
 543 * @callback: Callback for non blocking commands
 544 */
 545struct mpi3mr_drv_cmd {
 546        struct mutex mutex;
 547        struct completion done;
 548        void *reply;
 549        u8 *sensebuf;
 550        u8 iou_rc;
 551        u16 state;
 552        u16 dev_handle;
 553        u16 ioc_status;
 554        u32 ioc_loginfo;
 555        u8 is_waiting;
 556        u8 retry_count;
 557        u16 host_tag;
 558
 559        void (*callback)(struct mpi3mr_ioc *mrioc,
 560            struct mpi3mr_drv_cmd *drv_cmd);
 561};
 562
 563
 564/**
 565 * struct chain_element - memory descriptor structure to store
 566 * virtual and dma addresses for chain elements.
 567 *
 568 * @addr: virtual address
 569 * @dma_addr: dma address
 570 */
 571struct chain_element {
 572        void *addr;
 573        dma_addr_t dma_addr;
 574};
 575
 576/**
 577 * struct scmd_priv - SCSI command private data
 578 *
 579 * @host_tag: Host tag specific to operational queue
 580 * @in_lld_scope: Command in LLD scope or not
 581 * @meta_sg_valid: DIX command with meta data SGL or not
 582 * @scmd: SCSI Command pointer
 583 * @req_q_idx: Operational request queue index
 584 * @chain_idx: Chain frame index
 585 * @meta_chain_idx: Chain frame index of meta data SGL
 586 * @mpi3mr_scsiio_req: MPI SCSI IO request
 587 */
 588struct scmd_priv {
 589        u16 host_tag;
 590        u8 in_lld_scope;
 591        u8 meta_sg_valid;
 592        struct scsi_cmnd *scmd;
 593        u16 req_q_idx;
 594        int chain_idx;
 595        int meta_chain_idx;
 596        u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
 597};
 598
 599/**
 600 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
 601 * private data
 602 *
 603 * @list: List pointer
 604 * @pdev: PCI device pointer
 605 * @shost: Scsi_Host pointer
 606 * @id: Controller ID
 607 * @cpu_count: Number of online CPUs
 608 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
 609 * @name: Controller ASCII name
 610 * @driver_name: Driver ASCII name
 611 * @sysif_regs: System interface registers virtual address
 612 * @sysif_regs_phys: System interface registers physical address
 613 * @bars: PCI BARS
 614 * @dma_mask: DMA mask
 615 * @msix_count: Number of MSIX vectors used
 616 * @intr_enabled: Is interrupts enabled
 617 * @num_admin_req: Number of admin requests
 618 * @admin_req_q_sz: Admin request queue size
 619 * @admin_req_pi: Admin request queue producer index
 620 * @admin_req_ci: Admin request queue consumer index
 621 * @admin_req_base: Admin request queue base virtual address
 622 * @admin_req_dma: Admin request queue base dma address
 623 * @admin_req_lock: Admin queue access lock
 624 * @num_admin_replies: Number of admin replies
 625 * @admin_reply_q_sz: Admin reply queue size
 626 * @admin_reply_ci: Admin reply queue consumer index
 627 * @admin_reply_ephase:Admin reply queue expected phase
 628 * @admin_reply_base: Admin reply queue base virtual address
 629 * @admin_reply_dma: Admin reply queue base dma address
 630 * @ready_timeout: Controller ready timeout
 631 * @intr_info: Interrupt cookie pointer
 632 * @intr_info_count: Number of interrupt cookies
 633 * @num_queues: Number of operational queues
 634 * @num_op_req_q: Number of operational request queues
 635 * @req_qinfo: Operational request queue info pointer
 636 * @num_op_reply_q: Number of operational reply queues
 637 * @op_reply_qinfo: Operational reply queue info pointer
 638 * @init_cmds: Command tracker for initialization commands
 639 * @facts: Cached IOC facts data
 640 * @op_reply_desc_sz: Operational reply descriptor size
 641 * @num_reply_bufs: Number of reply buffers allocated
 642 * @reply_buf_pool: Reply buffer pool
 643 * @reply_buf: Reply buffer base virtual address
 644 * @reply_buf_dma: Reply buffer DMA address
 645 * @reply_buf_dma_max_address: Reply DMA address max limit
 646 * @reply_free_qsz: Reply free queue size
 647 * @reply_free_q_pool: Reply free queue pool
 648 * @reply_free_q: Reply free queue base virtual address
 649 * @reply_free_q_dma: Reply free queue base DMA address
 650 * @reply_free_queue_lock: Reply free queue lock
 651 * @reply_free_queue_host_index: Reply free queue host index
 652 * @num_sense_bufs: Number of sense buffers
 653 * @sense_buf_pool: Sense buffer pool
 654 * @sense_buf: Sense buffer base virtual address
 655 * @sense_buf_dma: Sense buffer base DMA address
 656 * @sense_buf_q_sz: Sense buffer queue size
 657 * @sense_buf_q_pool: Sense buffer queue pool
 658 * @sense_buf_q: Sense buffer queue virtual address
 659 * @sense_buf_q_dma: Sense buffer queue DMA address
 660 * @sbq_lock: Sense buffer queue lock
 661 * @sbq_host_index: Sense buffer queuehost index
 662 * @event_masks: Event mask bitmap
 663 * @fwevt_worker_name: Firmware event worker thread name
 664 * @fwevt_worker_thread: Firmware event worker thread
 665 * @fwevt_lock: Firmware event lock
 666 * @fwevt_list: Firmware event list
 667 * @watchdog_work_q_name: Fault watchdog worker thread name
 668 * @watchdog_work_q: Fault watchdog worker thread
 669 * @watchdog_work: Fault watchdog work
 670 * @watchdog_lock: Fault watchdog lock
 671 * @is_driver_loading: Is driver still loading
 672 * @scan_started: Async scan started
 673 * @scan_failed: Asycn scan failed
 674 * @stop_drv_processing: Stop all command processing
 675 * @max_host_ios: Maximum host I/O count
 676 * @chain_buf_count: Chain buffer count
 677 * @chain_buf_pool: Chain buffer pool
 678 * @chain_sgl_list: Chain SGL list
 679 * @chain_bitmap_sz: Chain buffer allocator bitmap size
 680 * @chain_bitmap: Chain buffer allocator bitmap
 681 * @chain_buf_lock: Chain buffer list lock
 682 * @host_tm_cmds: Command tracker for task management commands
 683 * @dev_rmhs_cmds: Command tracker for device removal commands
 684 * @devrem_bitmap_sz: Device removal bitmap size
 685 * @devrem_bitmap: Device removal bitmap
 686 * @dev_handle_bitmap_sz: Device handle bitmap size
 687 * @removepend_bitmap: Remove pending bitmap
 688 * @delayed_rmhs_list: Delayed device removal list
 689 * @ts_update_counter: Timestamp update counter
 690 * @fault_dbg: Fault debug flag
 691 * @reset_in_progress: Reset in progress flag
 692 * @unrecoverable: Controller unrecoverable flag
 693 * @reset_mutex: Controller reset mutex
 694 * @reset_waitq: Controller reset  wait queue
 695 * @diagsave_timeout: Diagnostic information save timeout
 696 * @logging_level: Controller debug logging level
 697 * @flush_io_count: I/O count to flush after reset
 698 * @current_event: Firmware event currently in process
 699 * @driver_info: Driver, Kernel, OS information to firmware
 700 * @change_count: Topology change count
 701 * @op_reply_q_offset: Operational reply queue offset with MSIx
 702 */
 703struct mpi3mr_ioc {
 704        struct list_head list;
 705        struct pci_dev *pdev;
 706        struct Scsi_Host *shost;
 707        u8 id;
 708        int cpu_count;
 709        bool enable_segqueue;
 710        u32 irqpoll_sleep;
 711
 712        char name[MPI3MR_NAME_LENGTH];
 713        char driver_name[MPI3MR_NAME_LENGTH];
 714
 715        volatile struct mpi3_sysif_registers __iomem *sysif_regs;
 716        resource_size_t sysif_regs_phys;
 717        int bars;
 718        u64 dma_mask;
 719
 720        u16 msix_count;
 721        u8 intr_enabled;
 722
 723        u16 num_admin_req;
 724        u32 admin_req_q_sz;
 725        u16 admin_req_pi;
 726        u16 admin_req_ci;
 727        void *admin_req_base;
 728        dma_addr_t admin_req_dma;
 729        spinlock_t admin_req_lock;
 730
 731        u16 num_admin_replies;
 732        u32 admin_reply_q_sz;
 733        u16 admin_reply_ci;
 734        u8 admin_reply_ephase;
 735        void *admin_reply_base;
 736        dma_addr_t admin_reply_dma;
 737
 738        u32 ready_timeout;
 739
 740        struct mpi3mr_intr_info *intr_info;
 741        u16 intr_info_count;
 742
 743        u16 num_queues;
 744        u16 num_op_req_q;
 745        struct op_req_qinfo *req_qinfo;
 746
 747        u16 num_op_reply_q;
 748        struct op_reply_qinfo *op_reply_qinfo;
 749
 750        struct mpi3mr_drv_cmd init_cmds;
 751        struct mpi3mr_ioc_facts facts;
 752        u16 op_reply_desc_sz;
 753
 754        u32 num_reply_bufs;
 755        struct dma_pool *reply_buf_pool;
 756        u8 *reply_buf;
 757        dma_addr_t reply_buf_dma;
 758        dma_addr_t reply_buf_dma_max_address;
 759
 760        u16 reply_free_qsz;
 761        struct dma_pool *reply_free_q_pool;
 762        __le64 *reply_free_q;
 763        dma_addr_t reply_free_q_dma;
 764        spinlock_t reply_free_queue_lock;
 765        u32 reply_free_queue_host_index;
 766
 767        u32 num_sense_bufs;
 768        struct dma_pool *sense_buf_pool;
 769        u8 *sense_buf;
 770        dma_addr_t sense_buf_dma;
 771
 772        u16 sense_buf_q_sz;
 773        struct dma_pool *sense_buf_q_pool;
 774        __le64 *sense_buf_q;
 775        dma_addr_t sense_buf_q_dma;
 776        spinlock_t sbq_lock;
 777        u32 sbq_host_index;
 778        u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
 779
 780        char fwevt_worker_name[MPI3MR_NAME_LENGTH];
 781        struct workqueue_struct *fwevt_worker_thread;
 782        spinlock_t fwevt_lock;
 783        struct list_head fwevt_list;
 784
 785        char watchdog_work_q_name[20];
 786        struct workqueue_struct *watchdog_work_q;
 787        struct delayed_work watchdog_work;
 788        spinlock_t watchdog_lock;
 789
 790        u8 is_driver_loading;
 791        u8 scan_started;
 792        u16 scan_failed;
 793        u8 stop_drv_processing;
 794
 795        u16 max_host_ios;
 796        spinlock_t tgtdev_lock;
 797        struct list_head tgtdev_list;
 798
 799        u32 chain_buf_count;
 800        struct dma_pool *chain_buf_pool;
 801        struct chain_element *chain_sgl_list;
 802        u16  chain_bitmap_sz;
 803        void *chain_bitmap;
 804        spinlock_t chain_buf_lock;
 805
 806        struct mpi3mr_drv_cmd host_tm_cmds;
 807        struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
 808        u16 devrem_bitmap_sz;
 809        void *devrem_bitmap;
 810        u16 dev_handle_bitmap_sz;
 811        void *removepend_bitmap;
 812        struct list_head delayed_rmhs_list;
 813
 814        u32 ts_update_counter;
 815        u8 fault_dbg;
 816        u8 reset_in_progress;
 817        u8 unrecoverable;
 818        struct mutex reset_mutex;
 819        wait_queue_head_t reset_waitq;
 820
 821        u16 diagsave_timeout;
 822        int logging_level;
 823        u16 flush_io_count;
 824
 825        struct mpi3mr_fwevt *current_event;
 826        struct mpi3_driver_info_layout driver_info;
 827        u16 change_count;
 828        u16 op_reply_q_offset;
 829};
 830
 831/**
 832 * struct mpi3mr_fwevt - Firmware event structure.
 833 *
 834 * @list: list head
 835 * @work: Work structure
 836 * @mrioc: Adapter instance reference
 837 * @event_id: MPI3 firmware event ID
 838 * @send_ack: Event acknowledgment required or not
 839 * @process_evt: Bottomhalf processing required or not
 840 * @evt_ctx: Event context to send in Ack
 841 * @ref_count: kref count
 842 * @event_data: Actual MPI3 event data
 843 */
 844struct mpi3mr_fwevt {
 845        struct list_head list;
 846        struct work_struct work;
 847        struct mpi3mr_ioc *mrioc;
 848        u16 event_id;
 849        bool send_ack;
 850        bool process_evt;
 851        u32 evt_ctx;
 852        struct kref ref_count;
 853        char event_data[0] __aligned(4);
 854};
 855
 856
 857/**
 858 * struct delayed_dev_rmhs_node - Delayed device removal node
 859 *
 860 * @list: list head
 861 * @handle: Device handle
 862 * @iou_rc: IO Unit Control Reason Code
 863 */
 864struct delayed_dev_rmhs_node {
 865        struct list_head list;
 866        u16 handle;
 867        u8 iou_rc;
 868};
 869
 870int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
 871void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
 872int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 init_type);
 873void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 reason);
 874int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
 875int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
 876u16 admin_req_sz, u8 ignore_reset);
 877int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
 878                           struct op_req_qinfo *opreqq, u8 *req);
 879void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
 880                          dma_addr_t dma_addr);
 881void mpi3mr_build_zero_len_sge(void *paddr);
 882void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
 883                                     dma_addr_t phys_addr);
 884void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
 885                                     dma_addr_t phys_addr);
 886void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
 887                                     u64 sense_buf_dma);
 888
 889void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
 890void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
 891                             struct mpi3_event_notification_reply *event_reply);
 892void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
 893                                  struct mpi3_default_reply_descriptor *reply_desc,
 894                                  u64 *reply_dma, u16 qidx);
 895void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
 896void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
 897
 898int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
 899                              u32 reset_reason, u8 snapdump);
 900int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc,
 901                                   u32 reset_reason);
 902void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
 903void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
 904
 905enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
 906int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
 907                          u32 event_ctx);
 908
 909void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
 910void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
 911void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
 912void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
 913void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
 914void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc);
 915
 916#endif /*MPI3MR_H_INCLUDED*/
 917