1=================== 2Linux IOMMU Support 3=================== 4 5The architecture spec can be obtained from the below location. 6 7http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf 8 9This guide gives a quick cheat sheet for some basic understanding. 10 11Some Keywords 12 13- DMAR - DMA remapping 14- DRHD - DMA Remapping Hardware Unit Definition 15- RMRR - Reserved memory Region Reporting Structure 16- ZLR - Zero length reads from PCI devices 17- IOVA - IO Virtual address. 18 19Basic stuff 20----------- 21 22ACPI enumerates and lists the different DMA engines in the platform, and 23device scope relationships between PCI devices and which DMA engine controls 24them. 25 26What is RMRR? 27------------- 28 29There are some devices the BIOS controls, for e.g USB devices to perform 30PS2 emulation. The regions of memory used for these devices are marked 31reserved in the e820 map. When we turn on DMA translation, DMA to those 32regions will fail. Hence BIOS uses RMRR to specify these regions along with 33devices that need to access these regions. OS is expected to setup 34unity mappings for these regions for these devices to access these regions. 35 36How is IOVA generated? 37---------------------- 38 39Well behaved drivers call pci_map_*() calls before sending command to device 40that needs to perform DMA. Once DMA is completed and mapping is no longer 41required, device performs a pci_unmap_*() calls to unmap the region. 42 43The Intel IOMMU driver allocates a virtual address per domain. Each PCIE 44device has its own domain (hence protection). Devices under p2p bridges 45share the virtual address with all devices under the p2p bridge due to 46transaction id aliasing for p2p bridges. 47 48IOVA generation is pretty generic. We used the same technique as vmalloc() 49but these are not global address spaces, but separate for each domain. 50Different DMA engines may support different number of domains. 51 52We also allocate guard pages with each mapping, so we can attempt to catch 53any overflow that might happen. 54 55 56Graphics Problems? 57------------------ 58If you encounter issues with graphics devices, you can try adding 59option intel_iommu=igfx_off to turn off the integrated graphics engine. 60If this fixes anything, please ensure you file a bug reporting the problem. 61 62Some exceptions to IOVA 63----------------------- 64Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff). 65The same is true for peer to peer transactions. Hence we reserve the 66address from PCI MMIO ranges so they are not allocated for IOVA addresses. 67 68 69Fault reporting 70--------------- 71When errors are reported, the DMA engine signals via an interrupt. The fault 72reason and device that caused it with fault reason is printed on console. 73 74See below for sample. 75 76 77Boot Message Sample 78------------------- 79 80Something like this gets printed indicating presence of DMAR tables 81in ACPI. 82 83ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0 84 85When DMAR is being processed and initialized by ACPI, prints DMAR locations 86and any RMRR's processed:: 87 88 ACPI DMAR:Host address width 36 89 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000 90 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000 91 ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000 92 ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff 93 ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff 94 95When DMAR is enabled for use, you will notice.. 96 97PCI-DMA: Using DMAR IOMMU 98------------------------- 99 100Fault reporting 101^^^^^^^^^^^^^^^ 102 103:: 104 105 DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000 106 DMAR:[fault reason 05] PTE Write access is not set 107 DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000 108 DMAR:[fault reason 05] PTE Write access is not set 109 110TBD 111---- 112 113- For compatibility testing, could use unity map domain for all devices, just 114 provide a 1-1 for all useful memory under a single domain for all devices. 115- API for paravirt ops for abstracting functionality for VMM folks. 116