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11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15#include <linux/gpio.h>
16#include <linux/gpio/machine.h>
17#include <linux/i2c.h>
18#include <linux/platform_data/pcf857x.h>
19#include <linux/platform_data/gpio-davinci.h>
20#include <linux/property.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/rawnand.h>
23#include <linux/mtd/partitions.h>
24#include <linux/mtd/physmap.h>
25#include <linux/nvmem-provider.h>
26#include <linux/phy.h>
27#include <linux/clk.h>
28#include <linux/videodev2.h>
29#include <linux/v4l2-dv-timings.h>
30#include <linux/export.h>
31#include <linux/leds.h>
32#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h>
34
35#include <media/i2c/tvp514x.h>
36
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39
40#include <mach/common.h>
41#include <mach/mux.h>
42#include <mach/serial.h>
43
44#include <linux/platform_data/i2c-davinci.h>
45#include <linux/platform_data/mtd-davinci.h>
46#include <linux/platform_data/mmc-davinci.h>
47#include <linux/platform_data/usb-davinci.h>
48#include <linux/platform_data/mtd-davinci-aemif.h>
49#include <linux/platform_data/ti-aemif.h>
50
51#include "davinci.h"
52#include "irqs.h"
53
54#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
55#define LXT971_PHY_ID (0x001378e2)
56#define LXT971_PHY_MASK (0xfffffff0)
57
58static struct mtd_partition davinci_evm_norflash_partitions[] = {
59
60 {
61 .name = "bootloader",
62 .offset = 0,
63 .size = 5 * SZ_64K,
64 .mask_flags = MTD_WRITEABLE,
65 },
66
67 {
68 .name = "params",
69 .offset = MTDPART_OFS_APPEND,
70 .size = SZ_64K,
71 .mask_flags = 0,
72 },
73
74 {
75 .name = "kernel",
76 .offset = MTDPART_OFS_APPEND,
77 .size = SZ_2M,
78 .mask_flags = 0
79 },
80
81 {
82 .name = "filesystem",
83 .offset = MTDPART_OFS_APPEND,
84 .size = MTDPART_SIZ_FULL,
85 .mask_flags = 0
86 }
87};
88
89static struct physmap_flash_data davinci_evm_norflash_data = {
90 .width = 2,
91 .parts = davinci_evm_norflash_partitions,
92 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
93};
94
95
96
97static struct resource davinci_evm_norflash_resource = {
98 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
99 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
100 .flags = IORESOURCE_MEM,
101};
102
103static struct platform_device davinci_evm_norflash_device = {
104 .name = "physmap-flash",
105 .id = 0,
106 .dev = {
107 .platform_data = &davinci_evm_norflash_data,
108 },
109 .num_resources = 1,
110 .resource = &davinci_evm_norflash_resource,
111};
112
113
114
115
116
117static struct mtd_partition davinci_evm_nandflash_partition[] = {
118
119
120
121
122
123
124
125 {
126 .name = "bootloader",
127 .offset = 0,
128 .size = SZ_256K + SZ_128K,
129 .mask_flags = MTD_WRITEABLE,
130 },
131
132 {
133 .name = "kernel",
134 .offset = MTDPART_OFS_APPEND,
135 .size = SZ_4M,
136 .mask_flags = 0,
137 },
138
139 {
140 .name = "filesystem",
141 .offset = MTDPART_OFS_APPEND,
142 .size = MTDPART_SIZ_FULL,
143 .mask_flags = 0,
144 }
145
146
147
148
149};
150
151static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
152 .wsetup = 20,
153 .wstrobe = 40,
154 .whold = 20,
155 .rsetup = 10,
156 .rstrobe = 40,
157 .rhold = 10,
158 .ta = 40,
159};
160
161static struct davinci_nand_pdata davinci_evm_nandflash_data = {
162 .core_chipsel = 0,
163 .parts = davinci_evm_nandflash_partition,
164 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
165 .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
166 .ecc_bits = 1,
167 .bbt_options = NAND_BBT_USE_FLASH,
168 .timing = &davinci_evm_nandflash_timing,
169};
170
171static struct resource davinci_evm_nandflash_resource[] = {
172 {
173 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
174 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
175 .flags = IORESOURCE_MEM,
176 }, {
177 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
178 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
179 .flags = IORESOURCE_MEM,
180 },
181};
182
183static struct resource davinci_evm_aemif_resource[] = {
184 {
185 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
186 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
187 .flags = IORESOURCE_MEM,
188 },
189};
190
191static struct aemif_abus_data davinci_evm_aemif_abus_data[] = {
192 {
193 .cs = 1,
194 },
195};
196
197static struct platform_device davinci_evm_nandflash_devices[] = {
198 {
199 .name = "davinci_nand",
200 .id = 0,
201 .dev = {
202 .platform_data = &davinci_evm_nandflash_data,
203 },
204 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
205 .resource = davinci_evm_nandflash_resource,
206 },
207};
208
209static struct aemif_platform_data davinci_evm_aemif_pdata = {
210 .abus_data = davinci_evm_aemif_abus_data,
211 .num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data),
212 .sub_devices = davinci_evm_nandflash_devices,
213 .num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices),
214};
215
216static struct platform_device davinci_evm_aemif_device = {
217 .name = "ti-aemif",
218 .id = -1,
219 .dev = {
220 .platform_data = &davinci_evm_aemif_pdata,
221 },
222 .resource = davinci_evm_aemif_resource,
223 .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource),
224};
225
226static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
227
228static struct platform_device davinci_fb_device = {
229 .name = "davincifb",
230 .id = -1,
231 .dev = {
232 .dma_mask = &davinci_fb_dma_mask,
233 .coherent_dma_mask = DMA_BIT_MASK(32),
234 },
235 .num_resources = 0,
236};
237
238static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
239 .clk_polarity = 0,
240 .hs_polarity = 1,
241 .vs_polarity = 1
242};
243
244#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
245
246static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
247 {
248 .index = 0,
249 .name = "Composite",
250 .type = V4L2_INPUT_TYPE_CAMERA,
251 .std = TVP514X_STD_ALL,
252 },
253 {
254 .index = 1,
255 .name = "S-Video",
256 .type = V4L2_INPUT_TYPE_CAMERA,
257 .std = TVP514X_STD_ALL,
258 },
259};
260
261
262
263
264
265
266static struct vpfe_route dm644xevm_tvp5146_routes[] = {
267 {
268 .input = INPUT_CVBS_VI2B,
269 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
270 },
271 {
272 .input = INPUT_SVIDEO_VI2C_VI1C,
273 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
274 },
275};
276
277static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
278 {
279 .name = "tvp5146",
280 .grp_id = 0,
281 .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
282 .inputs = dm644xevm_tvp5146_inputs,
283 .routes = dm644xevm_tvp5146_routes,
284 .can_route = 1,
285 .ccdc_if_params = {
286 .if_type = VPFE_BT656,
287 .hdpol = VPFE_PINPOL_POSITIVE,
288 .vdpol = VPFE_PINPOL_POSITIVE,
289 },
290 .board_info = {
291 I2C_BOARD_INFO("tvp5146", 0x5d),
292 .platform_data = &dm644xevm_tvp5146_pdata,
293 },
294 },
295};
296
297static struct vpfe_config dm644xevm_capture_cfg = {
298 .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
299 .i2c_adapter_id = 1,
300 .sub_devs = dm644xevm_vpfe_sub_devs,
301 .card_name = "DM6446 EVM",
302 .ccdc = "DM6446 CCDC",
303};
304
305static struct platform_device rtc_dev = {
306 .name = "rtc_davinci_evm",
307 .id = -1,
308};
309
310
311#ifdef CONFIG_I2C
312
313
314
315
316#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
317
318
319
320
321static struct gpio_led evm_leds[] = {
322 { .name = "DS8", .active_low = 1,
323 .default_trigger = "heartbeat", },
324 { .name = "DS7", .active_low = 1, },
325 { .name = "DS6", .active_low = 1, },
326 { .name = "DS5", .active_low = 1, },
327 { .name = "DS4", .active_low = 1, },
328 { .name = "DS3", .active_low = 1, },
329 { .name = "DS2", .active_low = 1,
330 .default_trigger = "mmc0", },
331 { .name = "DS1", .active_low = 1,
332 .default_trigger = "disk-activity", },
333};
334
335static const struct gpio_led_platform_data evm_led_data = {
336 .num_leds = ARRAY_SIZE(evm_leds),
337 .leds = evm_leds,
338};
339
340static struct platform_device *evm_led_dev;
341
342static int
343evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
344{
345 struct gpio_led *leds = evm_leds;
346 int status;
347
348 while (ngpio--) {
349 leds->gpio = gpio++;
350 leds++;
351 }
352
353
354
355
356 evm_led_dev = platform_device_alloc("leds-gpio", 0);
357 platform_device_add_data(evm_led_dev,
358 &evm_led_data, sizeof evm_led_data);
359
360 evm_led_dev->dev.parent = &client->dev;
361 status = platform_device_add(evm_led_dev);
362 if (status < 0) {
363 platform_device_put(evm_led_dev);
364 evm_led_dev = NULL;
365 }
366 return status;
367}
368
369static int
370evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
371{
372 if (evm_led_dev) {
373 platform_device_unregister(evm_led_dev);
374 evm_led_dev = NULL;
375 }
376 return 0;
377}
378
379static struct pcf857x_platform_data pcf_data_u2 = {
380 .gpio_base = PCF_Uxx_BASE(0),
381 .setup = evm_led_setup,
382 .teardown = evm_led_teardown,
383};
384
385
386
387
388static int sw_gpio;
389
390static ssize_t
391sw_show(struct device *d, struct device_attribute *a, char *buf)
392{
393 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
394
395 strcpy(buf, s);
396 return strlen(s);
397}
398
399static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
400
401static int
402evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
403{
404 int status;
405
406
407 sw_gpio = gpio + 7;
408 status = gpio_request(sw_gpio, "user_sw");
409 if (status == 0)
410 status = gpio_direction_input(sw_gpio);
411 if (status == 0)
412 status = device_create_file(&client->dev, &dev_attr_user_sw);
413 else
414 gpio_free(sw_gpio);
415 if (status != 0)
416 sw_gpio = -EINVAL;
417
418
419 gpio_request(gpio + 3, "pll_fs2");
420 gpio_direction_output(gpio + 3, 0);
421
422 gpio_request(gpio + 2, "pll_fs1");
423 gpio_direction_output(gpio + 2, 0);
424
425 gpio_request(gpio + 1, "pll_sr");
426 gpio_direction_output(gpio + 1, 0);
427
428 return 0;
429}
430
431static int
432evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
433{
434 gpio_free(gpio + 1);
435 gpio_free(gpio + 2);
436 gpio_free(gpio + 3);
437
438 if (sw_gpio > 0) {
439 device_remove_file(&client->dev, &dev_attr_user_sw);
440 gpio_free(sw_gpio);
441 }
442 return 0;
443}
444
445static struct pcf857x_platform_data pcf_data_u18 = {
446 .gpio_base = PCF_Uxx_BASE(1),
447 .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
448 .setup = evm_u18_setup,
449 .teardown = evm_u18_teardown,
450};
451
452
453
454
455static int
456evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
457{
458
459 gpio_request(gpio + 0, "nDRV_VBUS");
460 gpio_direction_output(gpio + 0, 1);
461
462
463 gpio_request(gpio + 1, "VDDIMX_EN");
464 gpio_direction_output(gpio + 1, 1);
465
466
467 gpio_request(gpio + 2, "VLYNQ_EN");
468 gpio_direction_output(gpio + 2, 1);
469
470
471 gpio_request(gpio + 3, "nCF_RESET");
472 gpio_direction_output(gpio + 3, 0);
473
474
475
476
477 gpio_request(gpio + 5, "WLAN_RESET");
478 gpio_direction_output(gpio + 5, 1);
479
480
481 gpio_request(gpio + 6, "nATA_SEL");
482 gpio_direction_output(gpio + 6, 0);
483
484
485 gpio_request(gpio + 7, "nCF_SEL");
486 gpio_direction_output(gpio + 7, 1);
487
488 return 0;
489}
490
491static int
492evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
493{
494 gpio_free(gpio + 7);
495 gpio_free(gpio + 6);
496 gpio_free(gpio + 5);
497 gpio_free(gpio + 3);
498 gpio_free(gpio + 2);
499 gpio_free(gpio + 1);
500 gpio_free(gpio + 0);
501 return 0;
502}
503
504static struct pcf857x_platform_data pcf_data_u35 = {
505 .gpio_base = PCF_Uxx_BASE(2),
506 .setup = evm_u35_setup,
507 .teardown = evm_u35_teardown,
508};
509
510
511
512
513
514
515
516
517
518static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
519 {
520 .name = "macaddr",
521 .offset = 0x7f00,
522 .bytes = ETH_ALEN,
523 }
524};
525
526static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
527 .nvmem_name = "1-00500",
528 .cells = dm644evm_nvmem_cells,
529 .ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
530};
531
532static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
533 .nvmem_name = "1-00500",
534 .cell_name = "macaddr",
535 .dev_id = "davinci_emac.1",
536 .con_id = "mac-address",
537};
538
539static const struct property_entry eeprom_properties[] = {
540 PROPERTY_ENTRY_U32("pagesize", 64),
541 { }
542};
543
544static const struct software_node eeprom_node = {
545 .properties = eeprom_properties,
546};
547
548
549
550
551
552
553static struct i2c_client *dm6446evm_msp;
554
555static int dm6446evm_msp_probe(struct i2c_client *client)
556{
557 dm6446evm_msp = client;
558 return 0;
559}
560
561static int dm6446evm_msp_remove(struct i2c_client *client)
562{
563 dm6446evm_msp = NULL;
564 return 0;
565}
566
567static const struct i2c_device_id dm6446evm_msp_ids[] = {
568 { "dm6446evm_msp", 0, },
569 { },
570};
571
572static struct i2c_driver dm6446evm_msp_driver = {
573 .driver.name = "dm6446evm_msp",
574 .id_table = dm6446evm_msp_ids,
575 .probe_new = dm6446evm_msp_probe,
576 .remove = dm6446evm_msp_remove,
577};
578
579static int dm6444evm_msp430_get_pins(void)
580{
581 static const char txbuf[2] = { 2, 4, };
582 char buf[4];
583 struct i2c_msg msg[2] = {
584 {
585 .flags = 0,
586 .len = 2,
587 .buf = (void __force *)txbuf,
588 },
589 {
590 .flags = I2C_M_RD,
591 .len = 4,
592 .buf = buf,
593 },
594 };
595 int status;
596
597 if (!dm6446evm_msp)
598 return -ENXIO;
599
600 msg[0].addr = dm6446evm_msp->addr;
601 msg[1].addr = dm6446evm_msp->addr;
602
603
604
605
606
607 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
608 if (status < 0)
609 return status;
610
611 dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
612
613 return (buf[3] << 8) | buf[2];
614}
615
616static int dm6444evm_mmc_get_cd(int module)
617{
618 int status = dm6444evm_msp430_get_pins();
619
620 return (status < 0) ? status : !(status & BIT(1));
621}
622
623static int dm6444evm_mmc_get_ro(int module)
624{
625 int status = dm6444evm_msp430_get_pins();
626
627 return (status < 0) ? status : status & BIT(6 + 8);
628}
629
630static struct davinci_mmc_config dm6446evm_mmc_config = {
631 .get_cd = dm6444evm_mmc_get_cd,
632 .get_ro = dm6444evm_mmc_get_ro,
633 .wires = 4,
634};
635
636static struct i2c_board_info __initdata i2c_info[] = {
637 {
638 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
639 },
640 {
641 I2C_BOARD_INFO("pcf8574", 0x38),
642 .platform_data = &pcf_data_u2,
643 },
644 {
645 I2C_BOARD_INFO("pcf8574", 0x39),
646 .platform_data = &pcf_data_u18,
647 },
648 {
649 I2C_BOARD_INFO("pcf8574", 0x3a),
650 .platform_data = &pcf_data_u35,
651 },
652 {
653 I2C_BOARD_INFO("24c256", 0x50),
654 .swnode = &eeprom_node,
655 },
656 {
657 I2C_BOARD_INFO("tlv320aic33", 0x1b),
658 },
659};
660
661#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
662#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
663
664static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
665 .dev_id = "i2c_davinci.1",
666 .table = {
667 GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
668 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
669 GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
670 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
671 { }
672 },
673};
674
675
676
677
678static struct davinci_i2c_platform_data i2c_pdata = {
679 .bus_freq = 20 ,
680 .bus_delay = 100 ,
681 .gpio_recovery = true,
682};
683
684static void __init evm_init_i2c(void)
685{
686 gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
687 davinci_init_i2c(&i2c_pdata);
688 i2c_add_driver(&dm6446evm_msp_driver);
689 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
690}
691#endif
692
693
694static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
695
696 REGULATOR_SUPPLY("AVDD", "1-001b"),
697 REGULATOR_SUPPLY("DRVDD", "1-001b"),
698};
699
700static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
701
702 REGULATOR_SUPPLY("IOVDD", "1-001b"),
703 REGULATOR_SUPPLY("DVDD", "1-001b"),
704};
705
706#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
707
708
709static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
710 {
711 .name = "ntsc",
712 .timings_type = VPBE_ENC_STD,
713 .std_id = V4L2_STD_NTSC,
714 .interlaced = 1,
715 .xres = 720,
716 .yres = 480,
717 .aspect = {11, 10},
718 .fps = {30000, 1001},
719 .left_margin = 0x79,
720 .upper_margin = 0x10,
721 },
722 {
723 .name = "pal",
724 .timings_type = VPBE_ENC_STD,
725 .std_id = V4L2_STD_PAL,
726 .interlaced = 1,
727 .xres = 720,
728 .yres = 576,
729 .aspect = {54, 59},
730 .fps = {25, 1},
731 .left_margin = 0x7e,
732 .upper_margin = 0x16,
733 },
734};
735
736
737static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
738 {
739 .name = "480p59_94",
740 .timings_type = VPBE_ENC_DV_TIMINGS,
741 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
742 .interlaced = 0,
743 .xres = 720,
744 .yres = 480,
745 .aspect = {1, 1},
746 .fps = {5994, 100},
747 .left_margin = 0x80,
748 .upper_margin = 0x20,
749 },
750 {
751 .name = "576p50",
752 .timings_type = VPBE_ENC_DV_TIMINGS,
753 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
754 .interlaced = 0,
755 .xres = 720,
756 .yres = 576,
757 .aspect = {1, 1},
758 .fps = {50, 1},
759 .left_margin = 0x7e,
760 .upper_margin = 0x30,
761 },
762};
763
764
765
766
767
768
769
770
771
772static struct vpbe_output dm644xevm_vpbe_outputs[] = {
773 {
774 .output = {
775 .index = 0,
776 .name = "Composite",
777 .type = V4L2_OUTPUT_TYPE_ANALOG,
778 .std = VENC_STD_ALL,
779 .capabilities = V4L2_OUT_CAP_STD,
780 },
781 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
782 .default_mode = "ntsc",
783 .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
784 .modes = dm644xevm_enc_std_timing,
785 },
786 {
787 .output = {
788 .index = 1,
789 .name = "Component",
790 .type = V4L2_OUTPUT_TYPE_ANALOG,
791 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
792 },
793 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
794 .default_mode = "480p59_94",
795 .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
796 .modes = dm644xevm_enc_preset_timing,
797 },
798};
799
800static struct vpbe_config dm644xevm_display_cfg = {
801 .module_name = "dm644x-vpbe-display",
802 .i2c_adapter_id = 1,
803 .osd = {
804 .module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
805 },
806 .venc = {
807 .module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
808 },
809 .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
810 .outputs = dm644xevm_vpbe_outputs,
811};
812
813static struct platform_device *davinci_evm_devices[] __initdata = {
814 &davinci_fb_device,
815 &rtc_dev,
816};
817
818static void __init
819davinci_evm_map_io(void)
820{
821 dm644x_init();
822}
823
824static int davinci_phy_fixup(struct phy_device *phydev)
825{
826 unsigned int control;
827
828
829
830
831
832 control = phy_read(phydev, 26);
833 phy_write(phydev, 26, (control | 0x800));
834 return 0;
835}
836
837#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
838 IS_ENABLED(CONFIG_PATA_BK3710))
839
840#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
841
842#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
843
844#define GPIO_nVBUS_DRV 160
845
846static struct gpiod_lookup_table dm644evm_usb_gpio_table = {
847 .dev_id = "musb-davinci",
848 .table = {
849 GPIO_LOOKUP("davinci_gpio", GPIO_nVBUS_DRV, NULL,
850 GPIO_ACTIVE_HIGH),
851 { }
852 },
853};
854
855static __init void davinci_evm_init(void)
856{
857 int ret;
858 struct clk *aemif_clk;
859 struct davinci_soc_info *soc_info = &davinci_soc_info;
860
861 dm644x_register_clocks();
862
863 regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
864 ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
865 regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
866 ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
867
868 dm644x_init_devices();
869
870 ret = dm644x_gpio_register();
871 if (ret)
872 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
873
874 aemif_clk = clk_get(NULL, "aemif");
875 clk_prepare_enable(aemif_clk);
876
877 if (HAS_ATA) {
878 if (HAS_NAND || HAS_NOR)
879 pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
880 "\tDisable IDE for NAND/NOR support\n");
881 davinci_init_ide();
882 } else if (HAS_NAND || HAS_NOR) {
883 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
884 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
885
886
887 if (HAS_NAND) {
888 platform_device_register(&davinci_evm_aemif_device);
889#ifdef CONFIG_I2C
890 evm_leds[7].default_trigger = "nand-disk";
891#endif
892 if (HAS_NOR)
893 pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
894 } else if (HAS_NOR)
895 platform_device_register(&davinci_evm_norflash_device);
896 }
897
898 platform_add_devices(davinci_evm_devices,
899 ARRAY_SIZE(davinci_evm_devices));
900#ifdef CONFIG_I2C
901 nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
902 nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
903 evm_init_i2c();
904 davinci_setup_mmc(0, &dm6446evm_mmc_config);
905#endif
906 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
907
908 davinci_serial_init(dm644x_serial_device);
909 dm644x_init_asp();
910
911
912 gpiod_add_lookup_table(&dm644evm_usb_gpio_table);
913 davinci_setup_usb(1000, 8);
914
915 if (IS_BUILTIN(CONFIG_PHYLIB)) {
916 soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
917
918 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
919 davinci_phy_fixup);
920 }
921}
922
923MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
924
925 .atag_offset = 0x100,
926 .map_io = davinci_evm_map_io,
927 .init_irq = dm644x_init_irq,
928 .init_time = dm644x_init_time,
929 .init_machine = davinci_evm_init,
930 .init_late = davinci_init_late,
931 .dma_zone_size = SZ_128M,
932MACHINE_END
933
