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15#include <linux/clk-provider.h>
16#include <linux/clk/davinci.h>
17#include <linux/clkdev.h>
18#include <linux/cpufreq.h>
19#include <linux/gpio.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/irqchip/irq-davinci-cp-intc.h>
23#include <linux/mfd/da8xx-cfgchip.h>
24#include <linux/platform_data/clk-da8xx-cfgchip.h>
25#include <linux/platform_data/clk-davinci-pll.h>
26#include <linux/platform_data/davinci-cpufreq.h>
27#include <linux/platform_data/gpio-davinci.h>
28#include <linux/platform_device.h>
29#include <linux/regmap.h>
30#include <linux/regulator/consumer.h>
31
32#include <asm/mach/map.h>
33
34#include <mach/common.h>
35#include <mach/cputype.h>
36#include <mach/da8xx.h>
37#include <mach/pm.h>
38
39#include <clocksource/timer-davinci.h>
40
41#include "irqs.h"
42#include "mux.h"
43
44#define DA850_PLL1_BASE 0x01e1a000
45#define DA850_TIMER64P2_BASE 0x01f0c000
46#define DA850_TIMER64P3_BASE 0x01f0d000
47
48#define DA850_REF_FREQ 24000000
49
50
51
52
53
54
55
56static const struct mux_config da850_pins[] = {
57#ifdef CONFIG_DAVINCI_MUX
58
59 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
60 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
61 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
62 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
63
64 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
65 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
66
67 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
68 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
69
70 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
71 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
72
73 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
74 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
75
76 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
77 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
78 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
79 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
80 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
81 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
82 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
83 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
84 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
85 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
86 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
87 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
88 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
89 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
90 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
91 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
92 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
93 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
94 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
95 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
96 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
97 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
98 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
99 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
100 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
101
102 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
103 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
104 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
105 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
106 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
107 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
108 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
109 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
110 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
111 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
112 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
113 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
114 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
115 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
116 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
117 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
118 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
119 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
120 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
121 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
122 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
123 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
124 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
125
126 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
127 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
128 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
129 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
130 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
131 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
132 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
133 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
134 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
135 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
136 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
137 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
138 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
139 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
140 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
141 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
142 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
143 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
144 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
145 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
146
147 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
148 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
149 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
150 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
151 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
152 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
153
154 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
155 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
156 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
157 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
158 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
159 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
160
161 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
162 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
163 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
164 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
165 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
166 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
167 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
168 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
169 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
170 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
171 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
172 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
173 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
174 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
175 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
176 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
177 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
178 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
179 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
180 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
181 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
182 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
183 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
184 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
185 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
186 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
187 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
188 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
189 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
190 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
191 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
192 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
193 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
194 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
195 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
196 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
197 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
198 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
199 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
200 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
201 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
202 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
203 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
204 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
205 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
206 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
207 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
208 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
209
210 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
211 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
212 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
213 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
214 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
215 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
216 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
217 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
218 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
219 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
220 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
221 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
222
223 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
224 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
225 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
226 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
227 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
228 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
229 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
230 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
231 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
232 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
233 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
234 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
235 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
236 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
237 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
238 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
239 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
240 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
241 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
242 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
243
244 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
245 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
246 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
247 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
248 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
249 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
250 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
251 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
252 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
253 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
254 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
255 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
256 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
257 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
258 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
259 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
260 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
261 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
262#endif
263};
264
265const short da850_i2c0_pins[] __initconst = {
266 DA850_I2C0_SDA, DA850_I2C0_SCL,
267 -1
268};
269
270const short da850_i2c1_pins[] __initconst = {
271 DA850_I2C1_SCL, DA850_I2C1_SDA,
272 -1
273};
274
275const short da850_lcdcntl_pins[] __initconst = {
276 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
277 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
278 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
279 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
280 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
281 -1
282};
283
284const short da850_vpif_capture_pins[] __initconst = {
285 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
286 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
287 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
288 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
289 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
290 DA850_VPIF_CLKIN3,
291 -1
292};
293
294const short da850_vpif_display_pins[] __initconst = {
295 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
296 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
297 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
298 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
299 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
300 DA850_VPIF_CLKO3,
301 -1
302};
303
304static struct map_desc da850_io_desc[] = {
305 {
306 .virtual = IO_VIRT,
307 .pfn = __phys_to_pfn(IO_PHYS),
308 .length = IO_SIZE,
309 .type = MT_DEVICE
310 },
311 {
312 .virtual = DA8XX_CP_INTC_VIRT,
313 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
314 .length = DA8XX_CP_INTC_SIZE,
315 .type = MT_DEVICE
316 },
317};
318
319
320static struct davinci_id da850_ids[] = {
321 {
322 .variant = 0x0,
323 .part_no = 0xb7d1,
324 .manufacturer = 0x017,
325 .cpu_id = DAVINCI_CPU_ID_DA850,
326 .name = "da850/omap-l138",
327 },
328 {
329 .variant = 0x1,
330 .part_no = 0xb7d1,
331 .manufacturer = 0x017,
332 .cpu_id = DAVINCI_CPU_ID_DA850,
333 .name = "da850/omap-l138/am18x",
334 },
335};
336
337
338
339
340
341static const struct davinci_timer_cfg da850_timer_cfg = {
342 .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
343 .irq = {
344 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
345 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
346 },
347};
348
349#ifdef CONFIG_CPU_FREQ
350
351
352
353
354
355
356
357struct da850_opp {
358 unsigned int freq;
359 unsigned int prediv;
360 unsigned int mult;
361 unsigned int postdiv;
362 unsigned int cvdd_min;
363 unsigned int cvdd_max;
364};
365
366static const struct da850_opp da850_opp_456 = {
367 .freq = 456000,
368 .prediv = 1,
369 .mult = 19,
370 .postdiv = 1,
371 .cvdd_min = 1300000,
372 .cvdd_max = 1350000,
373};
374
375static const struct da850_opp da850_opp_408 = {
376 .freq = 408000,
377 .prediv = 1,
378 .mult = 17,
379 .postdiv = 1,
380 .cvdd_min = 1300000,
381 .cvdd_max = 1350000,
382};
383
384static const struct da850_opp da850_opp_372 = {
385 .freq = 372000,
386 .prediv = 2,
387 .mult = 31,
388 .postdiv = 1,
389 .cvdd_min = 1200000,
390 .cvdd_max = 1320000,
391};
392
393static const struct da850_opp da850_opp_300 = {
394 .freq = 300000,
395 .prediv = 1,
396 .mult = 25,
397 .postdiv = 2,
398 .cvdd_min = 1200000,
399 .cvdd_max = 1320000,
400};
401
402static const struct da850_opp da850_opp_200 = {
403 .freq = 200000,
404 .prediv = 1,
405 .mult = 25,
406 .postdiv = 3,
407 .cvdd_min = 1100000,
408 .cvdd_max = 1160000,
409};
410
411static const struct da850_opp da850_opp_96 = {
412 .freq = 96000,
413 .prediv = 1,
414 .mult = 20,
415 .postdiv = 5,
416 .cvdd_min = 1000000,
417 .cvdd_max = 1050000,
418};
419
420#define OPP(freq) \
421 { \
422 .driver_data = (unsigned int) &da850_opp_##freq, \
423 .frequency = freq * 1000, \
424 }
425
426static struct cpufreq_frequency_table da850_freq_table[] = {
427 OPP(456),
428 OPP(408),
429 OPP(372),
430 OPP(300),
431 OPP(200),
432 OPP(96),
433 {
434 .driver_data = 0,
435 .frequency = CPUFREQ_TABLE_END,
436 },
437};
438
439#ifdef CONFIG_REGULATOR
440static int da850_set_voltage(unsigned int index);
441static int da850_regulator_init(void);
442#endif
443
444static struct davinci_cpufreq_config cpufreq_info = {
445 .freq_table = da850_freq_table,
446#ifdef CONFIG_REGULATOR
447 .init = da850_regulator_init,
448 .set_voltage = da850_set_voltage,
449#endif
450};
451
452#ifdef CONFIG_REGULATOR
453static struct regulator *cvdd;
454
455static int da850_set_voltage(unsigned int index)
456{
457 struct da850_opp *opp;
458
459 if (!cvdd)
460 return -ENODEV;
461
462 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
463
464 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
465}
466
467static int da850_regulator_init(void)
468{
469 cvdd = regulator_get(NULL, "cvdd");
470 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
471 " voltage scaling unsupported\n")) {
472 return PTR_ERR(cvdd);
473 }
474
475 return 0;
476}
477#endif
478
479static struct platform_device da850_cpufreq_device = {
480 .name = "cpufreq-davinci",
481 .dev = {
482 .platform_data = &cpufreq_info,
483 },
484 .id = -1,
485};
486
487unsigned int da850_max_speed = 300000;
488
489int da850_register_cpufreq(char *async_clk)
490{
491 int i;
492
493
494 if (async_clk)
495 clk_add_alias("async", da850_cpufreq_device.name,
496 async_clk, NULL);
497 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
498 if (da850_freq_table[i].frequency <= da850_max_speed) {
499 cpufreq_info.freq_table = &da850_freq_table[i];
500 break;
501 }
502 }
503
504 return platform_device_register(&da850_cpufreq_device);
505}
506#else
507int __init da850_register_cpufreq(char *async_clk)
508{
509 return 0;
510}
511#endif
512
513
514static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
515
516static struct resource da850_vpif_resource[] = {
517 {
518 .start = DA8XX_VPIF_BASE,
519 .end = DA8XX_VPIF_BASE + 0xfff,
520 .flags = IORESOURCE_MEM,
521 }
522};
523
524static struct platform_device da850_vpif_dev = {
525 .name = "vpif",
526 .id = -1,
527 .dev = {
528 .dma_mask = &da850_vpif_dma_mask,
529 .coherent_dma_mask = DMA_BIT_MASK(32),
530 },
531 .resource = da850_vpif_resource,
532 .num_resources = ARRAY_SIZE(da850_vpif_resource),
533};
534
535static struct resource da850_vpif_display_resource[] = {
536 {
537 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
538 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
539 .flags = IORESOURCE_IRQ,
540 },
541};
542
543static struct platform_device da850_vpif_display_dev = {
544 .name = "vpif_display",
545 .id = -1,
546 .dev = {
547 .dma_mask = &da850_vpif_dma_mask,
548 .coherent_dma_mask = DMA_BIT_MASK(32),
549 },
550 .resource = da850_vpif_display_resource,
551 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
552};
553
554static struct resource da850_vpif_capture_resource[] = {
555 {
556 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
557 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
558 .flags = IORESOURCE_IRQ,
559 },
560 {
561 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
562 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
563 .flags = IORESOURCE_IRQ,
564 },
565};
566
567static struct platform_device da850_vpif_capture_dev = {
568 .name = "vpif_capture",
569 .id = -1,
570 .dev = {
571 .dma_mask = &da850_vpif_dma_mask,
572 .coherent_dma_mask = DMA_BIT_MASK(32),
573 },
574 .resource = da850_vpif_capture_resource,
575 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
576};
577
578int __init da850_register_vpif(void)
579{
580 return platform_device_register(&da850_vpif_dev);
581}
582
583int __init da850_register_vpif_display(struct vpif_display_config
584 *display_config)
585{
586 da850_vpif_display_dev.dev.platform_data = display_config;
587 return platform_device_register(&da850_vpif_display_dev);
588}
589
590int __init da850_register_vpif_capture(struct vpif_capture_config
591 *capture_config)
592{
593 da850_vpif_capture_dev.dev.platform_data = capture_config;
594 return platform_device_register(&da850_vpif_capture_dev);
595}
596
597static struct davinci_gpio_platform_data da850_gpio_platform_data = {
598 .no_auto_base = true,
599 .base = 0,
600 .ngpio = 144,
601};
602
603int __init da850_register_gpio(void)
604{
605 return da8xx_register_gpio(&da850_gpio_platform_data);
606}
607
608static const struct davinci_soc_info davinci_soc_info_da850 = {
609 .io_desc = da850_io_desc,
610 .io_desc_num = ARRAY_SIZE(da850_io_desc),
611 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
612 .ids = da850_ids,
613 .ids_num = ARRAY_SIZE(da850_ids),
614 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
615 .pinmux_pins = da850_pins,
616 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
617 .emac_pdata = &da8xx_emac_pdata,
618 .sram_dma = DA8XX_SHARED_RAM_BASE,
619 .sram_len = SZ_128K,
620};
621
622void __init da850_init(void)
623{
624 davinci_common_init(&davinci_soc_info_da850);
625
626 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
627 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
628 return;
629
630 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
631 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
632}
633
634static const struct davinci_cp_intc_config da850_cp_intc_config = {
635 .reg = {
636 .start = DA8XX_CP_INTC_BASE,
637 .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
638 .flags = IORESOURCE_MEM,
639 },
640 .num_irqs = DA850_N_CP_INTC_IRQ,
641};
642
643void __init da850_init_irq(void)
644{
645 davinci_cp_intc_init(&da850_cp_intc_config);
646}
647
648void __init da850_init_time(void)
649{
650 void __iomem *pll0;
651 struct regmap *cfgchip;
652 struct clk *clk;
653 int rv;
654
655 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
656
657 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
658 cfgchip = da8xx_get_cfgchip();
659
660 da850_pll0_init(NULL, pll0, cfgchip);
661
662 clk = clk_get(NULL, "timer0");
663 if (WARN_ON(IS_ERR(clk))) {
664 pr_err("Unable to get the timer clock\n");
665 return;
666 }
667
668 rv = davinci_timer_register(clk, &da850_timer_cfg);
669 WARN(rv, "Unable to register the timer: %d\n", rv);
670}
671
672static struct resource da850_pll1_resources[] = {
673 {
674 .start = DA850_PLL1_BASE,
675 .end = DA850_PLL1_BASE + SZ_4K - 1,
676 .flags = IORESOURCE_MEM,
677 },
678};
679
680static struct davinci_pll_platform_data da850_pll1_pdata;
681
682static struct platform_device da850_pll1_device = {
683 .name = "da850-pll1",
684 .id = -1,
685 .resource = da850_pll1_resources,
686 .num_resources = ARRAY_SIZE(da850_pll1_resources),
687 .dev = {
688 .platform_data = &da850_pll1_pdata,
689 },
690};
691
692static struct resource da850_psc0_resources[] = {
693 {
694 .start = DA8XX_PSC0_BASE,
695 .end = DA8XX_PSC0_BASE + SZ_4K - 1,
696 .flags = IORESOURCE_MEM,
697 },
698};
699
700static struct platform_device da850_psc0_device = {
701 .name = "da850-psc0",
702 .id = -1,
703 .resource = da850_psc0_resources,
704 .num_resources = ARRAY_SIZE(da850_psc0_resources),
705};
706
707static struct resource da850_psc1_resources[] = {
708 {
709 .start = DA8XX_PSC1_BASE,
710 .end = DA8XX_PSC1_BASE + SZ_4K - 1,
711 .flags = IORESOURCE_MEM,
712 },
713};
714
715static struct platform_device da850_psc1_device = {
716 .name = "da850-psc1",
717 .id = -1,
718 .resource = da850_psc1_resources,
719 .num_resources = ARRAY_SIZE(da850_psc1_resources),
720};
721
722static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
723
724static struct platform_device da850_async1_clksrc_device = {
725 .name = "da850-async1-clksrc",
726 .id = -1,
727 .dev = {
728 .platform_data = &da850_async1_pdata,
729 },
730};
731
732static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
733
734static struct platform_device da850_async3_clksrc_device = {
735 .name = "da850-async3-clksrc",
736 .id = -1,
737 .dev = {
738 .platform_data = &da850_async3_pdata,
739 },
740};
741
742static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
743
744static struct platform_device da850_tbclksync_device = {
745 .name = "da830-tbclksync",
746 .id = -1,
747 .dev = {
748 .platform_data = &da850_tbclksync_pdata,
749 },
750};
751
752void __init da850_register_clocks(void)
753{
754
755
756 da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
757 platform_device_register(&da850_pll1_device);
758
759 da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
760 platform_device_register(&da850_async1_clksrc_device);
761
762 da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
763 platform_device_register(&da850_async3_clksrc_device);
764
765 platform_device_register(&da850_psc0_device);
766
767 platform_device_register(&da850_psc1_device);
768
769 da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
770 platform_device_register(&da850_tbclksync_device);
771}
772
