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7#include <linux/kernel.h>
8#include <linux/io.h>
9#include <linux/init.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12
13#include <asm/cacheflush.h>
14#include <asm/cputype.h>
15#include <asm/firmware.h>
16#include <asm/hardware/cache-l2x0.h>
17#include <asm/suspend.h>
18
19#include "common.h"
20#include "smc.h"
21
22#define EXYNOS_BOOT_ADDR 0x8
23#define EXYNOS_BOOT_FLAG 0xc
24
25static void exynos_save_cp15(void)
26{
27
28 asm ("mrc p15, 0, %0, c15, c0, 0\n"
29 "mrc p15, 0, %1, c15, c0, 1\n"
30 : "=r" (cp15_save_power), "=r" (cp15_save_diag)
31 : : "cc");
32}
33
34static int exynos_do_idle(unsigned long mode)
35{
36 switch (mode) {
37 case FW_DO_IDLE_AFTR:
38 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
39 exynos_save_cp15();
40 writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
41 sysram_ns_base_addr + 0x24);
42 writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
43 if (soc_is_exynos3250()) {
44 flush_cache_all();
45 exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
46 SMC_POWERSTATE_IDLE, 0);
47 exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
48 SMC_POWERSTATE_IDLE, 0);
49 } else
50 exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
51 break;
52 case FW_DO_IDLE_SLEEP:
53 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
54 }
55 return 0;
56}
57
58static int exynos_cpu_boot(int cpu)
59{
60
61
62
63
64 if (soc_is_exynos3250())
65 return 0;
66
67
68
69
70 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
71 return 0;
72}
73
74static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
75{
76 void __iomem *boot_reg;
77
78 if (!sysram_ns_base_addr)
79 return -ENODEV;
80
81 boot_reg = sysram_ns_base_addr + 0x1c;
82
83
84
85
86
87
88 if (soc_is_exynos4412())
89 boot_reg += 4 * cpu;
90
91 writel_relaxed(boot_addr, boot_reg);
92 return 0;
93}
94
95static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
96{
97 void __iomem *boot_reg;
98
99 if (!sysram_ns_base_addr)
100 return -ENODEV;
101
102 boot_reg = sysram_ns_base_addr + 0x1c;
103
104 if (soc_is_exynos4412())
105 boot_reg += 4 * cpu;
106
107 *boot_addr = readl_relaxed(boot_reg);
108 return 0;
109}
110
111static int exynos_cpu_suspend(unsigned long arg)
112{
113 flush_cache_all();
114 outer_flush_all();
115
116 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
117
118 pr_info("Failed to suspend the system\n");
119 writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
120 return 1;
121}
122
123static int exynos_suspend(void)
124{
125 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
126 exynos_save_cp15();
127
128 writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
129 writel(__pa_symbol(exynos_cpu_resume_ns),
130 sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
131
132 return cpu_suspend(0, exynos_cpu_suspend);
133}
134
135static int exynos_resume(void)
136{
137 writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
138
139 return 0;
140}
141
142static const struct firmware_ops exynos_firmware_ops = {
143 .do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
144 .set_cpu_boot_addr = exynos_set_cpu_boot_addr,
145 .get_cpu_boot_addr = exynos_get_cpu_boot_addr,
146 .cpu_boot = exynos_cpu_boot,
147 .suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
148 .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
149};
150
151static void exynos_l2_write_sec(unsigned long val, unsigned reg)
152{
153 static int l2cache_enabled;
154
155 switch (reg) {
156 case L2X0_CTRL:
157 if (val & L2X0_CTRL_EN) {
158
159
160
161
162 if (!l2cache_enabled) {
163 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
164 l2cache_enabled = 1;
165 }
166 } else {
167 l2cache_enabled = 0;
168 }
169 exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
170 break;
171
172 case L2X0_DEBUG_CTRL:
173 exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
174 break;
175
176 default:
177 WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
178 }
179}
180
181static void exynos_l2_configure(const struct l2x0_regs *regs)
182{
183 exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
184 regs->prefetch_ctrl);
185 exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
186}
187
188bool __init exynos_secure_firmware_available(void)
189{
190 struct device_node *nd;
191 const __be32 *addr;
192
193 nd = of_find_compatible_node(NULL, NULL,
194 "samsung,secure-firmware");
195 if (!nd)
196 return false;
197
198 addr = of_get_address(nd, 0, NULL, NULL);
199 of_node_put(nd);
200 if (!addr) {
201 pr_err("%s: No address specified.\n", __func__);
202 return false;
203 }
204
205 return true;
206}
207
208void __init exynos_firmware_init(void)
209{
210 if (!exynos_secure_firmware_available())
211 return;
212
213 pr_info("Running under secure firmware.\n");
214
215 register_firmware_ops(&exynos_firmware_ops);
216
217
218
219
220
221
222
223 if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
224 read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
225 outer_cache.write_sec = exynos_l2_write_sec;
226 outer_cache.configure = exynos_l2_configure;
227 }
228}
229
230#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
231#define BOOT_MODE_MASK 0x1f
232
233void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
234{
235 unsigned int tmp;
236
237 tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
238
239 if (mode & BOOT_MODE_MASK)
240 tmp &= ~BOOT_MODE_MASK;
241
242 tmp |= mode;
243 writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
244}
245
246void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
247{
248 unsigned int tmp;
249
250 tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
251 tmp &= ~mode;
252 writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
253}
254
