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16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/serial.h>
20#include <linux/tty.h>
21#include <linux/platform_device.h>
22#include <linux/serial_core.h>
23#include <linux/interrupt.h>
24#include <linux/bitops.h>
25#include <linux/io.h>
26#include <linux/export.h>
27#include <linux/cpu.h>
28#include <linux/pci.h>
29#include <linux/sched_clock.h>
30#include <linux/soc/ixp4xx/cpu.h>
31#include <linux/irqchip/irq-ixp4xx.h>
32#include <linux/platform_data/timer-ixp4xx.h>
33#include <linux/dma-map-ops.h>
34#include <mach/udc.h>
35#include <mach/hardware.h>
36#include <linux/uaccess.h>
37#include <asm/page.h>
38#include <asm/exception.h>
39#include <asm/irq.h>
40#include <asm/system_misc.h>
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/time.h>
44
45#include "irqs.h"
46
47u32 ixp4xx_read_feature_bits(void)
48{
49 u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
50
51 if (cpu_is_ixp42x_rev_a0())
52 return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
53 IXP4XX_FEATURE_AES);
54 if (cpu_is_ixp42x())
55 return val & IXP42X_FEATURE_MASK;
56 if (cpu_is_ixp43x())
57 return val & IXP43X_FEATURE_MASK;
58 return val & IXP46X_FEATURE_MASK;
59}
60EXPORT_SYMBOL(ixp4xx_read_feature_bits);
61
62void ixp4xx_write_feature_bits(u32 value)
63{
64 __raw_writel(~value, IXP4XX_EXP_CFG2);
65}
66EXPORT_SYMBOL(ixp4xx_write_feature_bits);
67
68#define IXP4XX_TIMER_FREQ 66666000
69
70
71
72
73static struct map_desc ixp4xx_io_desc[] __initdata = {
74 {
75 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
76 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
77 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
78 .type = MT_DEVICE
79 }, {
80 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
81 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
82 .length = IXP4XX_EXP_CFG_REGION_SIZE,
83 .type = MT_DEVICE
84 }, {
85 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
86 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
87 .length = IXP4XX_PCI_CFG_REGION_SIZE,
88 .type = MT_DEVICE
89 },
90};
91
92void __init ixp4xx_map_io(void)
93{
94 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
95}
96
97void __init ixp4xx_init_irq(void)
98{
99
100
101
102
103 cpu_idle_poll_ctrl(true);
104
105 ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
106 (cpu_is_ixp46x() || cpu_is_ixp43x()));
107}
108
109void __init ixp4xx_timer_init(void)
110{
111 return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
112 IRQ_IXP4XX_TIMER1,
113 IXP4XX_TIMER_FREQ);
114}
115
116static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
117
118void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
119{
120 memcpy(&ixp4xx_udc_info, info, sizeof *info);
121}
122
123static struct resource ixp4xx_udc_resources[] = {
124 [0] = {
125 .start = 0xc800b000,
126 .end = 0xc800bfff,
127 .flags = IORESOURCE_MEM,
128 },
129 [1] = {
130 .start = IRQ_IXP4XX_USB,
131 .end = IRQ_IXP4XX_USB,
132 .flags = IORESOURCE_IRQ,
133 },
134};
135
136static struct resource ixp4xx_gpio_resource[] = {
137 {
138 .start = IXP4XX_GPIO_BASE_PHYS,
139 .end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
140 .flags = IORESOURCE_MEM,
141 },
142};
143
144static struct platform_device ixp4xx_gpio_device = {
145 .name = "ixp4xx-gpio",
146 .id = -1,
147 .dev = {
148 .coherent_dma_mask = DMA_BIT_MASK(32),
149 },
150 .resource = ixp4xx_gpio_resource,
151 .num_resources = ARRAY_SIZE(ixp4xx_gpio_resource),
152};
153
154
155
156
157
158static struct platform_device ixp4xx_udc_device = {
159 .name = "pxa25x-udc",
160 .id = -1,
161 .num_resources = 2,
162 .resource = ixp4xx_udc_resources,
163 .dev = {
164 .platform_data = &ixp4xx_udc_info,
165 },
166};
167
168static struct resource ixp4xx_npe_resources[] = {
169 {
170 .start = IXP4XX_NPEA_BASE_PHYS,
171 .end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
172 .flags = IORESOURCE_MEM,
173 },
174 {
175 .start = IXP4XX_NPEB_BASE_PHYS,
176 .end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
177 .flags = IORESOURCE_MEM,
178 },
179 {
180 .start = IXP4XX_NPEC_BASE_PHYS,
181 .end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
182 .flags = IORESOURCE_MEM,
183 },
184
185};
186
187static struct platform_device ixp4xx_npe_device = {
188 .name = "ixp4xx-npe",
189 .id = -1,
190 .num_resources = ARRAY_SIZE(ixp4xx_npe_resources),
191 .resource = ixp4xx_npe_resources,
192};
193
194static struct resource ixp4xx_qmgr_resources[] = {
195 {
196 .start = IXP4XX_QMGR_BASE_PHYS,
197 .end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .start = IRQ_IXP4XX_QM1,
202 .end = IRQ_IXP4XX_QM1,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .start = IRQ_IXP4XX_QM2,
207 .end = IRQ_IXP4XX_QM2,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212static struct platform_device ixp4xx_qmgr_device = {
213 .name = "ixp4xx-qmgr",
214 .id = -1,
215 .num_resources = ARRAY_SIZE(ixp4xx_qmgr_resources),
216 .resource = ixp4xx_qmgr_resources,
217};
218
219static struct platform_device *ixp4xx_devices[] __initdata = {
220 &ixp4xx_npe_device,
221 &ixp4xx_qmgr_device,
222 &ixp4xx_gpio_device,
223 &ixp4xx_udc_device,
224};
225
226static struct resource ixp46x_i2c_resources[] = {
227 [0] = {
228 .start = 0xc8011000,
229 .end = 0xc801101c,
230 .flags = IORESOURCE_MEM,
231 },
232 [1] = {
233 .start = IRQ_IXP4XX_I2C,
234 .end = IRQ_IXP4XX_I2C,
235 .flags = IORESOURCE_IRQ
236 }
237};
238
239
240#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100
241
242static struct resource ixp46x_hwrandom_resource[] = {
243 {
244 .start = IXP4XX_HWRANDOM_BASE_PHYS,
245 .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3,
246 .flags = IORESOURCE_MEM,
247 },
248};
249
250static struct platform_device ixp46x_hwrandom_device = {
251 .name = "ixp4xx-hwrandom",
252 .id = -1,
253 .dev = {
254 .coherent_dma_mask = DMA_BIT_MASK(32),
255 },
256 .resource = ixp46x_hwrandom_resource,
257 .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource),
258};
259
260
261
262
263
264static struct platform_device ixp46x_i2c_controller = {
265 .name = "IOP3xx-I2C",
266 .id = 0,
267 .num_resources = 2,
268 .resource = ixp46x_i2c_resources
269};
270
271static struct resource ixp46x_ptp_resources[] = {
272 DEFINE_RES_MEM(IXP4XX_TIMESYNC_BASE_PHYS, SZ_4K),
273 DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO8, "master"),
274 DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO7, "slave"),
275};
276
277static struct platform_device ixp46x_ptp = {
278 .name = "ptp-ixp46x",
279 .id = -1,
280 .resource = ixp46x_ptp_resources,
281 .num_resources = ARRAY_SIZE(ixp46x_ptp_resources),
282};
283
284static struct platform_device *ixp46x_devices[] __initdata = {
285 &ixp46x_hwrandom_device,
286 &ixp46x_i2c_controller,
287 &ixp46x_ptp,
288};
289
290unsigned long ixp4xx_exp_bus_size;
291EXPORT_SYMBOL(ixp4xx_exp_bus_size);
292
293static struct platform_device_info ixp_dev_info __initdata = {
294 .name = "ixp4xx_crypto",
295 .id = 0,
296 .dma_mask = DMA_BIT_MASK(32),
297};
298
299static int __init ixp_crypto_register(void)
300{
301 struct platform_device *pdev;
302
303 if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
304 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
305 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
306 return -ENODEV;
307 }
308
309 pdev = platform_device_register_full(&ixp_dev_info);
310 if (IS_ERR(pdev))
311 return PTR_ERR(pdev);
312
313 return 0;
314}
315
316void __init ixp4xx_sys_init(void)
317{
318 ixp4xx_exp_bus_size = SZ_16M;
319
320 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
321
322 if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX))
323 ixp_crypto_register();
324
325 if (cpu_is_ixp46x()) {
326 int region;
327
328 platform_add_devices(ixp46x_devices,
329 ARRAY_SIZE(ixp46x_devices));
330
331 for (region = 0; region < 7; region++) {
332 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
333 ixp4xx_exp_bus_size = SZ_32M;
334 break;
335 }
336 }
337 }
338
339 printk("IXP4xx: Using %luMiB expansion bus window size\n",
340 ixp4xx_exp_bus_size >> 20);
341}
342
343unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
344EXPORT_SYMBOL(ixp4xx_timer_freq);
345
346void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
347{
348 if (mode == REBOOT_SOFT) {
349
350 soft_restart(0);
351 } else {
352
353
354
355
356
357 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
358
359
360 *IXP4XX_OSWT = 0;
361
362 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
363 }
364}
365
366#ifdef CONFIG_PCI
367static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
368{
369 return (dma_addr + size) > SZ_64M;
370}
371
372static int ixp4xx_platform_notify_remove(struct device *dev)
373{
374 if (dev_is_pci(dev))
375 dmabounce_unregister_dev(dev);
376
377 return 0;
378}
379#endif
380
381
382
383
384static int ixp4xx_platform_notify(struct device *dev)
385{
386 dev->dma_mask = &dev->coherent_dma_mask;
387
388#ifdef CONFIG_PCI
389 if (dev_is_pci(dev)) {
390 dev->coherent_dma_mask = DMA_BIT_MASK(28);
391 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
392 return 0;
393 }
394#endif
395
396 dev->coherent_dma_mask = DMA_BIT_MASK(32);
397 return 0;
398}
399
400int dma_set_coherent_mask(struct device *dev, u64 mask)
401{
402 if (dev_is_pci(dev))
403 mask &= DMA_BIT_MASK(28);
404
405 if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
406 dev->coherent_dma_mask = mask;
407 return 0;
408 }
409
410 return -EIO;
411}
412EXPORT_SYMBOL(dma_set_coherent_mask);
413
414#ifdef CONFIG_IXP4XX_INDIRECT_PCI
415
416
417
418
419
420
421
422static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
423 unsigned int mtype, void *caller)
424{
425 if (!is_pci_memory(addr))
426 return __arm_ioremap_caller(addr, size, mtype, caller);
427
428 return (void __iomem *)addr;
429}
430
431static void ixp4xx_iounmap(volatile void __iomem *addr)
432{
433 if (!is_pci_memory((__force u32)addr))
434 __iounmap(addr);
435}
436#endif
437
438void __init ixp4xx_init_early(void)
439{
440 platform_notify = ixp4xx_platform_notify;
441#ifdef CONFIG_PCI
442 platform_notify_remove = ixp4xx_platform_notify_remove;
443#endif
444#ifdef CONFIG_IXP4XX_INDIRECT_PCI
445 arch_ioremap_caller = ixp4xx_ioremap_caller;
446 arch_iounmap = ixp4xx_iounmap;
447#endif
448}
449
