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10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/io.h>
15
16#include "iomap.h"
17#include "common.h"
18#include "prcm-common.h"
19#include "prm44xx.h"
20#include "prm54xx.h"
21#include "prm7xx.h"
22#include "prminst44xx.h"
23#include "prm-regbits-44xx.h"
24#include "prcm44xx.h"
25#include "prcm43xx.h"
26#include "prcm_mpu44xx.h"
27#include "soc.h"
28
29static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
30
31static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
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38
39void omap_prm_base_init(void)
40{
41 memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
42 sizeof(prm_base));
43 memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
44 sizeof(prcm_mpu_base));
45}
46
47s32 omap4_prmst_get_prm_dev_inst(void)
48{
49 return prm_dev_inst;
50}
51
52void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
53{
54 prm_dev_inst = dev_inst;
55}
56
57
58u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
59{
60 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
61 part == OMAP4430_INVALID_PRCM_PARTITION ||
62 !_prm_bases[part].va);
63 return readl_relaxed(_prm_bases[part].va + inst + idx);
64}
65
66
67void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
68{
69 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
70 part == OMAP4430_INVALID_PRCM_PARTITION ||
71 !_prm_bases[part].va);
72 writel_relaxed(val, _prm_bases[part].va + inst + idx);
73}
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75
76u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
77 u16 idx)
78{
79 u32 v;
80
81 v = omap4_prminst_read_inst_reg(part, inst, idx);
82 v &= ~mask;
83 v |= bits;
84 omap4_prminst_write_inst_reg(v, part, inst, idx);
85
86 return v;
87}
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99int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
100 u16 rstctrl_offs)
101{
102 u32 v;
103
104 v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
105 v &= 1 << shift;
106 v >>= shift;
107
108 return v;
109}
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122
123int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
124 u16 rstctrl_offs)
125{
126 u32 mask = 1 << shift;
127
128 omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
129
130 return 0;
131}
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152int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
153 u16 rstctrl_offs, u16 rstst_offs)
154{
155 int c;
156 u32 mask = 1 << shift;
157 u32 st_mask = 1 << st_shift;
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160 if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
161 rstctrl_offs) == 0)
162 return -EEXIST;
163
164
165 omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
166 rstst_offs);
167
168 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
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170 omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
171 inst, rstst_offs),
172 MAX_MODULE_HARDRESET_WAIT, c);
173
174 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
175}
176
177
178void omap4_prminst_global_warm_sw_reset(void)
179{
180 u32 v;
181 s32 inst = omap4_prmst_get_prm_dev_inst();
182
183 if (inst == PRM_INSTANCE_UNKNOWN)
184 return;
185
186 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
187 OMAP4_PRM_RSTCTRL_OFFSET);
188 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
189 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
190 inst, OMAP4_PRM_RSTCTRL_OFFSET);
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193 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
194 inst, OMAP4_PRM_RSTCTRL_OFFSET);
195}
196