1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * arch/arm/mach-pxa/include/mach/hardware.h 4 * 5 * Author: Nicolas Pitre 6 * Created: Jun 15, 2001 7 * Copyright: MontaVista Software Inc. 8 */ 9 10#ifndef __ASM_ARCH_HARDWARE_H 11#define __ASM_ARCH_HARDWARE_H 12 13#include <mach/addr-map.h> 14 15/* 16 * Workarounds for at least 2 errata so far require this. 17 * The mapping is set in mach-pxa/generic.c. 18 */ 19#define UNCACHED_PHYS_0 0xfe000000 20#define UNCACHED_PHYS_0_SIZE 0x00100000 21 22/* 23 * Intel PXA2xx internal register mapping: 24 * 25 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff 26 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff 27 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff 28 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff 29 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff 30 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff 31 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff 32 * 33 * Note that not all PXA2xx chips implement all those addresses, and the 34 * kernel only maps the minimum needed range of this mapping. 35 */ 36#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) 37#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) 38 39#ifndef __ASSEMBLY__ 40# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) 41 42/* With indexed regs we don't want to feed the index through io_p2v() 43 especially if it is a variable, otherwise horrible code will result. */ 44# define __REG2(x,y) \ 45 (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) 46 47# define __PREG(x) (io_v2p((u32)&(x))) 48 49#else 50 51# define __REG(x) io_p2v(x) 52# define __PREG(x) io_v2p(x) 53 54#endif 55 56#ifndef __ASSEMBLY__ 57 58#include <asm/cputype.h> 59 60/* 61 * CPU Stepping CPU_ID JTAG_ID 62 * 63 * PXA210 B0 0x69052922 0x2926C013 64 * PXA210 B1 0x69052923 0x3926C013 65 * PXA210 B2 0x69052924 0x4926C013 66 * PXA210 C0 0x69052D25 0x5926C013 67 * 68 * PXA250 A0 0x69052100 0x09264013 69 * PXA250 A1 0x69052101 0x19264013 70 * PXA250 B0 0x69052902 0x29264013 71 * PXA250 B1 0x69052903 0x39264013 72 * PXA250 B2 0x69052904 0x49264013 73 * PXA250 C0 0x69052D05 0x59264013 74 * 75 * PXA255 A0 0x69052D06 0x69264013 76 * 77 * PXA26x A0 0x69052903 0x39264013 78 * PXA26x B0 0x69052D05 0x59264013 79 * 80 * PXA27x A0 0x69054110 0x09265013 81 * PXA27x A1 0x69054111 0x19265013 82 * PXA27x B0 0x69054112 0x29265013 83 * PXA27x B1 0x69054113 0x39265013 84 * PXA27x C0 0x69054114 0x49265013 85 * PXA27x C5 0x69054117 0x79265013 86 * 87 * PXA30x A0 0x69056880 0x0E648013 88 * PXA30x A1 0x69056881 0x1E648013 89 * PXA31x A0 0x69056890 0x0E649013 90 * PXA31x A1 0x69056891 0x1E649013 91 * PXA31x A2 0x69056892 0x2E649013 92 * PXA32x B1 0x69056825 0x5E642013 93 * PXA32x B2 0x69056826 0x6E642013 94 * 95 * PXA930 B0 0x69056835 0x5E643013 96 * PXA930 B1 0x69056837 0x7E643013 97 * PXA930 B2 0x69056838 0x8E643013 98 * 99 * PXA935 A0 0x56056931 0x1E653013 100 * PXA935 B0 0x56056936 0x6E653013 101 * PXA935 B1 0x56056938 0x8E653013 102 */ 103#ifdef CONFIG_PXA25x 104#define __cpu_is_pxa210(id) \ 105 ({ \ 106 unsigned int _id = (id) & 0xf3f0; \ 107 _id == 0x2120; \ 108 }) 109 110#define __cpu_is_pxa250(id) \ 111 ({ \ 112 unsigned int _id = (id) & 0xf3ff; \ 113 _id <= 0x2105; \ 114 }) 115 116#define __cpu_is_pxa255(id) \ 117 ({ \ 118 unsigned int _id = (id) & 0xffff; \ 119 _id == 0x2d06; \ 120 }) 121 122#define __cpu_is_pxa25x(id) \ 123 ({ \ 124 unsigned int _id = (id) & 0xf300; \ 125 _id == 0x2100; \ 126 }) 127#else 128#define __cpu_is_pxa210(id) (0) 129#define __cpu_is_pxa250(id) (0) 130#define __cpu_is_pxa255(id) (0) 131#define __cpu_is_pxa25x(id) (0) 132#endif 133 134#ifdef CONFIG_PXA27x 135#define __cpu_is_pxa27x(id) \ 136 ({ \ 137 unsigned int _id = (id) >> 4 & 0xfff; \ 138 _id == 0x411; \ 139 }) 140#else 141#define __cpu_is_pxa27x(id) (0) 142#endif 143 144#ifdef CONFIG_CPU_PXA300 145#define __cpu_is_pxa300(id) \ 146 ({ \ 147 unsigned int _id = (id) >> 4 & 0xfff; \ 148 _id == 0x688; \ 149 }) 150#else 151#define __cpu_is_pxa300(id) (0) 152#endif 153 154#ifdef CONFIG_CPU_PXA310 155#define __cpu_is_pxa310(id) \ 156 ({ \ 157 unsigned int _id = (id) >> 4 & 0xfff; \ 158 _id == 0x689; \ 159 }) 160#else 161#define __cpu_is_pxa310(id) (0) 162#endif 163 164#ifdef CONFIG_CPU_PXA320 165#define __cpu_is_pxa320(id) \ 166 ({ \ 167 unsigned int _id = (id) >> 4 & 0xfff; \ 168 _id == 0x603 || _id == 0x682; \ 169 }) 170#else 171#define __cpu_is_pxa320(id) (0) 172#endif 173 174#ifdef CONFIG_CPU_PXA930 175#define __cpu_is_pxa930(id) \ 176 ({ \ 177 unsigned int _id = (id) >> 4 & 0xfff; \ 178 _id == 0x683; \ 179 }) 180#else 181#define __cpu_is_pxa930(id) (0) 182#endif 183 184#ifdef CONFIG_CPU_PXA935 185#define __cpu_is_pxa935(id) \ 186 ({ \ 187 unsigned int _id = (id) >> 4 & 0xfff; \ 188 _id == 0x693; \ 189 }) 190#else 191#define __cpu_is_pxa935(id) (0) 192#endif 193 194#define cpu_is_pxa210() \ 195 ({ \ 196 __cpu_is_pxa210(read_cpuid_id()); \ 197 }) 198 199#define cpu_is_pxa250() \ 200 ({ \ 201 __cpu_is_pxa250(read_cpuid_id()); \ 202 }) 203 204#define cpu_is_pxa255() \ 205 ({ \ 206 __cpu_is_pxa255(read_cpuid_id()); \ 207 }) 208 209#define cpu_is_pxa25x() \ 210 ({ \ 211 __cpu_is_pxa25x(read_cpuid_id()); \ 212 }) 213 214#define cpu_is_pxa27x() \ 215 ({ \ 216 __cpu_is_pxa27x(read_cpuid_id()); \ 217 }) 218 219#define cpu_is_pxa300() \ 220 ({ \ 221 __cpu_is_pxa300(read_cpuid_id()); \ 222 }) 223 224#define cpu_is_pxa310() \ 225 ({ \ 226 __cpu_is_pxa310(read_cpuid_id()); \ 227 }) 228 229#define cpu_is_pxa320() \ 230 ({ \ 231 __cpu_is_pxa320(read_cpuid_id()); \ 232 }) 233 234#define cpu_is_pxa930() \ 235 ({ \ 236 __cpu_is_pxa930(read_cpuid_id()); \ 237 }) 238 239#define cpu_is_pxa935() \ 240 ({ \ 241 __cpu_is_pxa935(read_cpuid_id()); \ 242 }) 243 244 245 246/* 247 * CPUID Core Generation Bit 248 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x 249 */ 250#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) 251#define __cpu_is_pxa2xx(id) \ 252 ({ \ 253 unsigned int _id = (id) >> 13 & 0x7; \ 254 _id <= 0x2; \ 255 }) 256#else 257#define __cpu_is_pxa2xx(id) (0) 258#endif 259 260#ifdef CONFIG_PXA3xx 261#define __cpu_is_pxa3xx(id) \ 262 ({ \ 263 __cpu_is_pxa300(id) \ 264 || __cpu_is_pxa310(id) \ 265 || __cpu_is_pxa320(id) \ 266 || __cpu_is_pxa93x(id); \ 267 }) 268#else 269#define __cpu_is_pxa3xx(id) (0) 270#endif 271 272#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) 273#define __cpu_is_pxa93x(id) \ 274 ({ \ 275 __cpu_is_pxa930(id) \ 276 || __cpu_is_pxa935(id); \ 277 }) 278#else 279#define __cpu_is_pxa93x(id) (0) 280#endif 281 282#define cpu_is_pxa2xx() \ 283 ({ \ 284 __cpu_is_pxa2xx(read_cpuid_id()); \ 285 }) 286 287#define cpu_is_pxa3xx() \ 288 ({ \ 289 __cpu_is_pxa3xx(read_cpuid_id()); \ 290 }) 291 292#define cpu_is_pxa93x() \ 293 ({ \ 294 __cpu_is_pxa93x(read_cpuid_id()); \ 295 }) 296 297 298/* 299 * return current memory and LCD clock frequency in units of 10kHz 300 */ 301extern unsigned int get_memclk_frequency_10khz(void); 302 303#endif 304 305#endif /* _ASM_ARCH_HARDWARE_H */ 306