1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * FILE SA-1100.h 4 * 5 * Version 1.2 6 * Author Copyright (c) Marc A. Viredaz, 1998 7 * DEC Western Research Laboratory, Palo Alto, CA 8 * Date January 1998 (April 1997) 9 * System StrongARM SA-1100 10 * Language C or ARM Assembly 11 * Purpose Definition of constants related to the StrongARM 12 * SA-1100 microprocessor (Advanced RISC Machine (ARM) 13 * architecture version 4). This file is based on the 14 * StrongARM SA-1100 data sheet version 2.2. 15 * 16 */ 17 18 19/* Be sure that virtual mapping is defined right */ 20#ifndef __ASM_ARCH_HARDWARE_H 21#error You must include hardware.h not SA-1100.h 22#endif 23 24#include "bitfield.h" 25 26/* 27 * SA1100 CS line to physical address 28 */ 29 30#define SA1100_CS0_PHYS 0x00000000 31#define SA1100_CS1_PHYS 0x08000000 32#define SA1100_CS2_PHYS 0x10000000 33#define SA1100_CS3_PHYS 0x18000000 34#define SA1100_CS4_PHYS 0x40000000 35#define SA1100_CS5_PHYS 0x48000000 36 37/* 38 * Personal Computer Memory Card International Association (PCMCIA) sockets 39 */ 40 41#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ 42#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ 43#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ 44#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ 45#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ 46 47#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ 48#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ 49#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ 50#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ 51 52#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ 53#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ 54#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ 55#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ 56 57#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ 58 (0x20000000 + (Nb)*PCMCIASp) 59#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ 60#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ 61 (_PCMCIA (Nb) + 2*PCMCIAPrtSp) 62#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ 63 (_PCMCIA (Nb) + 3*PCMCIAPrtSp) 64 65#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ 66#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ 67#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ 68#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ 69 70#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ 71#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ 72#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ 73#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ 74 75 76/* 77 * Universal Serial Bus (USB) Device Controller (UDC) control registers 78 * 79 * Registers 80 * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device 81 * Controller (UDC) Control Register (read/write). 82 * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device 83 * Controller (UDC) Address Register (read/write). 84 * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device 85 * Controller (UDC) Output Maximum Packet size register 86 * (read/write). 87 * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device 88 * Controller (UDC) Input Maximum Packet size register 89 * (read/write). 90 * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device 91 * Controller (UDC) Control/Status register end-point 0 92 * (read/write). 93 * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device 94 * Controller (UDC) Control/Status register end-point 1 95 * (output, read/write). 96 * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device 97 * Controller (UDC) Control/Status register end-point 2 98 * (input, read/write). 99 * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device 100 * Controller (UDC) Data register end-point 0 101 * (read/write). 102 * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device 103 * Controller (UDC) Write Count register end-point 0 104 * (read). 105 * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device 106 * Controller (UDC) Data Register (read/write). 107 * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device 108 * Controller (UDC) Status Register (read/write). 109 */ 110 111#define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ 112#define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ 113#define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ 114#define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ 115#define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ 116#define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ 117#define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ 118#define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ 119#define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ 120#define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ 121#define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ 122 123#define UDCCR_UDD 0x00000001 /* UDC Disable */ 124#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ 125#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ 126#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ 127 /* (disable) */ 128#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ 129 /* (disable) */ 130#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ 131 /* (disable) */ 132#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ 133 /* (disable) */ 134#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ 135#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ 136 137#define UDCAR_ADD Fld (7, 0) /* function ADDress */ 138 139#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ 140 /* [byte] */ 141#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ 142 /* [1..256 byte] */ \ 143 (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) 144 145#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ 146 /* [byte] */ 147#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ 148 /* [1..256 byte] */ \ 149 (((Size) - 1) << FShft (UDCIMP_INMAXP)) 150 151#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ 152#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ 153#define UDCCS0_SST 0x00000004 /* Sent STall */ 154#define UDCCS0_FST 0x00000008 /* Force STall */ 155#define UDCCS0_DE 0x00000010 /* Data End */ 156#define UDCCS0_SE 0x00000020 /* Setup End (read) */ 157#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ 158 /* (write) */ 159#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ 160 161#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ 162 /* Service request (read) */ 163#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ 164#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ 165#define UDCCS1_SST 0x00000008 /* Sent STall */ 166#define UDCCS1_FST 0x00000010 /* Force STall */ 167#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ 168 169#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ 170 /* Service request (read) */ 171#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ 172#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ 173#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ 174#define UDCCS2_SST 0x00000010 /* Sent STall */ 175#define UDCCS2_FST 0x00000020 /* Force STall */ 176 177#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 178 179#define UDCWC_WC Fld (4, 0) /* Write Count */ 180 181#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 182 183#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ 184#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ 185#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ 186#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ 187#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ 188#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ 189 190 191/* 192 * Universal Asynchronous Receiver/Transmitter (UART) control registers 193 * 194 * Registers 195 * Ser1UTCR0 Serial port 1 Universal Asynchronous 196 * Receiver/Transmitter (UART) Control Register 0 197 * (read/write). 198 * Ser1UTCR1 Serial port 1 Universal Asynchronous 199 * Receiver/Transmitter (UART) Control Register 1 200 * (read/write). 201 * Ser1UTCR2 Serial port 1 Universal Asynchronous 202 * Receiver/Transmitter (UART) Control Register 2 203 * (read/write). 204 * Ser1UTCR3 Serial port 1 Universal Asynchronous 205 * Receiver/Transmitter (UART) Control Register 3 206 * (read/write). 207 * Ser1UTDR Serial port 1 Universal Asynchronous 208 * Receiver/Transmitter (UART) Data Register 209 * (read/write). 210 * Ser1UTSR0 Serial port 1 Universal Asynchronous 211 * Receiver/Transmitter (UART) Status Register 0 212 * (read/write). 213 * Ser1UTSR1 Serial port 1 Universal Asynchronous 214 * Receiver/Transmitter (UART) Status Register 1 (read). 215 * 216 * Ser2UTCR0 Serial port 2 Universal Asynchronous 217 * Receiver/Transmitter (UART) Control Register 0 218 * (read/write). 219 * Ser2UTCR1 Serial port 2 Universal Asynchronous 220 * Receiver/Transmitter (UART) Control Register 1 221 * (read/write). 222 * Ser2UTCR2 Serial port 2 Universal Asynchronous 223 * Receiver/Transmitter (UART) Control Register 2 224 * (read/write). 225 * Ser2UTCR3 Serial port 2 Universal Asynchronous 226 * Receiver/Transmitter (UART) Control Register 3 227 * (read/write). 228 * Ser2UTCR4 Serial port 2 Universal Asynchronous 229 * Receiver/Transmitter (UART) Control Register 4 230 * (read/write). 231 * Ser2UTDR Serial port 2 Universal Asynchronous 232 * Receiver/Transmitter (UART) Data Register 233 * (read/write). 234 * Ser2UTSR0 Serial port 2 Universal Asynchronous 235 * Receiver/Transmitter (UART) Status Register 0 236 * (read/write). 237 * Ser2UTSR1 Serial port 2 Universal Asynchronous 238 * Receiver/Transmitter (UART) Status Register 1 (read). 239 * 240 * Ser3UTCR0 Serial port 3 Universal Asynchronous 241 * Receiver/Transmitter (UART) Control Register 0 242 * (read/write). 243 * Ser3UTCR1 Serial port 3 Universal Asynchronous 244 * Receiver/Transmitter (UART) Control Register 1 245 * (read/write). 246 * Ser3UTCR2 Serial port 3 Universal Asynchronous 247 * Receiver/Transmitter (UART) Control Register 2 248 * (read/write). 249 * Ser3UTCR3 Serial port 3 Universal Asynchronous 250 * Receiver/Transmitter (UART) Control Register 3 251 * (read/write). 252 * Ser3UTDR Serial port 3 Universal Asynchronous 253 * Receiver/Transmitter (UART) Data Register 254 * (read/write). 255 * Ser3UTSR0 Serial port 3 Universal Asynchronous 256 * Receiver/Transmitter (UART) Status Register 0 257 * (read/write). 258 * Ser3UTSR1 Serial port 3 Universal Asynchronous 259 * Receiver/Transmitter (UART) Status Register 1 (read). 260 * 261 * Clocks 262 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 263 * or 3.5795 MHz). 264 * fua, Tua Frequency, period of the UART communication. 265 */ 266 267#define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ 268#define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ 269#define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ 270#define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ 271#define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ 272#define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ 273#define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ 274#define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ 275 276#define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ 277#define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ 278#define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ 279#define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ 280#define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ 281#define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ 282#define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ 283 284#define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ 285#define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ 286#define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ 287#define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ 288#define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ 289#define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ 290#define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ 291#define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ 292 293#define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ 294#define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ 295#define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ 296#define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ 297#define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ 298#define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ 299#define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ 300 301/* Those are still used in some places */ 302#define _Ser1UTCR0 __PREG(Ser1UTCR0) 303#define _Ser2UTCR0 __PREG(Ser2UTCR0) 304#define _Ser3UTCR0 __PREG(Ser3UTCR0) 305 306/* Register offsets */ 307#define UTCR0 0x00 308#define UTCR1 0x04 309#define UTCR2 0x08 310#define UTCR3 0x0c 311#define UTDR 0x14 312#define UTSR0 0x1c 313#define UTSR1 0x20 314 315#define UTCR0_PE 0x00000001 /* Parity Enable */ 316#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ 317#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ 318#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ 319#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ 320#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ 321#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ 322#define UTCR0_DSS 0x00000008 /* Data Size Select */ 323#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ 324#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ 325#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ 326 /* (ser. port 1: GPIO [18], */ 327 /* ser. port 3: GPIO [20]) */ 328#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ 329#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ 330#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ 331#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ 332#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ 333#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ 334#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ 335 (UTCR0_1StpBit + UTCR0_8BitData) 336 337#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ 338#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ 339 /* fua = fxtl/(16*(BRD[11:0] + 1)) */ 340 /* Tua = 16*(BRD [11:0] + 1)*Txtl */ 341#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 342 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ 343 FShft (UTCR1_BRD)) 344#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 345 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ 346 FShft (UTCR2_BRD)) 347 /* fua = fxtl/(16*Floor (Div/16)) */ 348 /* Tua = 16*Floor (Div/16)*Txtl */ 349#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 350 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ 351 FShft (UTCR1_BRD)) 352#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 353 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ 354 FShft (UTCR2_BRD)) 355 /* fua = fxtl/(16*Ceil (Div/16)) */ 356 /* Tua = 16*Ceil (Div/16)*Txtl */ 357 358#define UTCR3_RXE 0x00000001 /* Receive Enable */ 359#define UTCR3_TXE 0x00000002 /* Transmit Enable */ 360#define UTCR3_BRK 0x00000004 /* BReaK mode */ 361#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ 362 /* more Interrupt Enable */ 363#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ 364 /* Interrupt Enable */ 365#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ 366#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ 367 /* TIE, LBM can be set or cleared) */ \ 368 (UTCR3_RXE + UTCR3_TXE) 369 370#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ 371 /* (HP-SIR) modulation Enable */ 372#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ 373#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ 374#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ 375#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ 376#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ 377 378#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 379#if 0 /* Hidden receive FIFO bits */ 380#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ 381#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ 382#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 383#endif /* 0 */ 384 385#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ 386 /* Service request (read) */ 387#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ 388 /* more Service request (read) */ 389#define UTSR0_RID 0x00000004 /* Receiver IDle */ 390#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ 391#define UTSR0_REB 0x00000010 /* Receive End of Break */ 392#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ 393 394#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ 395#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ 396#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ 397#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ 398#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ 399#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ 400 401 402/* 403 * Synchronous Data Link Controller (SDLC) control registers 404 * 405 * Registers 406 * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) 407 * Control Register 0 (read/write). 408 * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) 409 * Control Register 1 (read/write). 410 * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) 411 * Control Register 2 (read/write). 412 * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) 413 * Control Register 3 (read/write). 414 * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) 415 * Control Register 4 (read/write). 416 * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) 417 * Data Register (read/write). 418 * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) 419 * Status Register 0 (read/write). 420 * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) 421 * Status Register 1 (read/write). 422 * 423 * Clocks 424 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 425 * or 3.5795 MHz). 426 * fsd, Tsd Frequency, period of the SDLC communication. 427 */ 428 429#define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ 430#define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ 431#define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ 432#define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ 433#define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ 434#define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ 435#define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ 436#define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ 437 438#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ 439#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ 440#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ 441#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ 442#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ 443#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ 444#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ 445#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ 446#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ 447#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ 448#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ 449#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ 450 /* (GPIO [16]) */ 451#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ 452#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ 453#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ 454#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ 455#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ 456#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ 457#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ 458#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ 459 460#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ 461 /* (GPIO [17]) */ 462#define SDCR1_TXE 0x00000002 /* Transmit Enable */ 463#define SDCR1_RXE 0x00000004 /* Receive Enable */ 464#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ 465 /* more Interrupt Enable */ 466#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ 467 /* Interrupt Enable */ 468#define SDCR1_AME 0x00000020 /* Address Match Enable */ 469#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ 470#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ 471#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ 472#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ 473 474#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ 475 476#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ 477#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ 478 /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ 479 /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ 480#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 481 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ 482 FShft (SDCR3_BRD)) 483#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 484 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ 485 FShft (SDCR4_BRD)) 486 /* fsd = fxtl/(16*Floor (Div/16)) */ 487 /* Tsd = 16*Floor (Div/16)*Txtl */ 488#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 489 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ 490 FShft (SDCR3_BRD)) 491#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 492 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ 493 FShft (SDCR4_BRD)) 494 /* fsd = fxtl/(16*Ceil (Div/16)) */ 495 /* Tsd = 16*Ceil (Div/16)*Txtl */ 496 497#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 498#if 0 /* Hidden receive FIFO bits */ 499#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ 500#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ 501#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 502#endif /* 0 */ 503 504#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ 505#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ 506#define SDSR0_RAB 0x00000004 /* Receive ABort */ 507#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ 508 /* Service request (read) */ 509#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ 510 /* more Service request (read) */ 511 512#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ 513#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ 514#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 515#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ 516#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ 517#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ 518#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ 519#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ 520 521 522/* 523 * High-Speed Serial to Parallel controller (HSSP) control registers 524 * 525 * Registers 526 * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel 527 * controller (HSSP) Control Register 0 (read/write). 528 * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel 529 * controller (HSSP) Control Register 1 (read/write). 530 * Ser2HSDR Serial port 2 High-Speed Serial to Parallel 531 * controller (HSSP) Data Register (read/write). 532 * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel 533 * controller (HSSP) Status Register 0 (read/write). 534 * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel 535 * controller (HSSP) Status Register 1 (read). 536 * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel 537 * controller (HSSP) Control Register 2 (read/write). 538 * [The HSCR2 register is only implemented in 539 * versions 2.0 (rev. = 8) and higher of the StrongARM 540 * SA-1100.] 541 */ 542 543#define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */ 544#define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */ 545#define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */ 546#define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */ 547#define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */ 548#define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */ 549 550#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ 551#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ 552#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ 553#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ 554#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ 555#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ 556#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ 557#define HSCR0_TXE 0x00000008 /* Transmit Enable */ 558#define HSCR0_RXE 0x00000010 /* Receive Enable */ 559#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ 560 /* more Interrupt Enable */ 561#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ 562 /* Interrupt Enable */ 563#define HSCR0_AME 0x00000080 /* Address Match Enable */ 564 565#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ 566 567#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 568#if 0 /* Hidden receive FIFO bits */ 569#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ 570#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ 571#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 572#endif /* 0 */ 573 574#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ 575#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ 576#define HSSR0_RAB 0x00000004 /* Receive ABort */ 577#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ 578 /* Service request (read) */ 579#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ 580 /* more Service request (read) */ 581#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ 582 583#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ 584#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ 585#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 586#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ 587#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ 588#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ 589#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ 590 591#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ 592#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ 593 /* (inverted) */ 594#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ 595 /* (non-inverted) */ 596#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ 597#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ 598 /* (inverted) */ 599#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ 600 /* (non-inverted) */ 601 602 603/* 604 * Multi-media Communications Port (MCP) control registers 605 * 606 * Registers 607 * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) 608 * Control Register 0 (read/write). 609 * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) 610 * Data Register 0 (audio, read/write). 611 * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) 612 * Data Register 1 (telecom, read/write). 613 * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) 614 * Data Register 2 (CODEC registers, read/write). 615 * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) 616 * Status Register (read/write). 617 * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) 618 * Control Register 1 (read/write). 619 * [The MCCR1 register is only implemented in 620 * versions 2.0 (rev. = 8) and higher of the StrongARM 621 * SA-1100.] 622 * 623 * Clocks 624 * fmc, Tmc Frequency, period of the MCP communication (10 MHz, 625 * 12 MHz, or GPIO [21]). 626 * faud, Taud Frequency, period of the audio sampling. 627 * ftcm, Ttcm Frequency, period of the telecom sampling. 628 */ 629 630#define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */ 631#define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */ 632#define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */ 633#define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */ 634#define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */ 635#define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */ 636 637#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ 638 /* [6..127] */ 639 /* faud = fmc/(32*ASD) */ 640 /* Taud = 32*ASD*Tmc */ 641#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ 642 /* [192..4064] */ \ 643 ((Div)/32 << FShft (MCCR0_ASD)) 644 /* faud = fmc/(32*Floor (Div/32)) */ 645 /* Taud = 32*Floor (Div/32)*Tmc */ 646#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ 647 (((Div) + 31)/32 << FShft (MCCR0_ASD)) 648 /* faud = fmc/(32*Ceil (Div/32)) */ 649 /* Taud = 32*Ceil (Div/32)*Tmc */ 650#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ 651 /* Divisor/32 [16..127] */ 652 /* ftcm = fmc/(32*TSD) */ 653 /* Ttcm = 32*TSD*Tmc */ 654#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ 655 /* [512..4064] */ \ 656 ((Div)/32 << FShft (MCCR0_TSD)) 657 /* ftcm = fmc/(32*Floor (Div/32)) */ 658 /* Ttcm = 32*Floor (Div/32)*Tmc */ 659#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ 660 (((Div) + 31)/32 << FShft (MCCR0_TSD)) 661 /* ftcm = fmc/(32*Ceil (Div/32)) */ 662 /* Ttcm = 32*Ceil (Div/32)*Tmc */ 663#define MCCR0_MCE 0x00010000 /* MCP Enable */ 664#define MCCR0_ECS 0x00020000 /* External Clock Select */ 665#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ 666#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ 667#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ 668 /* sampling/storing Mode */ 669#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ 670#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ 671#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ 672 /* or less interrupt Enable */ 673#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ 674 /* or more interrupt Enable */ 675#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ 676 /* or less interrupt Enable */ 677#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ 678 /* more interrupt Enable */ 679#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ 680#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ 681#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ 682 (((Div) - 1) << FShft (MCCR0_ECP)) 683 684#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ 685 /* FIFOs */ 686 687#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ 688 /* FIFOs */ 689 690 /* receive/transmit CODEC reg. */ 691 /* FIFOs: */ 692#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ 693#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ 694#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ 695#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ 696#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ 697 698#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ 699 /* or less Service request (read) */ 700#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ 701 /* more Service request (read) */ 702#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ 703 /* or less Service request (read) */ 704#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ 705 /* or more Service request (read) */ 706#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ 707#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ 708#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ 709#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ 710#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ 711 /* (read) */ 712#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ 713 /* (read) */ 714#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ 715 /* (read) */ 716#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ 717 /* (read) */ 718#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ 719 /* (read) */ 720#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ 721 /* (read) */ 722#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ 723#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ 724 725#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ 726#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ 727 /* (11.981 MHz) */ 728#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ 729 /* (9.585 MHz) */ 730 731 732/* 733 * Synchronous Serial Port (SSP) control registers 734 * 735 * Registers 736 * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control 737 * Register 0 (read/write). 738 * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control 739 * Register 1 (read/write). 740 * [Bits SPO and SP are only implemented in versions 2.0 741 * (rev. = 8) and higher of the StrongARM SA-1100.] 742 * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data 743 * Register (read/write). 744 * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status 745 * Register (read/write). 746 * 747 * Clocks 748 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 749 * or 3.5795 MHz). 750 * fss, Tss Frequency, period of the SSP communication. 751 */ 752 753#define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */ 754#define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */ 755#define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */ 756#define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */ 757 758#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ 759#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ 760 (((Size) - 1) << FShft (SSCR0_DSS)) 761#define SSCR0_FRF Fld (2, 4) /* FRame Format */ 762#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ 763 /* Interface (SPI) format */ \ 764 (0 << FShft (SSCR0_FRF)) 765#define SSCR0_TI /* Texas Instruments Synchronous */ \ 766 /* Serial format */ \ 767 (1 << FShft (SSCR0_FRF)) 768#define SSCR0_National /* National Microwire format */ \ 769 (2 << FShft (SSCR0_FRF)) 770#define SSCR0_SSE 0x00000080 /* SSP Enable */ 771#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ 772 /* fss = fxtl/(2*(SCR + 1)) */ 773 /* Tss = 2*(SCR + 1)*Txtl */ 774#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ 775 (((Div) - 2)/2 << FShft (SSCR0_SCR)) 776 /* fss = fxtl/(2*Floor (Div/2)) */ 777 /* Tss = 2*Floor (Div/2)*Txtl */ 778#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ 779 (((Div) - 1)/2 << FShft (SSCR0_SCR)) 780 /* fss = fxtl/(2*Ceil (Div/2)) */ 781 /* Tss = 2*Ceil (Div/2)*Txtl */ 782 783#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ 784 /* Interrupt Enable */ 785#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ 786 /* Interrupt Enable */ 787#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ 788#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ 789#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ 790#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ 791#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ 792#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ 793 /* after frame (SFRM, 1st edge) */ 794#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ 795 /* after frame (SFRM, 1st edge) */ 796#define SSCR1_ECS 0x00000020 /* External Clock Select */ 797#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ 798#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ 799 800#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ 801 802#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ 803#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 804#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ 805#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ 806 /* Service request (read) */ 807#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ 808 /* Service request (read) */ 809#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ 810 811 812/* 813 * Operating System (OS) timer control registers 814 * 815 * Registers 816 * OSMR0 Operating System (OS) timer Match Register 0 817 * (read/write). 818 * OSMR1 Operating System (OS) timer Match Register 1 819 * (read/write). 820 * OSMR2 Operating System (OS) timer Match Register 2 821 * (read/write). 822 * OSMR3 Operating System (OS) timer Match Register 3 823 * (read/write). 824 * OSCR Operating System (OS) timer Counter Register 825 * (read/write). 826 * OSSR Operating System (OS) timer Status Register 827 * (read/write). 828 * OWER Operating System (OS) timer Watch-dog Enable Register 829 * (read/write). 830 * OIER Operating System (OS) timer Interrupt Enable Register 831 * (read/write). 832 */ 833 834#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */ 835#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */ 836#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */ 837#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */ 838#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ 839#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ 840#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */ 841#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */ 842 843#define OSSR_M(Nb) /* Match detected [0..3] */ \ 844 (0x00000001 << (Nb)) 845#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ 846#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ 847#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ 848#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ 849 850#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ 851 /* (set only) */ 852 853#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ 854 (0x00000001 << (Nb)) 855#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ 856#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ 857#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ 858#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ 859 860 861/* 862 * Power Manager (PM) control registers 863 * 864 * Registers 865 * PMCR Power Manager (PM) Control Register (read/write). 866 * PSSR Power Manager (PM) Sleep Status Register (read/write). 867 * PSPR Power Manager (PM) Scratch-Pad Register (read/write). 868 * PWER Power Manager (PM) Wake-up Enable Register 869 * (read/write). 870 * PCFR Power Manager (PM) general ConFiguration Register 871 * (read/write). 872 * PPCR Power Manager (PM) Phase-Locked Loop (PLL) 873 * Configuration Register (read/write). 874 * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) 875 * Sleep state Register (read/write, see GPIO pins). 876 * POSR Power Manager (PM) Oscillator Status Register (read). 877 * 878 * Clocks 879 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 880 * or 3.5795 MHz). 881 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 882 */ 883 884#define PMCR __REG(0x90020000) /* PM Control Reg. */ 885#define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ 886#define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ 887#define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ 888#define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */ 889#define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */ 890#define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */ 891#define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */ 892 893#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ 894 895#define PSSR_SS 0x00000001 /* Software Sleep */ 896#define PSSR_BFS 0x00000002 /* Battery Fault Status */ 897 /* (BATT_FAULT) */ 898#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ 899#define PSSR_DH 0x00000008 /* DRAM control Hold */ 900#define PSSR_PH 0x00000010 /* Peripheral control Hold */ 901 902#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ 903#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ 904#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ 905#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ 906#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ 907#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ 908#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ 909#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ 910#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ 911#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ 912#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ 913#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ 914#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ 915#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ 916#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ 917#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ 918#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ 919#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ 920#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ 921#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ 922#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ 923#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ 924#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ 925#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ 926#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ 927#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ 928#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ 929#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ 930#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ 931#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ 932 933#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ 934#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ 935#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ 936#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ 937#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ 938#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ 939#define PCFR_FS 0x00000004 /* Float Static memory pins */ 940#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ 941#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ 942#define PCFR_FO 0x00000008 /* Force RTC oscillator */ 943 /* (32.768 kHz) enable On */ 944 945#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ 946#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ 947 (0x00 << FShft (PPCR_CCF)) 948#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ 949 (0x01 << FShft (PPCR_CCF)) 950#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ 951 (0x02 << FShft (PPCR_CCF)) 952#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ 953 (0x03 << FShft (PPCR_CCF)) 954#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ 955 (0x04 << FShft (PPCR_CCF)) 956#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ 957 (0x05 << FShft (PPCR_CCF)) 958#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ 959 (0x06 << FShft (PPCR_CCF)) 960#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ 961 (0x07 << FShft (PPCR_CCF)) 962#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ 963 (0x08 << FShft (PPCR_CCF)) 964#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ 965 (0x09 << FShft (PPCR_CCF)) 966#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ 967 (0x0A << FShft (PPCR_CCF)) 968#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ 969 (0x0B << FShft (PPCR_CCF)) 970#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ 971 (0x0C << FShft (PPCR_CCF)) 972#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ 973 (0x0D << FShft (PPCR_CCF)) 974#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ 975 (0x0E << FShft (PPCR_CCF)) 976#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ 977 (0x0F << FShft (PPCR_CCF)) 978 /* 3.6864 MHz crystal (fxtl): */ 979#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ 980#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ 981#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ 982#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ 983#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ 984#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ 985#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ 986#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ 987#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ 988#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ 989#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ 990#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ 991#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ 992#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ 993#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ 994#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ 995 /* 3.5795 MHz crystal (fxtl): */ 996#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ 997#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ 998#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ 999#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ 1000#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
1001#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ 1002#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ 1003#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ 1004#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ 1005#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ 1006#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ 1007#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ 1008#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ 1009#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ 1010#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ 1011#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ 1012 1013#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ 1014 1015 1016/* 1017 * Reset Controller (RC) control registers 1018 * 1019 * Registers 1020 * RSRR Reset Controller (RC) Software Reset Register 1021 * (read/write). 1022 * RCSR Reset Controller (RC) Status Register (read/write). 1023 */ 1024 1025#define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ 1026#define RCSR __REG(0x90030004) /* RC Status Reg. */ 1027 1028#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ 1029 1030#define RCSR_HWR 0x00000001 /* HardWare Reset */ 1031#define RCSR_SWR 0x00000002 /* SoftWare Reset */ 1032#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ 1033#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ 1034 1035 1036/* 1037 * Test unit control registers 1038 * 1039 * Registers 1040 * TUCR Test Unit Control Register (read/write). 1041 */ 1042 1043#define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ 1044 1045#define TUCR_TIC 0x00000040 /* TIC mode */ 1046#define TUCR_TTST 0x00000080 /* Trim TeST mode */ 1047#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ 1048 /* Check */ 1049#define TUCR_PMD 0x00000200 /* Power Management Disable */ 1050#define TUCR_MR 0x00000400 /* Memory Request mode */ 1051#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ 1052#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ 1053 /* grant (MBGNT) on GPIO [22:21] */ 1054#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ 1055#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ 1056#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ 1057#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ 1058#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ 1059#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ 1060#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ 1061 (0 << FShft (TUCR_TSEL)) 1062#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ 1063 (1 << FShft (TUCR_TSEL)) 1064#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ 1065 (2 << FShft (TUCR_TSEL)) 1066#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ 1067 (3 << FShft (TUCR_TSEL)) 1068#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ 1069 /* Clocks on GPIO [26:27] */ \ 1070 (4 << FShft (TUCR_TSEL)) 1071#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ 1072 /* (Alternative) */ \ 1073 (5 << FShft (TUCR_TSEL)) 1074#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ 1075 (6 << FShft (TUCR_TSEL)) 1076#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ 1077 (7 << FShft (TUCR_TSEL)) 1078 1079 1080/* 1081 * General-Purpose Input/Output (GPIO) control registers 1082 * 1083 * Registers 1084 * GPLR General-Purpose Input/Output (GPIO) Pin Level 1085 * Register (read). 1086 * GPDR General-Purpose Input/Output (GPIO) Pin Direction 1087 * Register (read/write). 1088 * GPSR General-Purpose Input/Output (GPIO) Pin output Set 1089 * Register (write). 1090 * GPCR General-Purpose Input/Output (GPIO) Pin output Clear 1091 * Register (write). 1092 * GRER General-Purpose Input/Output (GPIO) Rising-Edge 1093 * detect Register (read/write). 1094 * GFER General-Purpose Input/Output (GPIO) Falling-Edge 1095 * detect Register (read/write). 1096 * GEDR General-Purpose Input/Output (GPIO) Edge Detect 1097 * status Register (read/write). 1098 * GAFR General-Purpose Input/Output (GPIO) Alternate 1099 * Function Register (read/write). 1100 * 1101 * Clock 1102 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1103 */ 1104 1105#define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ 1106#define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ 1107#define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */ 1108#define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ 1109#define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */ 1110#define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */ 1111#define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */ 1112#define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */ 1113 1114#define GPIO_MIN (0) 1115#define GPIO_MAX (27) 1116 1117#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ 1118 (0x00000001 << (Nb)) 1119#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ 1120#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ 1121#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ 1122#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ 1123#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ 1124#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ 1125#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ 1126#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ 1127#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ 1128#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ 1129#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ 1130#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ 1131#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ 1132#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ 1133#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ 1134#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ 1135#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ 1136#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ 1137#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ 1138#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ 1139#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ 1140#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ 1141#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ 1142#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ 1143#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ 1144#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ 1145#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ 1146#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ 1147 1148#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ 1149 GPIO_GPIO ((Nb) - 6) 1150#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ 1151#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ 1152#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ 1153#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ 1154#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ 1155#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ 1156#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ 1157#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ 1158 /* ser. port 4: */ 1159#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ 1160#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ 1161#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ 1162#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ 1163 /* ser. port 1: */ 1164#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ 1165#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ 1166#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ 1167#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ 1168#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ 1169 /* ser. port 4: */ 1170#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ 1171 /* ser. port 3: */ 1172#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ 1173 /* ser. port 4: */ 1174#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ 1175 /* test controller: */ 1176#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ 1177#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ 1178#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ 1179#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ 1180#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ 1181#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ 1182#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ 1183#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ 1184 1185#define GPDR_In 0 /* Input */ 1186#define GPDR_Out 1 /* Output */ 1187 1188 1189/* 1190 * Interrupt Controller (IC) control registers 1191 * 1192 * Registers 1193 * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) 1194 * Pending register (read). 1195 * ICMR Interrupt Controller (IC) Mask Register (read/write). 1196 * ICLR Interrupt Controller (IC) Level Register (read/write). 1197 * ICCR Interrupt Controller (IC) Control Register 1198 * (read/write). 1199 * [The ICCR register is only implemented in versions 2.0 1200 * (rev. = 8) and higher of the StrongARM SA-1100.] 1201 * ICFP Interrupt Controller (IC) Fast Interrupt reQuest 1202 * (FIQ) Pending register (read). 1203 * ICPR Interrupt Controller (IC) Pending Register (read). 1204 * [The ICPR register is active low (inverted) in 1205 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1206 * StrongARM SA-1100, it is active high (non-inverted) in 1207 * versions 2.0 (rev. = 8) and higher.] 1208 */ 1209 1210#define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */ 1211#define ICMR __REG(0x90050004) /* IC Mask Reg. */ 1212#define ICLR __REG(0x90050008) /* IC Level Reg. */ 1213#define ICCR __REG(0x9005000C) /* IC Control Reg. */ 1214#define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */ 1215#define ICPR __REG(0x90050020) /* IC Pending Reg. */ 1216 1217#define IC_GPIO(Nb) /* GPIO [0..10] */ \ 1218 (0x00000001 << (Nb)) 1219#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ 1220#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ 1221#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ 1222#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ 1223#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ 1224#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ 1225#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ 1226#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ 1227#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ 1228#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ 1229#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ 1230#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ 1231#define IC_LCD 0x00001000 /* LCD controller */ 1232#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ 1233#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ 1234#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ 1235#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ 1236#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ 1237#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ 1238#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ 1239#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ 1240 (0x00100000 << (Nb)) 1241#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ 1242#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ 1243#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ 1244#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ 1245#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ 1246#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ 1247#define IC_OST(Nb) /* OS Timer match [0..3] */ \ 1248 (0x04000000 << (Nb)) 1249#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ 1250#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ 1251#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ 1252#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ 1253#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ 1254#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ 1255 1256#define ICLR_IRQ 0 /* Interrupt ReQuest */ 1257#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ 1258 1259#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ 1260 /* Mask */ 1261#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ 1262 /* (ICMR ignored) */ 1263#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ 1264 /* enable (ICMR used) */ 1265 1266 1267/* 1268 * Peripheral Pin Controller (PPC) control registers 1269 * 1270 * Registers 1271 * PPDR Peripheral Pin Controller (PPC) Pin Direction 1272 * Register (read/write). 1273 * PPSR Peripheral Pin Controller (PPC) Pin State Register 1274 * (read/write). 1275 * PPAR Peripheral Pin Controller (PPC) Pin Assignment 1276 * Register (read/write). 1277 * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin 1278 * Direction Register (read/write). 1279 * PPFR Peripheral Pin Controller (PPC) Pin Flag Register 1280 * (read). 1281 */ 1282 1283#define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */ 1284#define PPSR __REG(0x90060004) /* PPC Pin State Reg. */ 1285#define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */ 1286#define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */ 1287#define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */ 1288 1289#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ 1290 (0x00000001 << (Nb)) 1291#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ 1292#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ 1293#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ 1294#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ 1295#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ 1296#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ 1297#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ 1298#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ 1299#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ 1300#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ 1301#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ 1302#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ 1303 /* ser. port 1: */ 1304#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ 1305#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ 1306 /* ser. port 2: */ 1307#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ 1308#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ 1309 /* ser. port 3: */ 1310#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ 1311#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ 1312 /* ser. port 4: */ 1313#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ 1314#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ 1315#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ 1316#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ 1317 1318#define PPDR_In 0 /* Input */ 1319#define PPDR_Out 1 /* Output */ 1320 1321 /* ser. port 1: */ 1322#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ 1323#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ 1324#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ 1325 /* ser. port 4: */ 1326#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ 1327#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ 1328 /* & SFRM_C */ 1329#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ 1330 1331#define PSDR_OutL 0 /* Output Low in sleep mode */ 1332#define PSDR_Flt 1 /* Floating (input) in sleep mode */ 1333 1334#define PPFR_LCD 0x00000001 /* LCD controller */ 1335#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ 1336#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ 1337#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ 1338#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ 1339#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ 1340#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ 1341#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ 1342#define PPFR_PerEn 0 /* Peripheral Enabled */ 1343#define PPFR_PPCEn 1 /* PPC Enabled */ 1344 1345 1346/* 1347 * Dynamic Random-Access Memory (DRAM) control registers 1348 * 1349 * Registers 1350 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) 1351 * CoNFiGuration register (read/write). 1352 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) 1353 * Column Address Strobe (CAS) shift register 0 1354 * (read/write). 1355 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) 1356 * Column Address Strobe (CAS) shift register 1 1357 * (read/write). 1358 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) 1359 * Column Address Strobe (CAS) shift register 2 1360 * (read/write). 1361 * 1362 * Clocks 1363 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1364 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1365 * fcas, Tcas Frequency, period of the DRAM CAS shift registers. 1366 */ 1367 1368#define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ 1369#define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ 1370#define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ 1371#define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ 1372 1373/* SA1100 MDCNFG values */ 1374#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ 1375 (0x00000001 << (Nb)) 1376#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ 1377#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ 1378#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ 1379#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ 1380#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ 1381#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ 1382 (((Add) - 9) << FShft (MDCNFG_DRAC)) 1383#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ 1384 /* (fcas = fcpu/2) */ 1385#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ 1386#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ 1387 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) 1388#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ 1389 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) 1390#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ 1391#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ 1392 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) 1393#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ 1394 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) 1395#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ 1396#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ 1397 ((Tcpu) << FShft (MDCNFG_TDL)) 1398#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ 1399 /* [Tmem] */ 1400#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ 1401 /* [0..262136 Tcpu] */ \ 1402 ((Tcpu)/8 << FShft (MDCNFG_DRI)) 1403 1404/* SA1110 MDCNFG values */ 1405#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ 1406#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ 1407#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ 1408#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ 1409#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ 1410 /* bank 0/1 */ 1411#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ 1412#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ 1413#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ 1414 /* deassertion 0/1 */ 1415#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ 1416#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ 1417#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ 1418#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ 1419#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ 1420#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ 1421 /* bank 0/1 */ 1422#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ 1423#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ 1424#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ 1425 /* deassertion 0/1 */ 1426#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ 1427 1428 1429/* 1430 * Static memory control registers 1431 * 1432 * Registers 1433 * MSC0 Memory system: Static memory Control register 0 1434 * (read/write). 1435 * MSC1 Memory system: Static memory Control register 1 1436 * (read/write). 1437 * 1438 * Clocks 1439 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1440 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1441 */ 1442 1443#define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ 1444#define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ 1445#define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */ 1446 1447#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ 1448 Fld (16, ((Nb) Modulo 2)*16) 1449#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ 1450#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ 1451#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ 1452#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ 1453 1454#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ 1455#define MSC_NonBrst /* Non-Burst static memory */ \ 1456 (0 << FShft (MSC_RT)) 1457#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ 1458 (1 << FShft (MSC_RT)) 1459#define MSC_Brst4 /* Burst-of-4 static memory */ \ 1460 (2 << FShft (MSC_RT)) 1461#define MSC_Brst8 /* Burst-of-8 static memory */ \ 1462 (3 << FShft (MSC_RT)) 1463#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ 1464#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ 1465#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ 1466#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ 1467 /* First access - 1(.5) [Tmem] */ 1468#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ 1469 /* static memory) [3..65 Tcpu] */ \ 1470 ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) 1471#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ 1472 ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) 1473#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ 1474 /* static memory) [2..64 Tcpu] */ \ 1475 ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) 1476#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ 1477 ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) 1478#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ 1479 /* Next access - 1 [Tmem] */ 1480#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ 1481 /* static memory) [2..64 Tcpu] */ \ 1482 ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) 1483#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ 1484 ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) 1485#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ 1486 /* static memory) [2..64 Tcpu] */ \ 1487 ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) 1488#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ 1489 ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) 1490#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ 1491 /* time/2 [Tmem] */ 1492#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ 1493 (((Tcpu)/4) << FShft (MSC_RRR)) 1494#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ 1495 ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) 1496 1497 1498/* 1499 * Personal Computer Memory Card International Association (PCMCIA) control 1500 * register 1501 * 1502 * Register 1503 * MECR Memory system: Expansion memory bus (PCMCIA) 1504 * Configuration Register (read/write). 1505 * 1506 * Clocks 1507 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1508 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1509 * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). 1510 */ 1511 1512 /* Memory system: */ 1513#define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */ 1514 1515#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ 1516 Fld (15, (Nb)*16) 1517#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ 1518#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ 1519 1520#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ 1521#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ 1522 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) 1523#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ 1524 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) 1525#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ 1526 /* [Tmem] */ 1527#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ 1528 ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) 1529#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ 1530 ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) 1531#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ 1532#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ 1533 ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) 1534#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ 1535 ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) 1536 1537/* 1538 * On SA1110 only 1539 */ 1540 1541#define MDREFR __REG(0xA000001C) 1542 1543#define MDREFR_TRASR Fld (4, 0) 1544#define MDREFR_DRI Fld (12, 4) 1545#define MDREFR_E0PIN (1 << 16) 1546#define MDREFR_K0RUN (1 << 17) 1547#define MDREFR_K0DB2 (1 << 18) 1548#define MDREFR_E1PIN (1 << 20) 1549#define MDREFR_K1RUN (1 << 21) 1550#define MDREFR_K1DB2 (1 << 22) 1551#define MDREFR_K2RUN (1 << 25) 1552#define MDREFR_K2DB2 (1 << 26) 1553#define MDREFR_EAPD (1 << 28) 1554#define MDREFR_KAPD (1 << 29) 1555#define MDREFR_SLFRSH (1 << 31) 1556 1557 1558/* 1559 * Direct Memory Access (DMA) control registers 1560 */ 1561#define DMA_SIZE (6 * 0x20) 1562#define DMA_PHYS 0xb0000000 1563 1564 1565/* 1566 * Liquid Crystal Display (LCD) control registers 1567 * 1568 * Registers 1569 * LCCR0 Liquid Crystal Display (LCD) Control Register 0 1570 * (read/write). 1571 * [Bits LDM, BAM, and ERM are only implemented in 1572 * versions 2.0 (rev. = 8) and higher of the StrongARM 1573 * SA-1100.] 1574 * LCSR Liquid Crystal Display (LCD) Status Register 1575 * (read/write). 1576 * [Bit LDD can be only read in versions 1.0 (rev. = 1) 1577 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be 1578 * read and written (cleared) in versions 2.0 (rev. = 8) 1579 * and higher.] 1580 * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access 1581 * (DMA) Base Address Register channel 1 (read/write). 1582 * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access 1583 * (DMA) Current Address Register channel 1 (read). 1584 * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access 1585 * (DMA) Base Address Register channel 2 (read/write). 1586 * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access 1587 * (DMA) Current Address Register channel 2 (read). 1588 * LCCR1 Liquid Crystal Display (LCD) Control Register 1 1589 * (read/write). 1590 * [The LCCR1 register can be only written in 1591 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1592 * StrongARM SA-1100, it can be written and read in 1593 * versions 2.0 (rev. = 8) and higher.] 1594 * LCCR2 Liquid Crystal Display (LCD) Control Register 2 1595 * (read/write). 1596 * [The LCCR1 register can be only written in 1597 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1598 * StrongARM SA-1100, it can be written and read in 1599 * versions 2.0 (rev. = 8) and higher.] 1600 * LCCR3 Liquid Crystal Display (LCD) Control Register 3 1601 * (read/write). 1602 * [The LCCR1 register can be only written in 1603 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1604 * StrongARM SA-1100, it can be written and read in 1605 * versions 2.0 (rev. = 8) and higher. Bit PCP is only 1606 * implemented in versions 2.0 (rev. = 8) and higher of 1607 * the StrongARM SA-1100.] 1608 * 1609 * Clocks 1610 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1611 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1612 * fpix, Tpix Frequency, period of the pixel clock. 1613 * fln, Tln Frequency, period of the line clock. 1614 * fac, Tac Frequency, period of the AC bias clock. 1615 */ 1616 1617#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ 1618#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ 1619 /* [byte] */ \ 1620 (16*LCD_PEntrySp) 1621#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ 1622 /* [byte] */ \ 1623 (256*LCD_PEntrySp) 1624#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ 1625 /* dummy-Palette Space [byte] */ \ 1626 (16*LCD_PEntrySp) 1627 1628#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ 1629#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ 1630#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ 1631#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ 1632#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ 1633#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ 1634 (0 << FShft (LCD_PBS)) 1635#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ 1636 (1 << FShft (LCD_PBS)) 1637#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ 1638 (2 << FShft (LCD_PBS)) 1639 1640#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ 1641#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ 1642#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ 1643#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ 1644#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ 1645#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ 1646#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ 1647#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ 1648#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ 1649#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ 1650#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ 1651#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ 1652#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ 1653#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ 1654#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ 1655#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ 1656 /* (Alternative) */ 1657 1658#define LCCR0_LEN 0x00000001 /* LCD ENable */ 1659#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ 1660#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 1661#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ 1662#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ 1663 /* Select */ 1664#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ 1665#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ 1666#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ 1667 /* interrupt Mask (disable) */ 1668#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ 1669 /* interrupt Mask (disable) */ 1670#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ 1671 /* IUU, OOL, OUL, OOU, and OUU) */ 1672 /* interrupt Mask (disable) */ 1673#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ 1674#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ 1675#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ 1676#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ 1677#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ 1678#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ 1679#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ 1680 /* display mode) */ 1681#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ 1682 /* display */ 1683#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ 1684 /* display */ 1685#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ 1686 /* [Tmem] */ 1687#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ 1688 /* [0..510 Tcpu] */ \ 1689 ((Tcpu)/2 << FShft (LCCR0_PDD)) 1690 1691#define LCSR_LDD 0x00000001 /* LCD Disable Done */ 1692#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ 1693#define LCSR_BER 0x00000004 /* Bus ERror */ 1694#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ 1695#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ 1696 /* panel */ 1697#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ 1698 /* panel */ 1699#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ 1700 /* panel */ 1701#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ 1702 /* panel */ 1703#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ 1704 /* panel */ 1705#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ 1706 /* panel */ 1707#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ 1708 /* panel */ 1709#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ 1710 /* panel */ 1711 1712#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ 1713#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ 1714 (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) 1715#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ 1716 /* pulse Width - 1 [Tpix] (L_LCLK) */ 1717#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ 1718 /* pulse Width [1..64 Tpix] */ \ 1719 (((Tpix) - 1) << FShft (LCCR1_HSW)) 1720#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ 1721 /* count - 1 [Tpix] */ 1722#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ 1723 /* [1..256 Tpix] */ \ 1724 (((Tpix) - 1) << FShft (LCCR1_ELW)) 1725#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ 1726 /* Wait count - 1 [Tpix] */ 1727#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ 1728 /* [1..256 Tpix] */ \ 1729 (((Tpix) - 1) << FShft (LCCR1_BLW)) 1730 1731#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ 1732#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ 1733 (((Line) - 1) << FShft (LCCR2_LPP)) 1734#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ 1735 /* Width - 1 [Tln] (L_FCLK) */ 1736#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ 1737 /* Width [1..64 Tln] */ \ 1738 (((Tln) - 1) << FShft (LCCR2_VSW)) 1739#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ 1740 /* count [Tln] */ 1741#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ 1742 /* [0..255 Tln] */ \ 1743 ((Tln) << FShft (LCCR2_EFW)) 1744#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ 1745 /* Wait count [Tln] */ 1746#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ 1747 /* [0..255 Tln] */ \ 1748 ((Tln) << FShft (LCCR2_BFW)) 1749 1750#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ 1751 /* [1..255] (L_PCLK) */ 1752 /* fpix = fcpu/(2*(PCD + 2)) */ 1753 /* Tpix = 2*(PCD + 2)*Tcpu */ 1754#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ 1755 (((Div) - 4)/2 << FShft (LCCR3_PCD)) 1756 /* fpix = fcpu/(2*Floor (Div/2)) */ 1757 /* Tpix = 2*Floor (Div/2)*Tcpu */ 1758#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ 1759 (((Div) - 3)/2 << FShft (LCCR3_PCD)) 1760 /* fpix = fcpu/(2*Ceil (Div/2)) */ 1761 /* Tpix = 2*Ceil (Div/2)*Tcpu */ 1762#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ 1763 /* [Tln] (L_BIAS) */ 1764#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ 1765 (((Div) - 2)/2 << FShft (LCCR3_ACB)) 1766 /* fac = fln/(2*Floor (Div/2)) */ 1767 /* Tac = 2*Floor (Div/2)*Tln */ 1768#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ 1769 (((Div) - 1)/2 << FShft (LCCR3_ACB)) 1770 /* fac = fln/(2*Ceil (Div/2)) */ 1771 /* Tac = 2*Ceil (Div/2)*Tln */ 1772#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ 1773 /* Interrupt */ 1774#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ 1775 /* Off */ \ 1776 (0 << FShft (LCCR3_API)) 1777#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ 1778 /* [1..15] */ \ 1779 ((Trans) << FShft (LCCR3_API)) 1780#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ 1781 /* Polarity (L_FCLK) */ 1782#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ 1783 /* active High */ 1784#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ 1785 /* active Low */ 1786#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ 1787 /* pulse Polarity (L_LCLK) */ 1788#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ 1789 /* pulse active High */ 1790#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ 1791 /* pulse active Low */ 1792#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ 1793#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ 1794#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ 1795#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ 1796 /* active display mode) */ 1797#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ 1798#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ 1799