linux/arch/arm64/Kconfig
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   1# SPDX-License-Identifier: GPL-2.0-only
   2config ARM64
   3        def_bool y
   4        select ACPI_CCA_REQUIRED if ACPI
   5        select ACPI_GENERIC_GSI if ACPI
   6        select ACPI_GTDT if ACPI
   7        select ACPI_IORT if ACPI
   8        select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   9        select ACPI_MCFG if (ACPI && PCI)
  10        select ACPI_SPCR_TABLE if ACPI
  11        select ACPI_PPTT if ACPI
  12        select ARCH_HAS_DEBUG_WX
  13        select ARCH_BINFMT_ELF_STATE
  14        select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
  15        select ARCH_ENABLE_MEMORY_HOTPLUG
  16        select ARCH_ENABLE_MEMORY_HOTREMOVE
  17        select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
  18        select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
  19        select ARCH_HAS_CACHE_LINE_SIZE
  20        select ARCH_HAS_DEBUG_VIRTUAL
  21        select ARCH_HAS_DEBUG_VM_PGTABLE
  22        select ARCH_HAS_DMA_PREP_COHERENT
  23        select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
  24        select ARCH_HAS_FAST_MULTIPLIER
  25        select ARCH_HAS_FORTIFY_SOURCE
  26        select ARCH_HAS_GCOV_PROFILE_ALL
  27        select ARCH_HAS_GIGANTIC_PAGE
  28        select ARCH_HAS_KCOV
  29        select ARCH_HAS_KEEPINITRD
  30        select ARCH_HAS_MEMBARRIER_SYNC_CORE
  31        select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
  32        select ARCH_HAS_PTE_DEVMAP
  33        select ARCH_HAS_PTE_SPECIAL
  34        select ARCH_HAS_SETUP_DMA_OPS
  35        select ARCH_HAS_SET_DIRECT_MAP
  36        select ARCH_HAS_SET_MEMORY
  37        select ARCH_STACKWALK
  38        select ARCH_HAS_STRICT_KERNEL_RWX
  39        select ARCH_HAS_STRICT_MODULE_RWX
  40        select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  41        select ARCH_HAS_SYNC_DMA_FOR_CPU
  42        select ARCH_HAS_SYSCALL_WRAPPER
  43        select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
  44        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  45        select ARCH_HAS_ZONE_DMA_SET if EXPERT
  46        select ARCH_HAVE_ELF_PROT
  47        select ARCH_HAVE_NMI_SAFE_CMPXCHG
  48        select ARCH_INLINE_READ_LOCK if !PREEMPTION
  49        select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
  50        select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
  51        select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
  52        select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
  53        select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
  54        select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
  55        select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
  56        select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
  57        select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
  58        select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
  59        select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
  60        select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
  61        select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
  62        select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
  63        select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
  64        select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
  65        select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
  66        select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
  67        select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
  68        select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
  69        select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
  70        select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
  71        select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
  72        select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
  73        select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
  74        select ARCH_KEEP_MEMBLOCK
  75        select ARCH_USE_CMPXCHG_LOCKREF
  76        select ARCH_USE_GNU_PROPERTY
  77        select ARCH_USE_MEMTEST
  78        select ARCH_USE_QUEUED_RWLOCKS
  79        select ARCH_USE_QUEUED_SPINLOCKS
  80        select ARCH_USE_SYM_ANNOTATIONS
  81        select ARCH_SUPPORTS_DEBUG_PAGEALLOC
  82        select ARCH_SUPPORTS_HUGETLBFS
  83        select ARCH_SUPPORTS_MEMORY_FAILURE
  84        select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
  85        select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
  86        select ARCH_SUPPORTS_LTO_CLANG_THIN
  87        select ARCH_SUPPORTS_CFI_CLANG
  88        select ARCH_SUPPORTS_ATOMIC_RMW
  89        select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
  90        select ARCH_SUPPORTS_NUMA_BALANCING
  91        select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
  92        select ARCH_WANT_DEFAULT_BPF_JIT
  93        select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
  94        select ARCH_WANT_FRAME_POINTERS
  95        select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
  96        select ARCH_WANT_LD_ORPHAN_WARN
  97        select ARCH_WANTS_NO_INSTR
  98        select ARCH_HAS_UBSAN_SANITIZE_ALL
  99        select ARM_AMBA
 100        select ARM_ARCH_TIMER
 101        select ARM_GIC
 102        select AUDIT_ARCH_COMPAT_GENERIC
 103        select ARM_GIC_V2M if PCI
 104        select ARM_GIC_V3
 105        select ARM_GIC_V3_ITS if PCI
 106        select ARM_PSCI_FW
 107        select BUILDTIME_TABLE_SORT
 108        select CLONE_BACKWARDS
 109        select COMMON_CLK
 110        select CPU_PM if (SUSPEND || CPU_IDLE)
 111        select CRC32
 112        select DCACHE_WORD_ACCESS
 113        select DMA_DIRECT_REMAP
 114        select EDAC_SUPPORT
 115        select FRAME_POINTER
 116        select GENERIC_ALLOCATOR
 117        select GENERIC_ARCH_TOPOLOGY
 118        select GENERIC_CLOCKEVENTS_BROADCAST
 119        select GENERIC_CPU_AUTOPROBE
 120        select GENERIC_CPU_VULNERABILITIES
 121        select GENERIC_EARLY_IOREMAP
 122        select GENERIC_FIND_FIRST_BIT
 123        select GENERIC_IDLE_POLL_SETUP
 124        select GENERIC_IRQ_IPI
 125        select GENERIC_IRQ_PROBE
 126        select GENERIC_IRQ_SHOW
 127        select GENERIC_IRQ_SHOW_LEVEL
 128        select GENERIC_LIB_DEVMEM_IS_ALLOWED
 129        select GENERIC_PCI_IOMAP
 130        select GENERIC_PTDUMP
 131        select GENERIC_SCHED_CLOCK
 132        select GENERIC_SMP_IDLE_THREAD
 133        select GENERIC_TIME_VSYSCALL
 134        select GENERIC_GETTIMEOFDAY
 135        select GENERIC_VDSO_TIME_NS
 136        select HANDLE_DOMAIN_IRQ
 137        select HARDIRQS_SW_RESEND
 138        select HAVE_MOVE_PMD
 139        select HAVE_MOVE_PUD
 140        select HAVE_PCI
 141        select HAVE_ACPI_APEI if (ACPI && EFI)
 142        select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 143        select HAVE_ARCH_AUDITSYSCALL
 144        select HAVE_ARCH_BITREVERSE
 145        select HAVE_ARCH_COMPILER_H
 146        select HAVE_ARCH_HUGE_VMAP
 147        select HAVE_ARCH_JUMP_LABEL
 148        select HAVE_ARCH_JUMP_LABEL_RELATIVE
 149        select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 150        select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
 151        select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
 152        select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
 153        select HAVE_ARCH_KFENCE
 154        select HAVE_ARCH_KGDB
 155        select HAVE_ARCH_MMAP_RND_BITS
 156        select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 157        select HAVE_ARCH_PFN_VALID
 158        select HAVE_ARCH_PREL32_RELOCATIONS
 159        select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
 160        select HAVE_ARCH_SECCOMP_FILTER
 161        select HAVE_ARCH_STACKLEAK
 162        select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 163        select HAVE_ARCH_TRACEHOOK
 164        select HAVE_ARCH_TRANSPARENT_HUGEPAGE
 165        select HAVE_ARCH_VMAP_STACK
 166        select HAVE_ARM_SMCCC
 167        select HAVE_ASM_MODVERSIONS
 168        select HAVE_EBPF_JIT
 169        select HAVE_C_RECORDMCOUNT
 170        select HAVE_CMPXCHG_DOUBLE
 171        select HAVE_CMPXCHG_LOCAL
 172        select HAVE_CONTEXT_TRACKING
 173        select HAVE_DEBUG_KMEMLEAK
 174        select HAVE_DMA_CONTIGUOUS
 175        select HAVE_DYNAMIC_FTRACE
 176        select HAVE_DYNAMIC_FTRACE_WITH_REGS \
 177                if $(cc-option,-fpatchable-function-entry=2)
 178        select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
 179                if DYNAMIC_FTRACE_WITH_REGS
 180        select HAVE_EFFICIENT_UNALIGNED_ACCESS
 181        select HAVE_FAST_GUP
 182        select HAVE_FTRACE_MCOUNT_RECORD
 183        select HAVE_FUNCTION_TRACER
 184        select HAVE_FUNCTION_ERROR_INJECTION
 185        select HAVE_FUNCTION_GRAPH_TRACER
 186        select HAVE_GCC_PLUGINS
 187        select HAVE_HW_BREAKPOINT if PERF_EVENTS
 188        select HAVE_IRQ_TIME_ACCOUNTING
 189        select HAVE_NMI
 190        select HAVE_PATA_PLATFORM
 191        select HAVE_PERF_EVENTS
 192        select HAVE_PERF_REGS
 193        select HAVE_PERF_USER_STACK_DUMP
 194        select HAVE_REGS_AND_STACK_ACCESS_API
 195        select HAVE_FUNCTION_ARG_ACCESS_API
 196        select HAVE_FUTEX_CMPXCHG if FUTEX
 197        select MMU_GATHER_RCU_TABLE_FREE
 198        select HAVE_RSEQ
 199        select HAVE_STACKPROTECTOR
 200        select HAVE_SYSCALL_TRACEPOINTS
 201        select HAVE_KPROBES
 202        select HAVE_KRETPROBES
 203        select HAVE_GENERIC_VDSO
 204        select IOMMU_DMA if IOMMU_SUPPORT
 205        select IRQ_DOMAIN
 206        select IRQ_FORCED_THREADING
 207        select KASAN_VMALLOC if KASAN_GENERIC
 208        select MODULES_USE_ELF_RELA
 209        select NEED_DMA_MAP_STATE
 210        select NEED_SG_DMA_LENGTH
 211        select OF
 212        select OF_EARLY_FLATTREE
 213        select PCI_DOMAINS_GENERIC if PCI
 214        select PCI_ECAM if (ACPI && PCI)
 215        select PCI_SYSCALL if PCI
 216        select POWER_RESET
 217        select POWER_SUPPLY
 218        select SPARSE_IRQ
 219        select SWIOTLB
 220        select SYSCTL_EXCEPTION_TRACE
 221        select THREAD_INFO_IN_TASK
 222        select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
 223        select TRACE_IRQFLAGS_SUPPORT
 224        help
 225          ARM 64-bit (AArch64) Linux support.
 226
 227config 64BIT
 228        def_bool y
 229
 230config MMU
 231        def_bool y
 232
 233config ARM64_PAGE_SHIFT
 234        int
 235        default 16 if ARM64_64K_PAGES
 236        default 14 if ARM64_16K_PAGES
 237        default 12
 238
 239config ARM64_CONT_PTE_SHIFT
 240        int
 241        default 5 if ARM64_64K_PAGES
 242        default 7 if ARM64_16K_PAGES
 243        default 4
 244
 245config ARM64_CONT_PMD_SHIFT
 246        int
 247        default 5 if ARM64_64K_PAGES
 248        default 5 if ARM64_16K_PAGES
 249        default 4
 250
 251config ARCH_MMAP_RND_BITS_MIN
 252       default 14 if ARM64_64K_PAGES
 253       default 16 if ARM64_16K_PAGES
 254       default 18
 255
 256# max bits determined by the following formula:
 257#  VA_BITS - PAGE_SHIFT - 3
 258config ARCH_MMAP_RND_BITS_MAX
 259       default 19 if ARM64_VA_BITS=36
 260       default 24 if ARM64_VA_BITS=39
 261       default 27 if ARM64_VA_BITS=42
 262       default 30 if ARM64_VA_BITS=47
 263       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 264       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 265       default 33 if ARM64_VA_BITS=48
 266       default 14 if ARM64_64K_PAGES
 267       default 16 if ARM64_16K_PAGES
 268       default 18
 269
 270config ARCH_MMAP_RND_COMPAT_BITS_MIN
 271       default 7 if ARM64_64K_PAGES
 272       default 9 if ARM64_16K_PAGES
 273       default 11
 274
 275config ARCH_MMAP_RND_COMPAT_BITS_MAX
 276       default 16
 277
 278config NO_IOPORT_MAP
 279        def_bool y if !PCI
 280
 281config STACKTRACE_SUPPORT
 282        def_bool y
 283
 284config ILLEGAL_POINTER_VALUE
 285        hex
 286        default 0xdead000000000000
 287
 288config LOCKDEP_SUPPORT
 289        def_bool y
 290
 291config GENERIC_BUG
 292        def_bool y
 293        depends on BUG
 294
 295config GENERIC_BUG_RELATIVE_POINTERS
 296        def_bool y
 297        depends on GENERIC_BUG
 298
 299config GENERIC_HWEIGHT
 300        def_bool y
 301
 302config GENERIC_CSUM
 303        def_bool y
 304
 305config GENERIC_CALIBRATE_DELAY
 306        def_bool y
 307
 308config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
 309        def_bool y
 310
 311config SMP
 312        def_bool y
 313
 314config KERNEL_MODE_NEON
 315        def_bool y
 316
 317config FIX_EARLYCON_MEM
 318        def_bool y
 319
 320config PGTABLE_LEVELS
 321        int
 322        default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 323        default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 324        default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
 325        default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 326        default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 327        default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 328
 329config ARCH_SUPPORTS_UPROBES
 330        def_bool y
 331
 332config ARCH_PROC_KCORE_TEXT
 333        def_bool y
 334
 335config BROKEN_GAS_INST
 336        def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
 337
 338config KASAN_SHADOW_OFFSET
 339        hex
 340        depends on KASAN_GENERIC || KASAN_SW_TAGS
 341        default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
 342        default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
 343        default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
 344        default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
 345        default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
 346        default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
 347        default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
 348        default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
 349        default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
 350        default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
 351        default 0xffffffffffffffff
 352
 353source "arch/arm64/Kconfig.platforms"
 354
 355menu "Kernel Features"
 356
 357menu "ARM errata workarounds via the alternatives framework"
 358
 359config ARM64_WORKAROUND_CLEAN_CACHE
 360        bool
 361
 362config ARM64_ERRATUM_826319
 363        bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 364        default y
 365        select ARM64_WORKAROUND_CLEAN_CACHE
 366        help
 367          This option adds an alternative code sequence to work around ARM
 368          erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 369          AXI master interface and an L2 cache.
 370
 371          If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 372          and is unable to accept a certain write via this interface, it will
 373          not progress on read data presented on the read data channel and the
 374          system can deadlock.
 375
 376          The workaround promotes data cache clean instructions to
 377          data cache clean-and-invalidate.
 378          Please note that this does not necessarily enable the workaround,
 379          as it depends on the alternative framework, which will only patch
 380          the kernel if an affected CPU is detected.
 381
 382          If unsure, say Y.
 383
 384config ARM64_ERRATUM_827319
 385        bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 386        default y
 387        select ARM64_WORKAROUND_CLEAN_CACHE
 388        help
 389          This option adds an alternative code sequence to work around ARM
 390          erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 391          master interface and an L2 cache.
 392
 393          Under certain conditions this erratum can cause a clean line eviction
 394          to occur at the same time as another transaction to the same address
 395          on the AMBA 5 CHI interface, which can cause data corruption if the
 396          interconnect reorders the two transactions.
 397
 398          The workaround promotes data cache clean instructions to
 399          data cache clean-and-invalidate.
 400          Please note that this does not necessarily enable the workaround,
 401          as it depends on the alternative framework, which will only patch
 402          the kernel if an affected CPU is detected.
 403
 404          If unsure, say Y.
 405
 406config ARM64_ERRATUM_824069
 407        bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 408        default y
 409        select ARM64_WORKAROUND_CLEAN_CACHE
 410        help
 411          This option adds an alternative code sequence to work around ARM
 412          erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 413          to a coherent interconnect.
 414
 415          If a Cortex-A53 processor is executing a store or prefetch for
 416          write instruction at the same time as a processor in another
 417          cluster is executing a cache maintenance operation to the same
 418          address, then this erratum might cause a clean cache line to be
 419          incorrectly marked as dirty.
 420
 421          The workaround promotes data cache clean instructions to
 422          data cache clean-and-invalidate.
 423          Please note that this option does not necessarily enable the
 424          workaround, as it depends on the alternative framework, which will
 425          only patch the kernel if an affected CPU is detected.
 426
 427          If unsure, say Y.
 428
 429config ARM64_ERRATUM_819472
 430        bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 431        default y
 432        select ARM64_WORKAROUND_CLEAN_CACHE
 433        help
 434          This option adds an alternative code sequence to work around ARM
 435          erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 436          present when it is connected to a coherent interconnect.
 437
 438          If the processor is executing a load and store exclusive sequence at
 439          the same time as a processor in another cluster is executing a cache
 440          maintenance operation to the same address, then this erratum might
 441          cause data corruption.
 442
 443          The workaround promotes data cache clean instructions to
 444          data cache clean-and-invalidate.
 445          Please note that this does not necessarily enable the workaround,
 446          as it depends on the alternative framework, which will only patch
 447          the kernel if an affected CPU is detected.
 448
 449          If unsure, say Y.
 450
 451config ARM64_ERRATUM_832075
 452        bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 453        default y
 454        help
 455          This option adds an alternative code sequence to work around ARM
 456          erratum 832075 on Cortex-A57 parts up to r1p2.
 457
 458          Affected Cortex-A57 parts might deadlock when exclusive load/store
 459          instructions to Write-Back memory are mixed with Device loads.
 460
 461          The workaround is to promote device loads to use Load-Acquire
 462          semantics.
 463          Please note that this does not necessarily enable the workaround,
 464          as it depends on the alternative framework, which will only patch
 465          the kernel if an affected CPU is detected.
 466
 467          If unsure, say Y.
 468
 469config ARM64_ERRATUM_834220
 470        bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 471        depends on KVM
 472        default y
 473        help
 474          This option adds an alternative code sequence to work around ARM
 475          erratum 834220 on Cortex-A57 parts up to r1p2.
 476
 477          Affected Cortex-A57 parts might report a Stage 2 translation
 478          fault as the result of a Stage 1 fault for load crossing a
 479          page boundary when there is a permission or device memory
 480          alignment fault at Stage 1 and a translation fault at Stage 2.
 481
 482          The workaround is to verify that the Stage 1 translation
 483          doesn't generate a fault before handling the Stage 2 fault.
 484          Please note that this does not necessarily enable the workaround,
 485          as it depends on the alternative framework, which will only patch
 486          the kernel if an affected CPU is detected.
 487
 488          If unsure, say Y.
 489
 490config ARM64_ERRATUM_845719
 491        bool "Cortex-A53: 845719: a load might read incorrect data"
 492        depends on COMPAT
 493        default y
 494        help
 495          This option adds an alternative code sequence to work around ARM
 496          erratum 845719 on Cortex-A53 parts up to r0p4.
 497
 498          When running a compat (AArch32) userspace on an affected Cortex-A53
 499          part, a load at EL0 from a virtual address that matches the bottom 32
 500          bits of the virtual address used by a recent load at (AArch64) EL1
 501          might return incorrect data.
 502
 503          The workaround is to write the contextidr_el1 register on exception
 504          return to a 32-bit task.
 505          Please note that this does not necessarily enable the workaround,
 506          as it depends on the alternative framework, which will only patch
 507          the kernel if an affected CPU is detected.
 508
 509          If unsure, say Y.
 510
 511config ARM64_ERRATUM_843419
 512        bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 513        default y
 514        select ARM64_MODULE_PLTS if MODULES
 515        help
 516          This option links the kernel with '--fix-cortex-a53-843419' and
 517          enables PLT support to replace certain ADRP instructions, which can
 518          cause subsequent memory accesses to use an incorrect address on
 519          Cortex-A53 parts up to r0p4.
 520
 521          If unsure, say Y.
 522
 523config ARM64_LD_HAS_FIX_ERRATUM_843419
 524        def_bool $(ld-option,--fix-cortex-a53-843419)
 525
 526config ARM64_ERRATUM_1024718
 527        bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
 528        default y
 529        help
 530          This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
 531
 532          Affected Cortex-A55 cores (all revisions) could cause incorrect
 533          update of the hardware dirty bit when the DBM/AP bits are updated
 534          without a break-before-make. The workaround is to disable the usage
 535          of hardware DBM locally on the affected cores. CPUs not affected by
 536          this erratum will continue to use the feature.
 537
 538          If unsure, say Y.
 539
 540config ARM64_ERRATUM_1418040
 541        bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
 542        default y
 543        depends on COMPAT
 544        help
 545          This option adds a workaround for ARM Cortex-A76/Neoverse-N1
 546          errata 1188873 and 1418040.
 547
 548          Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
 549          cause register corruption when accessing the timer registers
 550          from AArch32 userspace.
 551
 552          If unsure, say Y.
 553
 554config ARM64_WORKAROUND_SPECULATIVE_AT
 555        bool
 556
 557config ARM64_ERRATUM_1165522
 558        bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 559        default y
 560        select ARM64_WORKAROUND_SPECULATIVE_AT
 561        help
 562          This option adds a workaround for ARM Cortex-A76 erratum 1165522.
 563
 564          Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
 565          corrupted TLBs by speculating an AT instruction during a guest
 566          context switch.
 567
 568          If unsure, say Y.
 569
 570config ARM64_ERRATUM_1319367
 571        bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 572        default y
 573        select ARM64_WORKAROUND_SPECULATIVE_AT
 574        help
 575          This option adds work arounds for ARM Cortex-A57 erratum 1319537
 576          and A72 erratum 1319367
 577
 578          Cortex-A57 and A72 cores could end-up with corrupted TLBs by
 579          speculating an AT instruction during a guest context switch.
 580
 581          If unsure, say Y.
 582
 583config ARM64_ERRATUM_1530923
 584        bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 585        default y
 586        select ARM64_WORKAROUND_SPECULATIVE_AT
 587        help
 588          This option adds a workaround for ARM Cortex-A55 erratum 1530923.
 589
 590          Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
 591          corrupted TLBs by speculating an AT instruction during a guest
 592          context switch.
 593
 594          If unsure, say Y.
 595
 596config ARM64_WORKAROUND_REPEAT_TLBI
 597        bool
 598
 599config ARM64_ERRATUM_1286807
 600        bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
 601        default y
 602        select ARM64_WORKAROUND_REPEAT_TLBI
 603        help
 604          This option adds a workaround for ARM Cortex-A76 erratum 1286807.
 605
 606          On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
 607          address for a cacheable mapping of a location is being
 608          accessed by a core while another core is remapping the virtual
 609          address to a new physical page using the recommended
 610          break-before-make sequence, then under very rare circumstances
 611          TLBI+DSB completes before a read using the translation being
 612          invalidated has been observed by other observers. The
 613          workaround repeats the TLBI+DSB operation.
 614
 615config ARM64_ERRATUM_1463225
 616        bool "Cortex-A76: Software Step might prevent interrupt recognition"
 617        default y
 618        help
 619          This option adds a workaround for Arm Cortex-A76 erratum 1463225.
 620
 621          On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
 622          of a system call instruction (SVC) can prevent recognition of
 623          subsequent interrupts when software stepping is disabled in the
 624          exception handler of the system call and either kernel debugging
 625          is enabled or VHE is in use.
 626
 627          Work around the erratum by triggering a dummy step exception
 628          when handling a system call from a task that is being stepped
 629          in a VHE configuration of the kernel.
 630
 631          If unsure, say Y.
 632
 633config ARM64_ERRATUM_1542419
 634        bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
 635        default y
 636        help
 637          This option adds a workaround for ARM Neoverse-N1 erratum
 638          1542419.
 639
 640          Affected Neoverse-N1 cores could execute a stale instruction when
 641          modified by another CPU. The workaround depends on a firmware
 642          counterpart.
 643
 644          Workaround the issue by hiding the DIC feature from EL0. This
 645          forces user-space to perform cache maintenance.
 646
 647          If unsure, say Y.
 648
 649config ARM64_ERRATUM_1508412
 650        bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
 651        default y
 652        help
 653          This option adds a workaround for Arm Cortex-A77 erratum 1508412.
 654
 655          Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
 656          of a store-exclusive or read of PAR_EL1 and a load with device or
 657          non-cacheable memory attributes. The workaround depends on a firmware
 658          counterpart.
 659
 660          KVM guests must also have the workaround implemented or they can
 661          deadlock the system.
 662
 663          Work around the issue by inserting DMB SY barriers around PAR_EL1
 664          register reads and warning KVM users. The DMB barrier is sufficient
 665          to prevent a speculative PAR_EL1 read.
 666
 667          If unsure, say Y.
 668
 669config CAVIUM_ERRATUM_22375
 670        bool "Cavium erratum 22375, 24313"
 671        default y
 672        help
 673          Enable workaround for errata 22375 and 24313.
 674
 675          This implements two gicv3-its errata workarounds for ThunderX. Both
 676          with a small impact affecting only ITS table allocation.
 677
 678            erratum 22375: only alloc 8MB table size
 679            erratum 24313: ignore memory access type
 680
 681          The fixes are in ITS initialization and basically ignore memory access
 682          type and table size provided by the TYPER and BASER registers.
 683
 684          If unsure, say Y.
 685
 686config CAVIUM_ERRATUM_23144
 687        bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
 688        depends on NUMA
 689        default y
 690        help
 691          ITS SYNC command hang for cross node io and collections/cpu mapping.
 692
 693          If unsure, say Y.
 694
 695config CAVIUM_ERRATUM_23154
 696        bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 697        default y
 698        help
 699          The gicv3 of ThunderX requires a modified version for
 700          reading the IAR status to ensure data synchronization
 701          (access to icc_iar1_el1 is not sync'ed before and after).
 702
 703          If unsure, say Y.
 704
 705config CAVIUM_ERRATUM_27456
 706        bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 707        default y
 708        help
 709          On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
 710          instructions may cause the icache to become corrupted if it
 711          contains data for a non-current ASID.  The fix is to
 712          invalidate the icache when changing the mm context.
 713
 714          If unsure, say Y.
 715
 716config CAVIUM_ERRATUM_30115
 717        bool "Cavium erratum 30115: Guest may disable interrupts in host"
 718        default y
 719        help
 720          On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
 721          1.2, and T83 Pass 1.0, KVM guest execution may disable
 722          interrupts in host. Trapping both GICv3 group-0 and group-1
 723          accesses sidesteps the issue.
 724
 725          If unsure, say Y.
 726
 727config CAVIUM_TX2_ERRATUM_219
 728        bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
 729        default y
 730        help
 731          On Cavium ThunderX2, a load, store or prefetch instruction between a
 732          TTBR update and the corresponding context synchronizing operation can
 733          cause a spurious Data Abort to be delivered to any hardware thread in
 734          the CPU core.
 735
 736          Work around the issue by avoiding the problematic code sequence and
 737          trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
 738          trap handler performs the corresponding register access, skips the
 739          instruction and ensures context synchronization by virtue of the
 740          exception return.
 741
 742          If unsure, say Y.
 743
 744config FUJITSU_ERRATUM_010001
 745        bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
 746        default y
 747        help
 748          This option adds a workaround for Fujitsu-A64FX erratum E#010001.
 749          On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
 750          accesses may cause undefined fault (Data abort, DFSC=0b111111).
 751          This fault occurs under a specific hardware condition when a
 752          load/store instruction performs an address translation using:
 753          case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
 754          case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
 755          case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
 756          case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
 757
 758          The workaround is to ensure these bits are clear in TCR_ELx.
 759          The workaround only affects the Fujitsu-A64FX.
 760
 761          If unsure, say Y.
 762
 763config HISILICON_ERRATUM_161600802
 764        bool "Hip07 161600802: Erroneous redistributor VLPI base"
 765        default y
 766        help
 767          The HiSilicon Hip07 SoC uses the wrong redistributor base
 768          when issued ITS commands such as VMOVP and VMAPP, and requires
 769          a 128kB offset to be applied to the target address in this commands.
 770
 771          If unsure, say Y.
 772
 773config QCOM_FALKOR_ERRATUM_1003
 774        bool "Falkor E1003: Incorrect translation due to ASID change"
 775        default y
 776        help
 777          On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
 778          and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
 779          in TTBR1_EL1, this situation only occurs in the entry trampoline and
 780          then only for entries in the walk cache, since the leaf translation
 781          is unchanged. Work around the erratum by invalidating the walk cache
 782          entries for the trampoline before entering the kernel proper.
 783
 784config QCOM_FALKOR_ERRATUM_1009
 785        bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
 786        default y
 787        select ARM64_WORKAROUND_REPEAT_TLBI
 788        help
 789          On Falkor v1, the CPU may prematurely complete a DSB following a
 790          TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
 791          one more time to fix the issue.
 792
 793          If unsure, say Y.
 794
 795config QCOM_QDF2400_ERRATUM_0065
 796        bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
 797        default y
 798        help
 799          On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
 800          ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
 801          been indicated as 16Bytes (0xf), not 8Bytes (0x7).
 802
 803          If unsure, say Y.
 804
 805config QCOM_FALKOR_ERRATUM_E1041
 806        bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
 807        default y
 808        help
 809          Falkor CPU may speculatively fetch instructions from an improper
 810          memory location when MMU translation is changed from SCTLR_ELn[M]=1
 811          to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
 812
 813          If unsure, say Y.
 814
 815config NVIDIA_CARMEL_CNP_ERRATUM
 816        bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
 817        default y
 818        help
 819          If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
 820          invalidate shared TLB entries installed by a different core, as it would
 821          on standard ARM cores.
 822
 823          If unsure, say Y.
 824
 825config SOCIONEXT_SYNQUACER_PREITS
 826        bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
 827        default y
 828        help
 829          Socionext Synquacer SoCs implement a separate h/w block to generate
 830          MSI doorbell writes with non-zero values for the device ID.
 831
 832          If unsure, say Y.
 833
 834endmenu
 835
 836
 837choice
 838        prompt "Page size"
 839        default ARM64_4K_PAGES
 840        help
 841          Page size (translation granule) configuration.
 842
 843config ARM64_4K_PAGES
 844        bool "4KB"
 845        help
 846          This feature enables 4KB pages support.
 847
 848config ARM64_16K_PAGES
 849        bool "16KB"
 850        help
 851          The system will use 16KB pages support. AArch32 emulation
 852          requires applications compiled with 16K (or a multiple of 16K)
 853          aligned segments.
 854
 855config ARM64_64K_PAGES
 856        bool "64KB"
 857        help
 858          This feature enables 64KB pages support (4KB by default)
 859          allowing only two levels of page tables and faster TLB
 860          look-up. AArch32 emulation requires applications compiled
 861          with 64K aligned segments.
 862
 863endchoice
 864
 865choice
 866        prompt "Virtual address space size"
 867        default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 868        default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 869        default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 870        help
 871          Allows choosing one of multiple possible virtual address
 872          space sizes. The level of translation table is determined by
 873          a combination of page size and virtual address space size.
 874
 875config ARM64_VA_BITS_36
 876        bool "36-bit" if EXPERT
 877        depends on ARM64_16K_PAGES
 878
 879config ARM64_VA_BITS_39
 880        bool "39-bit"
 881        depends on ARM64_4K_PAGES
 882
 883config ARM64_VA_BITS_42
 884        bool "42-bit"
 885        depends on ARM64_64K_PAGES
 886
 887config ARM64_VA_BITS_47
 888        bool "47-bit"
 889        depends on ARM64_16K_PAGES
 890
 891config ARM64_VA_BITS_48
 892        bool "48-bit"
 893
 894config ARM64_VA_BITS_52
 895        bool "52-bit"
 896        depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
 897        help
 898          Enable 52-bit virtual addressing for userspace when explicitly
 899          requested via a hint to mmap(). The kernel will also use 52-bit
 900          virtual addresses for its own mappings (provided HW support for
 901          this feature is available, otherwise it reverts to 48-bit).
 902
 903          NOTE: Enabling 52-bit virtual addressing in conjunction with
 904          ARMv8.3 Pointer Authentication will result in the PAC being
 905          reduced from 7 bits to 3 bits, which may have a significant
 906          impact on its susceptibility to brute-force attacks.
 907
 908          If unsure, select 48-bit virtual addressing instead.
 909
 910endchoice
 911
 912config ARM64_FORCE_52BIT
 913        bool "Force 52-bit virtual addresses for userspace"
 914        depends on ARM64_VA_BITS_52 && EXPERT
 915        help
 916          For systems with 52-bit userspace VAs enabled, the kernel will attempt
 917          to maintain compatibility with older software by providing 48-bit VAs
 918          unless a hint is supplied to mmap.
 919
 920          This configuration option disables the 48-bit compatibility logic, and
 921          forces all userspace addresses to be 52-bit on HW that supports it. One
 922          should only enable this configuration option for stress testing userspace
 923          memory management code. If unsure say N here.
 924
 925config ARM64_VA_BITS
 926        int
 927        default 36 if ARM64_VA_BITS_36
 928        default 39 if ARM64_VA_BITS_39
 929        default 42 if ARM64_VA_BITS_42
 930        default 47 if ARM64_VA_BITS_47
 931        default 48 if ARM64_VA_BITS_48
 932        default 52 if ARM64_VA_BITS_52
 933
 934choice
 935        prompt "Physical address space size"
 936        default ARM64_PA_BITS_48
 937        help
 938          Choose the maximum physical address range that the kernel will
 939          support.
 940
 941config ARM64_PA_BITS_48
 942        bool "48-bit"
 943
 944config ARM64_PA_BITS_52
 945        bool "52-bit (ARMv8.2)"
 946        depends on ARM64_64K_PAGES
 947        depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
 948        help
 949          Enable support for a 52-bit physical address space, introduced as
 950          part of the ARMv8.2-LPA extension.
 951
 952          With this enabled, the kernel will also continue to work on CPUs that
 953          do not support ARMv8.2-LPA, but with some added memory overhead (and
 954          minor performance overhead).
 955
 956endchoice
 957
 958config ARM64_PA_BITS
 959        int
 960        default 48 if ARM64_PA_BITS_48
 961        default 52 if ARM64_PA_BITS_52
 962
 963choice
 964        prompt "Endianness"
 965        default CPU_LITTLE_ENDIAN
 966        help
 967          Select the endianness of data accesses performed by the CPU. Userspace
 968          applications will need to be compiled and linked for the endianness
 969          that is selected here.
 970
 971config CPU_BIG_ENDIAN
 972        bool "Build big-endian kernel"
 973        depends on !LD_IS_LLD || LLD_VERSION >= 130000
 974        help
 975          Say Y if you plan on running a kernel with a big-endian userspace.
 976
 977config CPU_LITTLE_ENDIAN
 978        bool "Build little-endian kernel"
 979        help
 980          Say Y if you plan on running a kernel with a little-endian userspace.
 981          This is usually the case for distributions targeting arm64.
 982
 983endchoice
 984
 985config SCHED_MC
 986        bool "Multi-core scheduler support"
 987        help
 988          Multi-core scheduler support improves the CPU scheduler's decision
 989          making when dealing with multi-core CPU chips at a cost of slightly
 990          increased overhead in some places. If unsure say N here.
 991
 992config SCHED_SMT
 993        bool "SMT scheduler support"
 994        help
 995          Improves the CPU scheduler's decision making when dealing with
 996          MultiThreading at a cost of slightly increased overhead in some
 997          places. If unsure say N here.
 998
 999config NR_CPUS
1000        int "Maximum number of CPUs (2-4096)"
1001        range 2 4096
1002        default "256"
1003
1004config HOTPLUG_CPU
1005        bool "Support for hot-pluggable CPUs"
1006        select GENERIC_IRQ_MIGRATION
1007        help
1008          Say Y here to experiment with turning CPUs off and on.  CPUs
1009          can be controlled through /sys/devices/system/cpu.
1010
1011# Common NUMA Features
1012config NUMA
1013        bool "NUMA Memory Allocation and Scheduler Support"
1014        select GENERIC_ARCH_NUMA
1015        select ACPI_NUMA if ACPI
1016        select OF_NUMA
1017        help
1018          Enable NUMA (Non-Uniform Memory Access) support.
1019
1020          The kernel will try to allocate memory used by a CPU on the
1021          local memory of the CPU and add some more
1022          NUMA awareness to the kernel.
1023
1024config NODES_SHIFT
1025        int "Maximum NUMA Nodes (as a power of 2)"
1026        range 1 10
1027        default "4"
1028        depends on NUMA
1029        help
1030          Specify the maximum number of NUMA Nodes available on the target
1031          system.  Increases memory reserved to accommodate various tables.
1032
1033config USE_PERCPU_NUMA_NODE_ID
1034        def_bool y
1035        depends on NUMA
1036
1037config HAVE_SETUP_PER_CPU_AREA
1038        def_bool y
1039        depends on NUMA
1040
1041config NEED_PER_CPU_EMBED_FIRST_CHUNK
1042        def_bool y
1043        depends on NUMA
1044
1045source "kernel/Kconfig.hz"
1046
1047config ARCH_SPARSEMEM_ENABLE
1048        def_bool y
1049        select SPARSEMEM_VMEMMAP_ENABLE
1050        select SPARSEMEM_VMEMMAP
1051
1052config HW_PERF_EVENTS
1053        def_bool y
1054        depends on ARM_PMU
1055
1056config ARCH_HAS_FILTER_PGPROT
1057        def_bool y
1058
1059# Supported by clang >= 7.0
1060config CC_HAVE_SHADOW_CALL_STACK
1061        def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1062
1063config PARAVIRT
1064        bool "Enable paravirtualization code"
1065        help
1066          This changes the kernel so it can modify itself when it is run
1067          under a hypervisor, potentially improving performance significantly
1068          over full virtualization.
1069
1070config PARAVIRT_TIME_ACCOUNTING
1071        bool "Paravirtual steal time accounting"
1072        select PARAVIRT
1073        help
1074          Select this option to enable fine granularity task steal time
1075          accounting. Time spent executing other tasks in parallel with
1076          the current vCPU is discounted from the vCPU power. To account for
1077          that, there can be a small performance impact.
1078
1079          If in doubt, say N here.
1080
1081config KEXEC
1082        depends on PM_SLEEP_SMP
1083        select KEXEC_CORE
1084        bool "kexec system call"
1085        help
1086          kexec is a system call that implements the ability to shutdown your
1087          current kernel, and to start another kernel.  It is like a reboot
1088          but it is independent of the system firmware.   And like a reboot
1089          you can start any kernel with it, not just Linux.
1090
1091config KEXEC_FILE
1092        bool "kexec file based system call"
1093        select KEXEC_CORE
1094        select HAVE_IMA_KEXEC if IMA
1095        help
1096          This is new version of kexec system call. This system call is
1097          file based and takes file descriptors as system call argument
1098          for kernel and initramfs as opposed to list of segments as
1099          accepted by previous system call.
1100
1101config KEXEC_SIG
1102        bool "Verify kernel signature during kexec_file_load() syscall"
1103        depends on KEXEC_FILE
1104        help
1105          Select this option to verify a signature with loaded kernel
1106          image. If configured, any attempt of loading a image without
1107          valid signature will fail.
1108
1109          In addition to that option, you need to enable signature
1110          verification for the corresponding kernel image type being
1111          loaded in order for this to work.
1112
1113config KEXEC_IMAGE_VERIFY_SIG
1114        bool "Enable Image signature verification support"
1115        default y
1116        depends on KEXEC_SIG
1117        depends on EFI && SIGNED_PE_FILE_VERIFICATION
1118        help
1119          Enable Image signature verification support.
1120
1121comment "Support for PE file signature verification disabled"
1122        depends on KEXEC_SIG
1123        depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1124
1125config CRASH_DUMP
1126        bool "Build kdump crash kernel"
1127        help
1128          Generate crash dump after being started by kexec. This should
1129          be normally only set in special crash dump kernels which are
1130          loaded in the main kernel with kexec-tools into a specially
1131          reserved region and then later executed after a crash by
1132          kdump/kexec.
1133
1134          For more details see Documentation/admin-guide/kdump/kdump.rst
1135
1136config TRANS_TABLE
1137        def_bool y
1138        depends on HIBERNATION
1139
1140config XEN_DOM0
1141        def_bool y
1142        depends on XEN
1143
1144config XEN
1145        bool "Xen guest support on ARM64"
1146        depends on ARM64 && OF
1147        select SWIOTLB_XEN
1148        select PARAVIRT
1149        help
1150          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1151
1152config FORCE_MAX_ZONEORDER
1153        int
1154        default "14" if ARM64_64K_PAGES
1155        default "12" if ARM64_16K_PAGES
1156        default "11"
1157        help
1158          The kernel memory allocator divides physically contiguous memory
1159          blocks into "zones", where each zone is a power of two number of
1160          pages.  This option selects the largest power of two that the kernel
1161          keeps in the memory allocator.  If you need to allocate very large
1162          blocks of physically contiguous memory, then you may need to
1163          increase this value.
1164
1165          This config option is actually maximum order plus one. For example,
1166          a value of 11 means that the largest free memory block is 2^10 pages.
1167
1168          We make sure that we can allocate upto a HugePage size for each configuration.
1169          Hence we have :
1170                MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1171
1172          However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1173          4M allocations matching the default size used by generic code.
1174
1175config UNMAP_KERNEL_AT_EL0
1176        bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1177        default y
1178        help
1179          Speculation attacks against some high-performance processors can
1180          be used to bypass MMU permission checks and leak kernel data to
1181          userspace. This can be defended against by unmapping the kernel
1182          when running in userspace, mapping it back in on exception entry
1183          via a trampoline page in the vector table.
1184
1185          If unsure, say Y.
1186
1187config RODATA_FULL_DEFAULT_ENABLED
1188        bool "Apply r/o permissions of VM areas also to their linear aliases"
1189        default y
1190        help
1191          Apply read-only attributes of VM areas to the linear alias of
1192          the backing pages as well. This prevents code or read-only data
1193          from being modified (inadvertently or intentionally) via another
1194          mapping of the same memory page. This additional enhancement can
1195          be turned off at runtime by passing rodata=[off|on] (and turned on
1196          with rodata=full if this option is set to 'n')
1197
1198          This requires the linear region to be mapped down to pages,
1199          which may adversely affect performance in some cases.
1200
1201config ARM64_SW_TTBR0_PAN
1202        bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1203        help
1204          Enabling this option prevents the kernel from accessing
1205          user-space memory directly by pointing TTBR0_EL1 to a reserved
1206          zeroed area and reserved ASID. The user access routines
1207          restore the valid TTBR0_EL1 temporarily.
1208
1209config ARM64_TAGGED_ADDR_ABI
1210        bool "Enable the tagged user addresses syscall ABI"
1211        default y
1212        help
1213          When this option is enabled, user applications can opt in to a
1214          relaxed ABI via prctl() allowing tagged addresses to be passed
1215          to system calls as pointer arguments. For details, see
1216          Documentation/arm64/tagged-address-abi.rst.
1217
1218menuconfig COMPAT
1219        bool "Kernel support for 32-bit EL0"
1220        depends on ARM64_4K_PAGES || EXPERT
1221        select HAVE_UID16
1222        select OLD_SIGSUSPEND3
1223        select COMPAT_OLD_SIGACTION
1224        help
1225          This option enables support for a 32-bit EL0 running under a 64-bit
1226          kernel at EL1. AArch32-specific components such as system calls,
1227          the user helper functions, VFP support and the ptrace interface are
1228          handled appropriately by the kernel.
1229
1230          If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1231          that you will only be able to execute AArch32 binaries that were compiled
1232          with page size aligned segments.
1233
1234          If you want to execute 32-bit userspace applications, say Y.
1235
1236if COMPAT
1237
1238config KUSER_HELPERS
1239        bool "Enable kuser helpers page for 32-bit applications"
1240        default y
1241        help
1242          Warning: disabling this option may break 32-bit user programs.
1243
1244          Provide kuser helpers to compat tasks. The kernel provides
1245          helper code to userspace in read only form at a fixed location
1246          to allow userspace to be independent of the CPU type fitted to
1247          the system. This permits binaries to be run on ARMv4 through
1248          to ARMv8 without modification.
1249
1250          See Documentation/arm/kernel_user_helpers.rst for details.
1251
1252          However, the fixed address nature of these helpers can be used
1253          by ROP (return orientated programming) authors when creating
1254          exploits.
1255
1256          If all of the binaries and libraries which run on your platform
1257          are built specifically for your platform, and make no use of
1258          these helpers, then you can turn this option off to hinder
1259          such exploits. However, in that case, if a binary or library
1260          relying on those helpers is run, it will not function correctly.
1261
1262          Say N here only if you are absolutely certain that you do not
1263          need these helpers; otherwise, the safe option is to say Y.
1264
1265config COMPAT_VDSO
1266        bool "Enable vDSO for 32-bit applications"
1267        depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1268        select GENERIC_COMPAT_VDSO
1269        default y
1270        help
1271          Place in the process address space of 32-bit applications an
1272          ELF shared object providing fast implementations of gettimeofday
1273          and clock_gettime.
1274
1275          You must have a 32-bit build of glibc 2.22 or later for programs
1276          to seamlessly take advantage of this.
1277
1278config THUMB2_COMPAT_VDSO
1279        bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1280        depends on COMPAT_VDSO
1281        default y
1282        help
1283          Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1284          otherwise with '-marm'.
1285
1286menuconfig ARMV8_DEPRECATED
1287        bool "Emulate deprecated/obsolete ARMv8 instructions"
1288        depends on SYSCTL
1289        help
1290          Legacy software support may require certain instructions
1291          that have been deprecated or obsoleted in the architecture.
1292
1293          Enable this config to enable selective emulation of these
1294          features.
1295
1296          If unsure, say Y
1297
1298if ARMV8_DEPRECATED
1299
1300config SWP_EMULATION
1301        bool "Emulate SWP/SWPB instructions"
1302        help
1303          ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1304          they are always undefined. Say Y here to enable software
1305          emulation of these instructions for userspace using LDXR/STXR.
1306          This feature can be controlled at runtime with the abi.swp
1307          sysctl which is disabled by default.
1308
1309          In some older versions of glibc [<=2.8] SWP is used during futex
1310          trylock() operations with the assumption that the code will not
1311          be preempted. This invalid assumption may be more likely to fail
1312          with SWP emulation enabled, leading to deadlock of the user
1313          application.
1314
1315          NOTE: when accessing uncached shared regions, LDXR/STXR rely
1316          on an external transaction monitoring block called a global
1317          monitor to maintain update atomicity. If your system does not
1318          implement a global monitor, this option can cause programs that
1319          perform SWP operations to uncached memory to deadlock.
1320
1321          If unsure, say Y
1322
1323config CP15_BARRIER_EMULATION
1324        bool "Emulate CP15 Barrier instructions"
1325        help
1326          The CP15 barrier instructions - CP15ISB, CP15DSB, and
1327          CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1328          strongly recommended to use the ISB, DSB, and DMB
1329          instructions instead.
1330
1331          Say Y here to enable software emulation of these
1332          instructions for AArch32 userspace code. When this option is
1333          enabled, CP15 barrier usage is traced which can help
1334          identify software that needs updating. This feature can be
1335          controlled at runtime with the abi.cp15_barrier sysctl.
1336
1337          If unsure, say Y
1338
1339config SETEND_EMULATION
1340        bool "Emulate SETEND instruction"
1341        help
1342          The SETEND instruction alters the data-endianness of the
1343          AArch32 EL0, and is deprecated in ARMv8.
1344
1345          Say Y here to enable software emulation of the instruction
1346          for AArch32 userspace code. This feature can be controlled
1347          at runtime with the abi.setend sysctl.
1348
1349          Note: All the cpus on the system must have mixed endian support at EL0
1350          for this feature to be enabled. If a new CPU - which doesn't support mixed
1351          endian - is hotplugged in after this feature has been enabled, there could
1352          be unexpected results in the applications.
1353
1354          If unsure, say Y
1355endif
1356
1357endif
1358
1359menu "ARMv8.1 architectural features"
1360
1361config ARM64_HW_AFDBM
1362        bool "Support for hardware updates of the Access and Dirty page flags"
1363        default y
1364        help
1365          The ARMv8.1 architecture extensions introduce support for
1366          hardware updates of the access and dirty information in page
1367          table entries. When enabled in TCR_EL1 (HA and HD bits) on
1368          capable processors, accesses to pages with PTE_AF cleared will
1369          set this bit instead of raising an access flag fault.
1370          Similarly, writes to read-only pages with the DBM bit set will
1371          clear the read-only bit (AP[2]) instead of raising a
1372          permission fault.
1373
1374          Kernels built with this configuration option enabled continue
1375          to work on pre-ARMv8.1 hardware and the performance impact is
1376          minimal. If unsure, say Y.
1377
1378config ARM64_PAN
1379        bool "Enable support for Privileged Access Never (PAN)"
1380        default y
1381        help
1382         Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1383         prevents the kernel or hypervisor from accessing user-space (EL0)
1384         memory directly.
1385
1386         Choosing this option will cause any unprotected (not using
1387         copy_to_user et al) memory access to fail with a permission fault.
1388
1389         The feature is detected at runtime, and will remain as a 'nop'
1390         instruction if the cpu does not implement the feature.
1391
1392config AS_HAS_LDAPR
1393        def_bool $(as-instr,.arch_extension rcpc)
1394
1395config AS_HAS_LSE_ATOMICS
1396        def_bool $(as-instr,.arch_extension lse)
1397
1398config ARM64_LSE_ATOMICS
1399        bool
1400        default ARM64_USE_LSE_ATOMICS
1401        depends on AS_HAS_LSE_ATOMICS
1402
1403config ARM64_USE_LSE_ATOMICS
1404        bool "Atomic instructions"
1405        depends on JUMP_LABEL
1406        default y
1407        help
1408          As part of the Large System Extensions, ARMv8.1 introduces new
1409          atomic instructions that are designed specifically to scale in
1410          very large systems.
1411
1412          Say Y here to make use of these instructions for the in-kernel
1413          atomic routines. This incurs a small overhead on CPUs that do
1414          not support these instructions and requires the kernel to be
1415          built with binutils >= 2.25 in order for the new instructions
1416          to be used.
1417
1418endmenu
1419
1420menu "ARMv8.2 architectural features"
1421
1422config ARM64_PMEM
1423        bool "Enable support for persistent memory"
1424        select ARCH_HAS_PMEM_API
1425        select ARCH_HAS_UACCESS_FLUSHCACHE
1426        help
1427          Say Y to enable support for the persistent memory API based on the
1428          ARMv8.2 DCPoP feature.
1429
1430          The feature is detected at runtime, and the kernel will use DC CVAC
1431          operations if DC CVAP is not supported (following the behaviour of
1432          DC CVAP itself if the system does not define a point of persistence).
1433
1434config ARM64_RAS_EXTN
1435        bool "Enable support for RAS CPU Extensions"
1436        default y
1437        help
1438          CPUs that support the Reliability, Availability and Serviceability
1439          (RAS) Extensions, part of ARMv8.2 are able to track faults and
1440          errors, classify them and report them to software.
1441
1442          On CPUs with these extensions system software can use additional
1443          barriers to determine if faults are pending and read the
1444          classification from a new set of registers.
1445
1446          Selecting this feature will allow the kernel to use these barriers
1447          and access the new registers if the system supports the extension.
1448          Platform RAS features may additionally depend on firmware support.
1449
1450config ARM64_CNP
1451        bool "Enable support for Common Not Private (CNP) translations"
1452        default y
1453        depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1454        help
1455          Common Not Private (CNP) allows translation table entries to
1456          be shared between different PEs in the same inner shareable
1457          domain, so the hardware can use this fact to optimise the
1458          caching of such entries in the TLB.
1459
1460          Selecting this option allows the CNP feature to be detected
1461          at runtime, and does not affect PEs that do not implement
1462          this feature.
1463
1464endmenu
1465
1466menu "ARMv8.3 architectural features"
1467
1468config ARM64_PTR_AUTH
1469        bool "Enable support for pointer authentication"
1470        default y
1471        help
1472          Pointer authentication (part of the ARMv8.3 Extensions) provides
1473          instructions for signing and authenticating pointers against secret
1474          keys, which can be used to mitigate Return Oriented Programming (ROP)
1475          and other attacks.
1476
1477          This option enables these instructions at EL0 (i.e. for userspace).
1478          Choosing this option will cause the kernel to initialise secret keys
1479          for each process at exec() time, with these keys being
1480          context-switched along with the process.
1481
1482          The feature is detected at runtime. If the feature is not present in
1483          hardware it will not be advertised to userspace/KVM guest nor will it
1484          be enabled.
1485
1486          If the feature is present on the boot CPU but not on a late CPU, then
1487          the late CPU will be parked. Also, if the boot CPU does not have
1488          address auth and the late CPU has then the late CPU will still boot
1489          but with the feature disabled. On such a system, this option should
1490          not be selected.
1491
1492config ARM64_PTR_AUTH_KERNEL
1493        bool "Use pointer authentication for kernel"
1494        default y
1495        depends on ARM64_PTR_AUTH
1496        depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1497        # Modern compilers insert a .note.gnu.property section note for PAC
1498        # which is only understood by binutils starting with version 2.33.1.
1499        depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1500        depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1501        depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1502        help
1503          If the compiler supports the -mbranch-protection or
1504          -msign-return-address flag (e.g. GCC 7 or later), then this option
1505          will cause the kernel itself to be compiled with return address
1506          protection. In this case, and if the target hardware is known to
1507          support pointer authentication, then CONFIG_STACKPROTECTOR can be
1508          disabled with minimal loss of protection.
1509
1510          This feature works with FUNCTION_GRAPH_TRACER option only if
1511          DYNAMIC_FTRACE_WITH_REGS is enabled.
1512
1513config CC_HAS_BRANCH_PROT_PAC_RET
1514        # GCC 9 or later, clang 8 or later
1515        def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1516
1517config CC_HAS_SIGN_RETURN_ADDRESS
1518        # GCC 7, 8
1519        def_bool $(cc-option,-msign-return-address=all)
1520
1521config AS_HAS_PAC
1522        def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1523
1524config AS_HAS_CFI_NEGATE_RA_STATE
1525        def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1526
1527endmenu
1528
1529menu "ARMv8.4 architectural features"
1530
1531config ARM64_AMU_EXTN
1532        bool "Enable support for the Activity Monitors Unit CPU extension"
1533        default y
1534        help
1535          The activity monitors extension is an optional extension introduced
1536          by the ARMv8.4 CPU architecture. This enables support for version 1
1537          of the activity monitors architecture, AMUv1.
1538
1539          To enable the use of this extension on CPUs that implement it, say Y.
1540
1541          Note that for architectural reasons, firmware _must_ implement AMU
1542          support when running on CPUs that present the activity monitors
1543          extension. The required support is present in:
1544            * Version 1.5 and later of the ARM Trusted Firmware
1545
1546          For kernels that have this configuration enabled but boot with broken
1547          firmware, you may need to say N here until the firmware is fixed.
1548          Otherwise you may experience firmware panics or lockups when
1549          accessing the counter registers. Even if you are not observing these
1550          symptoms, the values returned by the register reads might not
1551          correctly reflect reality. Most commonly, the value read will be 0,
1552          indicating that the counter is not enabled.
1553
1554config AS_HAS_ARMV8_4
1555        def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1556
1557config ARM64_TLB_RANGE
1558        bool "Enable support for tlbi range feature"
1559        default y
1560        depends on AS_HAS_ARMV8_4
1561        help
1562          ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1563          range of input addresses.
1564
1565          The feature introduces new assembly instructions, and they were
1566          support when binutils >= 2.30.
1567
1568endmenu
1569
1570menu "ARMv8.5 architectural features"
1571
1572config AS_HAS_ARMV8_5
1573        def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1574
1575config ARM64_BTI
1576        bool "Branch Target Identification support"
1577        default y
1578        help
1579          Branch Target Identification (part of the ARMv8.5 Extensions)
1580          provides a mechanism to limit the set of locations to which computed
1581          branch instructions such as BR or BLR can jump.
1582
1583          To make use of BTI on CPUs that support it, say Y.
1584
1585          BTI is intended to provide complementary protection to other control
1586          flow integrity protection mechanisms, such as the Pointer
1587          authentication mechanism provided as part of the ARMv8.3 Extensions.
1588          For this reason, it does not make sense to enable this option without
1589          also enabling support for pointer authentication.  Thus, when
1590          enabling this option you should also select ARM64_PTR_AUTH=y.
1591
1592          Userspace binaries must also be specifically compiled to make use of
1593          this mechanism.  If you say N here or the hardware does not support
1594          BTI, such binaries can still run, but you get no additional
1595          enforcement of branch destinations.
1596
1597config ARM64_BTI_KERNEL
1598        bool "Use Branch Target Identification for kernel"
1599        default y
1600        depends on ARM64_BTI
1601        depends on ARM64_PTR_AUTH_KERNEL
1602        depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1603        # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1604        depends on !CC_IS_GCC || GCC_VERSION >= 100100
1605        # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1606        depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1607        depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1608        help
1609          Build the kernel with Branch Target Identification annotations
1610          and enable enforcement of this for kernel code. When this option
1611          is enabled and the system supports BTI all kernel code including
1612          modular code must have BTI enabled.
1613
1614config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1615        # GCC 9 or later, clang 8 or later
1616        def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1617
1618config ARM64_E0PD
1619        bool "Enable support for E0PD"
1620        default y
1621        help
1622          E0PD (part of the ARMv8.5 extensions) allows us to ensure
1623          that EL0 accesses made via TTBR1 always fault in constant time,
1624          providing similar benefits to KASLR as those provided by KPTI, but
1625          with lower overhead and without disrupting legitimate access to
1626          kernel memory such as SPE.
1627
1628          This option enables E0PD for TTBR1 where available.
1629
1630config ARCH_RANDOM
1631        bool "Enable support for random number generation"
1632        default y
1633        help
1634          Random number generation (part of the ARMv8.5 Extensions)
1635          provides a high bandwidth, cryptographically secure
1636          hardware random number generator.
1637
1638config ARM64_AS_HAS_MTE
1639        # Initial support for MTE went in binutils 2.32.0, checked with
1640        # ".arch armv8.5-a+memtag" below. However, this was incomplete
1641        # as a late addition to the final architecture spec (LDGM/STGM)
1642        # is only supported in the newer 2.32.x and 2.33 binutils
1643        # versions, hence the extra "stgm" instruction check below.
1644        def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1645
1646config ARM64_MTE
1647        bool "Memory Tagging Extension support"
1648        default y
1649        depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1650        depends on AS_HAS_ARMV8_5
1651        depends on AS_HAS_LSE_ATOMICS
1652        # Required for tag checking in the uaccess routines
1653        depends on ARM64_PAN
1654        select ARCH_USES_HIGH_VMA_FLAGS
1655        help
1656          Memory Tagging (part of the ARMv8.5 Extensions) provides
1657          architectural support for run-time, always-on detection of
1658          various classes of memory error to aid with software debugging
1659          to eliminate vulnerabilities arising from memory-unsafe
1660          languages.
1661
1662          This option enables the support for the Memory Tagging
1663          Extension at EL0 (i.e. for userspace).
1664
1665          Selecting this option allows the feature to be detected at
1666          runtime. Any secondary CPU not implementing this feature will
1667          not be allowed a late bring-up.
1668
1669          Userspace binaries that want to use this feature must
1670          explicitly opt in. The mechanism for the userspace is
1671          described in:
1672
1673          Documentation/arm64/memory-tagging-extension.rst.
1674
1675endmenu
1676
1677menu "ARMv8.7 architectural features"
1678
1679config ARM64_EPAN
1680        bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1681        default y
1682        depends on ARM64_PAN
1683        help
1684         Enhanced Privileged Access Never (EPAN) allows Privileged
1685         Access Never to be used with Execute-only mappings.
1686
1687         The feature is detected at runtime, and will remain disabled
1688         if the cpu does not implement the feature.
1689endmenu
1690
1691config ARM64_SVE
1692        bool "ARM Scalable Vector Extension support"
1693        default y
1694        help
1695          The Scalable Vector Extension (SVE) is an extension to the AArch64
1696          execution state which complements and extends the SIMD functionality
1697          of the base architecture to support much larger vectors and to enable
1698          additional vectorisation opportunities.
1699
1700          To enable use of this extension on CPUs that implement it, say Y.
1701
1702          On CPUs that support the SVE2 extensions, this option will enable
1703          those too.
1704
1705          Note that for architectural reasons, firmware _must_ implement SVE
1706          support when running on SVE capable hardware.  The required support
1707          is present in:
1708
1709            * version 1.5 and later of the ARM Trusted Firmware
1710            * the AArch64 boot wrapper since commit 5e1261e08abf
1711              ("bootwrapper: SVE: Enable SVE for EL2 and below").
1712
1713          For other firmware implementations, consult the firmware documentation
1714          or vendor.
1715
1716          If you need the kernel to boot on SVE-capable hardware with broken
1717          firmware, you may need to say N here until you get your firmware
1718          fixed.  Otherwise, you may experience firmware panics or lockups when
1719          booting the kernel.  If unsure and you are not observing these
1720          symptoms, you should assume that it is safe to say Y.
1721
1722config ARM64_MODULE_PLTS
1723        bool "Use PLTs to allow module memory to spill over into vmalloc area"
1724        depends on MODULES
1725        select HAVE_MOD_ARCH_SPECIFIC
1726        help
1727          Allocate PLTs when loading modules so that jumps and calls whose
1728          targets are too far away for their relative offsets to be encoded
1729          in the instructions themselves can be bounced via veneers in the
1730          module's PLT. This allows modules to be allocated in the generic
1731          vmalloc area after the dedicated module memory area has been
1732          exhausted.
1733
1734          When running with address space randomization (KASLR), the module
1735          region itself may be too far away for ordinary relative jumps and
1736          calls, and so in that case, module PLTs are required and cannot be
1737          disabled.
1738
1739          Specific errata workaround(s) might also force module PLTs to be
1740          enabled (ARM64_ERRATUM_843419).
1741
1742config ARM64_PSEUDO_NMI
1743        bool "Support for NMI-like interrupts"
1744        select ARM_GIC_V3
1745        help
1746          Adds support for mimicking Non-Maskable Interrupts through the use of
1747          GIC interrupt priority. This support requires version 3 or later of
1748          ARM GIC.
1749
1750          This high priority configuration for interrupts needs to be
1751          explicitly enabled by setting the kernel parameter
1752          "irqchip.gicv3_pseudo_nmi" to 1.
1753
1754          If unsure, say N
1755
1756if ARM64_PSEUDO_NMI
1757config ARM64_DEBUG_PRIORITY_MASKING
1758        bool "Debug interrupt priority masking"
1759        help
1760          This adds runtime checks to functions enabling/disabling
1761          interrupts when using priority masking. The additional checks verify
1762          the validity of ICC_PMR_EL1 when calling concerned functions.
1763
1764          If unsure, say N
1765endif
1766
1767config RELOCATABLE
1768        bool "Build a relocatable kernel image" if EXPERT
1769        select ARCH_HAS_RELR
1770        default y
1771        help
1772          This builds the kernel as a Position Independent Executable (PIE),
1773          which retains all relocation metadata required to relocate the
1774          kernel binary at runtime to a different virtual address than the
1775          address it was linked at.
1776          Since AArch64 uses the RELA relocation format, this requires a
1777          relocation pass at runtime even if the kernel is loaded at the
1778          same address it was linked at.
1779
1780config RANDOMIZE_BASE
1781        bool "Randomize the address of the kernel image"
1782        select ARM64_MODULE_PLTS if MODULES
1783        select RELOCATABLE
1784        help
1785          Randomizes the virtual address at which the kernel image is
1786          loaded, as a security feature that deters exploit attempts
1787          relying on knowledge of the location of kernel internals.
1788
1789          It is the bootloader's job to provide entropy, by passing a
1790          random u64 value in /chosen/kaslr-seed at kernel entry.
1791
1792          When booting via the UEFI stub, it will invoke the firmware's
1793          EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1794          to the kernel proper. In addition, it will randomise the physical
1795          location of the kernel Image as well.
1796
1797          If unsure, say N.
1798
1799config RANDOMIZE_MODULE_REGION_FULL
1800        bool "Randomize the module region over a 2 GB range"
1801        depends on RANDOMIZE_BASE
1802        default y
1803        help
1804          Randomizes the location of the module region inside a 2 GB window
1805          covering the core kernel. This way, it is less likely for modules
1806          to leak information about the location of core kernel data structures
1807          but it does imply that function calls between modules and the core
1808          kernel will need to be resolved via veneers in the module PLT.
1809
1810          When this option is not set, the module region will be randomized over
1811          a limited range that contains the [_stext, _etext] interval of the
1812          core kernel, so branch relocations are almost always in range unless
1813          ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1814          particular case of region exhaustion, modules might be able to fall
1815          back to a larger 2GB area.
1816
1817config CC_HAVE_STACKPROTECTOR_SYSREG
1818        def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1819
1820config STACKPROTECTOR_PER_TASK
1821        def_bool y
1822        depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1823
1824endmenu
1825
1826menu "Boot options"
1827
1828config ARM64_ACPI_PARKING_PROTOCOL
1829        bool "Enable support for the ARM64 ACPI parking protocol"
1830        depends on ACPI
1831        help
1832          Enable support for the ARM64 ACPI parking protocol. If disabled
1833          the kernel will not allow booting through the ARM64 ACPI parking
1834          protocol even if the corresponding data is present in the ACPI
1835          MADT table.
1836
1837config CMDLINE
1838        string "Default kernel command string"
1839        default ""
1840        help
1841          Provide a set of default command-line options at build time by
1842          entering them here. As a minimum, you should specify the the
1843          root device (e.g. root=/dev/nfs).
1844
1845choice
1846        prompt "Kernel command line type" if CMDLINE != ""
1847        default CMDLINE_FROM_BOOTLOADER
1848        help
1849          Choose how the kernel will handle the provided default kernel
1850          command line string.
1851
1852config CMDLINE_FROM_BOOTLOADER
1853        bool "Use bootloader kernel arguments if available"
1854        help
1855          Uses the command-line options passed by the boot loader. If
1856          the boot loader doesn't provide any, the default kernel command
1857          string provided in CMDLINE will be used.
1858
1859config CMDLINE_FORCE
1860        bool "Always use the default kernel command string"
1861        help
1862          Always use the default kernel command string, even if the boot
1863          loader passes other arguments to the kernel.
1864          This is useful if you cannot or don't want to change the
1865          command-line options your boot loader passes to the kernel.
1866
1867endchoice
1868
1869config EFI_STUB
1870        bool
1871
1872config EFI
1873        bool "UEFI runtime support"
1874        depends on OF && !CPU_BIG_ENDIAN
1875        depends on KERNEL_MODE_NEON
1876        select ARCH_SUPPORTS_ACPI
1877        select LIBFDT
1878        select UCS2_STRING
1879        select EFI_PARAMS_FROM_FDT
1880        select EFI_RUNTIME_WRAPPERS
1881        select EFI_STUB
1882        select EFI_GENERIC_STUB
1883        imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1884        default y
1885        help
1886          This option provides support for runtime services provided
1887          by UEFI firmware (such as non-volatile variables, realtime
1888          clock, and platform reset). A UEFI stub is also provided to
1889          allow the kernel to be booted as an EFI application. This
1890          is only useful on systems that have UEFI firmware.
1891
1892config DMI
1893        bool "Enable support for SMBIOS (DMI) tables"
1894        depends on EFI
1895        default y
1896        help
1897          This enables SMBIOS/DMI feature for systems.
1898
1899          This option is only useful on systems that have UEFI firmware.
1900          However, even with this option, the resultant kernel should
1901          continue to boot on existing non-UEFI platforms.
1902
1903endmenu
1904
1905config SYSVIPC_COMPAT
1906        def_bool y
1907        depends on COMPAT && SYSVIPC
1908
1909menu "Power management options"
1910
1911source "kernel/power/Kconfig"
1912
1913config ARCH_HIBERNATION_POSSIBLE
1914        def_bool y
1915        depends on CPU_PM
1916
1917config ARCH_HIBERNATION_HEADER
1918        def_bool y
1919        depends on HIBERNATION
1920
1921config ARCH_SUSPEND_POSSIBLE
1922        def_bool y
1923
1924endmenu
1925
1926menu "CPU Power Management"
1927
1928source "drivers/cpuidle/Kconfig"
1929
1930source "drivers/cpufreq/Kconfig"
1931
1932endmenu
1933
1934source "drivers/acpi/Kconfig"
1935
1936source "arch/arm64/kvm/Kconfig"
1937
1938if CRYPTO
1939source "arch/arm64/crypto/Kconfig"
1940endif
1941