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7#ifndef __ARM64_KVM_ARM_H__
8#define __ARM64_KVM_ARM_H__
9
10#include <asm/esr.h>
11#include <asm/memory.h>
12#include <asm/types.h>
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15
16#define HCR_TID5 (UL(1) << 58)
17#define HCR_DCT (UL(1) << 57)
18#define HCR_ATA_SHIFT 56
19#define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
20#define HCR_AMVOFFEN (UL(1) << 51)
21#define HCR_FIEN (UL(1) << 47)
22#define HCR_FWB (UL(1) << 46)
23#define HCR_API (UL(1) << 41)
24#define HCR_APK (UL(1) << 40)
25#define HCR_TEA (UL(1) << 37)
26#define HCR_TERR (UL(1) << 36)
27#define HCR_TLOR (UL(1) << 35)
28#define HCR_E2H (UL(1) << 34)
29#define HCR_ID (UL(1) << 33)
30#define HCR_CD (UL(1) << 32)
31#define HCR_RW_SHIFT 31
32#define HCR_RW (UL(1) << HCR_RW_SHIFT)
33#define HCR_TRVM (UL(1) << 30)
34#define HCR_HCD (UL(1) << 29)
35#define HCR_TDZ (UL(1) << 28)
36#define HCR_TGE (UL(1) << 27)
37#define HCR_TVM (UL(1) << 26)
38#define HCR_TTLB (UL(1) << 25)
39#define HCR_TPU (UL(1) << 24)
40#define HCR_TPC (UL(1) << 23)
41#define HCR_TSW (UL(1) << 22)
42#define HCR_TACR (UL(1) << 21)
43#define HCR_TIDCP (UL(1) << 20)
44#define HCR_TSC (UL(1) << 19)
45#define HCR_TID3 (UL(1) << 18)
46#define HCR_TID2 (UL(1) << 17)
47#define HCR_TID1 (UL(1) << 16)
48#define HCR_TID0 (UL(1) << 15)
49#define HCR_TWE (UL(1) << 14)
50#define HCR_TWI (UL(1) << 13)
51#define HCR_DC (UL(1) << 12)
52#define HCR_BSU (3 << 10)
53#define HCR_BSU_IS (UL(1) << 10)
54#define HCR_FB (UL(1) << 9)
55#define HCR_VSE (UL(1) << 8)
56#define HCR_VI (UL(1) << 7)
57#define HCR_VF (UL(1) << 6)
58#define HCR_AMO (UL(1) << 5)
59#define HCR_IMO (UL(1) << 4)
60#define HCR_FMO (UL(1) << 3)
61#define HCR_PTW (UL(1) << 2)
62#define HCR_SWIO (UL(1) << 1)
63#define HCR_VM (UL(1) << 0)
64#define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39))
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84#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
85 HCR_BSU_IS | HCR_FB | HCR_TACR | \
86 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
87 HCR_FMO | HCR_IMO | HCR_PTW )
88#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
89#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
90#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
91#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
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94#define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
95#define TCR_EL2_TBI (1 << 20)
96#define TCR_EL2_PS_SHIFT 16
97#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
98#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
99#define TCR_EL2_TG0_MASK TCR_TG0_MASK
100#define TCR_EL2_SH0_MASK TCR_SH0_MASK
101#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
102#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
103#define TCR_EL2_T0SZ_MASK 0x3f
104#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
105 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
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107
108#define VTCR_EL2_RES1 (1U << 31)
109#define VTCR_EL2_HD (1 << 22)
110#define VTCR_EL2_HA (1 << 21)
111#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
112#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
113#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
114#define VTCR_EL2_TG0_4K TCR_TG0_4K
115#define VTCR_EL2_TG0_16K TCR_TG0_16K
116#define VTCR_EL2_TG0_64K TCR_TG0_64K
117#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
118#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
119#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
120#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
121#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
122#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
123#define VTCR_EL2_SL0_SHIFT 6
124#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
125#define VTCR_EL2_T0SZ_MASK 0x3f
126#define VTCR_EL2_VS_SHIFT 19
127#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
128#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
129
130#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
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144#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
145 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
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176#ifdef CONFIG_ARM64_64K_PAGES
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178#define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
179#define VTCR_EL2_TGRAN_SL0_BASE 3UL
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181#elif defined(CONFIG_ARM64_16K_PAGES)
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183#define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
184#define VTCR_EL2_TGRAN_SL0_BASE 3UL
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186#else
187
188#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
189#define VTCR_EL2_TGRAN_SL0_BASE 2UL
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191#endif
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193#define VTCR_EL2_LVLS_TO_SL0(levels) \
194 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
195#define VTCR_EL2_SL0_TO_LVLS(sl0) \
196 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
197#define VTCR_EL2_LVLS(vtcr) \
198 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
199
200#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
201#define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
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266#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
267
268#define VTTBR_CNP_BIT (UL(1))
269#define VTTBR_VMID_SHIFT (UL(48))
270#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
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273#define HSTR_EL2_T(x) (1 << x)
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276#define CPTR_EL2_TFP_SHIFT 10
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279#define CPTR_EL2_TCPAC (1 << 31)
280#define CPTR_EL2_TAM (1 << 30)
281#define CPTR_EL2_TTA (1 << 20)
282#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
283#define CPTR_EL2_TZ (1 << 8)
284#define CPTR_NVHE_EL2_RES1 0x000032ff
285#define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1
286#define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \
287 GENMASK(29, 21) | \
288 GENMASK(19, 14) | \
289 BIT(11))
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292#define MDCR_EL2_E2TB_MASK (UL(0x3))
293#define MDCR_EL2_E2TB_SHIFT (UL(24))
294#define MDCR_EL2_HPMFZS (UL(1) << 36)
295#define MDCR_EL2_HPMFZO (UL(1) << 29)
296#define MDCR_EL2_MTPME (UL(1) << 28)
297#define MDCR_EL2_TDCC (UL(1) << 27)
298#define MDCR_EL2_HCCD (UL(1) << 23)
299#define MDCR_EL2_TTRF (UL(1) << 19)
300#define MDCR_EL2_HPMD (UL(1) << 17)
301#define MDCR_EL2_TPMS (UL(1) << 14)
302#define MDCR_EL2_E2PB_MASK (UL(0x3))
303#define MDCR_EL2_E2PB_SHIFT (UL(12))
304#define MDCR_EL2_TDRA (UL(1) << 11)
305#define MDCR_EL2_TDOSA (UL(1) << 10)
306#define MDCR_EL2_TDA (UL(1) << 9)
307#define MDCR_EL2_TDE (UL(1) << 8)
308#define MDCR_EL2_HPME (UL(1) << 7)
309#define MDCR_EL2_TPM (UL(1) << 6)
310#define MDCR_EL2_TPMCR (UL(1) << 5)
311#define MDCR_EL2_HPMN_MASK (UL(0x1F))
312#define MDCR_EL2_RES0 (GENMASK(63, 37) | \
313 GENMASK(35, 30) | \
314 GENMASK(25, 24) | \
315 GENMASK(22, 20) | \
316 BIT(18) | \
317 GENMASK(16, 15))
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319
320#define FSC_FAULT ESR_ELx_FSC_FAULT
321#define FSC_ACCESS ESR_ELx_FSC_ACCESS
322#define FSC_PERM ESR_ELx_FSC_PERM
323#define FSC_SEA ESR_ELx_FSC_EXTABT
324#define FSC_SEA_TTW0 (0x14)
325#define FSC_SEA_TTW1 (0x15)
326#define FSC_SEA_TTW2 (0x16)
327#define FSC_SEA_TTW3 (0x17)
328#define FSC_SECC (0x18)
329#define FSC_SECC_TTW0 (0x1c)
330#define FSC_SECC_TTW1 (0x1d)
331#define FSC_SECC_TTW2 (0x1e)
332#define FSC_SECC_TTW3 (0x1f)
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335#define HPFAR_MASK (~UL(0xf))
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341#define PAR_TO_HPFAR(par) \
342 (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
343
344#define ECN(x) { ESR_ELx_EC_##x, #x }
345
346#define kvm_arm_exception_class \
347 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
348 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
349 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
350 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
351 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
352 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
353 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
354 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
355 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
356
357#define CPACR_EL1_FPEN (3 << 20)
358#define CPACR_EL1_TTA (1 << 28)
359#define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)
360
361#endif
362