LXR linux/arch/arm64/include/asm/pgtable.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2012 ARM Ltd.
   4 */
   5#ifndef __ASM_PGTABLE_H
   6#define __ASM_PGTABLE_H
   7
   8#include <asm/bug.h>
   9#include <asm/proc-fns.h>
  10
  11#include <asm/memory.h>
  12#include <asm/mte.h>
  13#include <asm/pgtable-hwdef.h>
  14#include <asm/pgtable-prot.h>
  15#include <asm/tlbflush.h>
  16
  17/*
  18 * VMALLOC range.
  19 *
  20 * VMALLOC_START: beginning of the kernel vmalloc space
  21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
  22 *      and fixed mappings
  23 */
  24#define VMALLOC_START           (MODULES_END)
  25#define VMALLOC_END             (VMEMMAP_START - SZ_256M)
  26
  27#define vmemmap                 ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
  28
  29#ifndef __ASSEMBLY__
  30
  31#include <asm/cmpxchg.h>
  32#include <asm/fixmap.h>
  33#include <linux/mmdebug.h>
  34#include <linux/mm_types.h>
  35#include <linux/sched.h>
  36
  37#ifdef CONFIG_TRANSPARENT_HUGEPAGE
  38#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
  39
  40/* Set stride and tlb_level in flush_*_tlb_range */
  41#define flush_pmd_tlb_range(vma, addr, end)     \
  42        __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
  43#define flush_pud_tlb_range(vma, addr, end)     \
  44        __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
  45#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
  46
  47/*
  48 * Outside of a few very special situations (e.g. hibernation), we always
  49 * use broadcast TLB invalidation instructions, therefore a spurious page
  50 * fault on one CPU which has been handled concurrently by another CPU
  51 * does not need to perform additional invalidation.
  52 */
  53#define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
  54
  55/*
  56 * ZERO_PAGE is a global shared page that is always zero: used
  57 * for zero-mapped memory areas etc..
  58 */
  59extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
  60#define ZERO_PAGE(vaddr)        phys_to_page(__pa_symbol(empty_zero_page))
  61
  62#define pte_ERROR(e)    \
  63        pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
  64
  65/*
  66 * Macros to convert between a physical address and its placement in a
  67 * page table entry, taking care of 52-bit addresses.
  68 */
  69#ifdef CONFIG_ARM64_PA_BITS_52
  70#define __pte_to_phys(pte)      \
  71        ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
  72#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
  73#else
  74#define __pte_to_phys(pte)      (pte_val(pte) & PTE_ADDR_MASK)
  75#define __phys_to_pte_val(phys) (phys)
  76#endif
  77
  78#define pte_pfn(pte)            (__pte_to_phys(pte) >> PAGE_SHIFT)
  79#define pfn_pte(pfn,prot)       \
  80        __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
  81
  82#define pte_none(pte)           (!pte_val(pte))
  83#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
  84#define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
  85
  86/*
  87 * The following only work if pte_present(). Undefined behaviour otherwise.
  88 */
  89#define pte_present(pte)        (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
  90#define pte_young(pte)          (!!(pte_val(pte) & PTE_AF))
  91#define pte_special(pte)        (!!(pte_val(pte) & PTE_SPECIAL))
  92#define pte_write(pte)          (!!(pte_val(pte) & PTE_WRITE))
  93#define pte_user_exec(pte)      (!(pte_val(pte) & PTE_UXN))
  94#define pte_cont(pte)           (!!(pte_val(pte) & PTE_CONT))
  95#define pte_devmap(pte)         (!!(pte_val(pte) & PTE_DEVMAP))
  96#define pte_tagged(pte)         ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
  97                                 PTE_ATTRINDX(MT_NORMAL_TAGGED))
  98
  99#define pte_cont_addr_end(addr, end)                                            \
 100({      unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK;    \
 101        (__boundary - 1 < (end) - 1) ? __boundary : (end);                      \
 102})
 103
 104#define pmd_cont_addr_end(addr, end)                                            \
 105({      unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK;    \
 106        (__boundary - 1 < (end) - 1) ? __boundary : (end);                      \
 107})
 108
 109#define pte_hw_dirty(pte)       (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
 110#define pte_sw_dirty(pte)       (!!(pte_val(pte) & PTE_DIRTY))
 111#define pte_dirty(pte)          (pte_sw_dirty(pte) || pte_hw_dirty(pte))
 112
 113#define pte_valid(pte)          (!!(pte_val(pte) & PTE_VALID))
 114/*
 115 * Execute-only user mappings do not have the PTE_USER bit set. All valid
 116 * kernel mappings have the PTE_UXN bit set.
 117 */
 118#define pte_valid_not_user(pte) \
 119        ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
 120/*
 121 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
 122 * so that we don't erroneously return false for pages that have been
 123 * remapped as PROT_NONE but are yet to be flushed from the TLB.
 124 * Note that we can't make any assumptions based on the state of the access
 125 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
 126 * TLB.
 127 */
 128#define pte_accessible(mm, pte) \
 129        (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
 130
 131/*
 132 * p??_access_permitted() is true for valid user mappings (PTE_USER
 133 * bit set, subject to the write permission check). For execute-only
 134 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
 135 * not set) must return false. PROT_NONE mappings do not have the
 136 * PTE_VALID bit set.
 137 */
 138#define pte_access_permitted(pte, write) \
 139        (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
 140#define pmd_access_permitted(pmd, write) \
 141        (pte_access_permitted(pmd_pte(pmd), (write)))
 142#define pud_access_permitted(pud, write) \
 143        (pte_access_permitted(pud_pte(pud), (write)))
 144
 145static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
 146{
 147        pte_val(pte) &= ~pgprot_val(prot);
 148        return pte;
 149}
 150
 151static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
 152{
 153        pte_val(pte) |= pgprot_val(prot);
 154        return pte;
 155}
 156
 157static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
 158{
 159        pmd_val(pmd) &= ~pgprot_val(prot);
 160        return pmd;
 161}
 162
 163static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
 164{
 165        pmd_val(pmd) |= pgprot_val(prot);
 166        return pmd;
 167}
 168
 169static inline pte_t pte_mkwrite(pte_t pte)
 170{
 171        pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
 172        pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
 173        return pte;
 174}
 175
 176static inline pte_t pte_mkclean(pte_t pte)
 177{
 178        pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
 179        pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
 180
 181        return pte;
 182}
 183
 184static inline pte_t pte_mkdirty(pte_t pte)
 185{
 186        pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
 187
 188        if (pte_write(pte))
 189                pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
 190
 191        return pte;
 192}
 193
 194static inline pte_t pte_wrprotect(pte_t pte)
 195{
 196        /*
 197         * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
 198         * clear), set the PTE_DIRTY bit.
 199         */
 200        if (pte_hw_dirty(pte))
 201                pte = pte_mkdirty(pte);
 202
 203        pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
 204        pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
 205        return pte;
 206}
 207
 208static inline pte_t pte_mkold(pte_t pte)
 209{
 210        return clear_pte_bit(pte, __pgprot(PTE_AF));
 211}
 212
 213static inline pte_t pte_mkyoung(pte_t pte)
 214{
 215        return set_pte_bit(pte, __pgprot(PTE_AF));
 216}
 217
 218static inline pte_t pte_mkspecial(pte_t pte)
 219{
 220        return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
 221}
 222
 223static inline pte_t pte_mkcont(pte_t pte)
 224{
 225        pte = set_pte_bit(pte, __pgprot(PTE_CONT));
 226        return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
 227}
 228
 229static inline pte_t pte_mknoncont(pte_t pte)
 230{
 231        return clear_pte_bit(pte, __pgprot(PTE_CONT));
 232}
 233
 234static inline pte_t pte_mkpresent(pte_t pte)
 235{
 236        return set_pte_bit(pte, __pgprot(PTE_VALID));
 237}
 238
 239static inline pmd_t pmd_mkcont(pmd_t pmd)
 240{
 241        return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
 242}
 243
 244static inline pte_t pte_mkdevmap(pte_t pte)
 245{
 246        return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
 247}
 248
 249static inline void set_pte(pte_t *ptep, pte_t pte)
 250{
 251        WRITE_ONCE(*ptep, pte);
 252
 253        /*
 254         * Only if the new pte is valid and kernel, otherwise TLB maintenance
 255         * or update_mmu_cache() have the necessary barriers.
 256         */
 257        if (pte_valid_not_user(pte)) {
 258                dsb(ishst);
 259                isb();
 260        }
 261}
 262
 263extern void __sync_icache_dcache(pte_t pteval);
 264
 265/*
 266 * PTE bits configuration in the presence of hardware Dirty Bit Management
 267 * (PTE_WRITE == PTE_DBM):
 268 *
 269 * Dirty  Writable | PTE_RDONLY  PTE_WRITE  PTE_DIRTY (sw)
 270 *   0      0      |   1           0          0
 271 *   0      1      |   1           1          0
 272 *   1      0      |   1           0          1
 273 *   1      1      |   0           1          x
 274 *
 275 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
 276 * the page fault mechanism. Checking the dirty status of a pte becomes:
 277 *
 278 *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
 279 */
 280
 281static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
 282                                           pte_t pte)
 283{
 284        pte_t old_pte;
 285
 286        if (!IS_ENABLED(CONFIG_DEBUG_VM))
 287                return;
 288
 289        old_pte = READ_ONCE(*ptep);
 290
 291        if (!pte_valid(old_pte) || !pte_valid(pte))
 292                return;
 293        if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
 294                return;
 295
 296        /*
 297         * Check for potential race with hardware updates of the pte
 298         * (ptep_set_access_flags safely changes valid ptes without going
 299         * through an invalid entry).
 300         */
 301        VM_WARN_ONCE(!pte_young(pte),
 302                     "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
 303                     __func__, pte_val(old_pte), pte_val(pte));
 304        VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
 305                     "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
 306                     __func__, pte_val(old_pte), pte_val(pte));
 307}
 308
 309static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 310                              pte_t *ptep, pte_t pte)
 311{
 312        if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
 313                __sync_icache_dcache(pte);
 314
 315        /*
 316         * If the PTE would provide user space access to the tags associated
 317         * with it then ensure that the MTE tags are synchronised.  Although
 318         * pte_access_permitted() returns false for exec only mappings, they
 319         * don't expose tags (instruction fetches don't check tags).
 320         */
 321        if (system_supports_mte() && pte_access_permitted(pte, false) &&
 322            !pte_special(pte)) {
 323                pte_t old_pte = READ_ONCE(*ptep);
 324                /*
 325                 * We only need to synchronise if the new PTE has tags enabled
 326                 * or if swapping in (in which case another mapping may have
 327                 * set tags in the past even if this PTE isn't tagged).
 328                 * (!pte_none() && !pte_present()) is an open coded version of
 329                 * is_swap_pte()
 330                 */
 331                if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte)))
 332                        mte_sync_tags(old_pte, pte);
 333        }
 334
 335        __check_racy_pte_update(mm, ptep, pte);
 336
 337        set_pte(ptep, pte);
 338}
 339
 340/*
 341 * Huge pte definitions.
 342 */
 343#define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
 344
 345/*
 346 * Hugetlb definitions.
 347 */
 348#define HUGE_MAX_HSTATE         4
 349#define HPAGE_SHIFT             PMD_SHIFT
 350#define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
 351#define HPAGE_MASK              (~(HPAGE_SIZE - 1))
 352#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
 353
 354static inline pte_t pgd_pte(pgd_t pgd)
 355{
 356        return __pte(pgd_val(pgd));
 357}
 358
 359static inline pte_t p4d_pte(p4d_t p4d)
 360{
 361        return __pte(p4d_val(p4d));
 362}
 363
 364static inline pte_t pud_pte(pud_t pud)
 365{
 366        return __pte(pud_val(pud));
 367}
 368
 369static inline pud_t pte_pud(pte_t pte)
 370{
 371        return __pud(pte_val(pte));
 372}
 373
 374static inline pmd_t pud_pmd(pud_t pud)
 375{
 376        return __pmd(pud_val(pud));
 377}
 378
 379static inline pte_t pmd_pte(pmd_t pmd)
 380{
 381        return __pte(pmd_val(pmd));
 382}
 383
 384static inline pmd_t pte_pmd(pte_t pte)
 385{
 386        return __pmd(pte_val(pte));
 387}
 388
 389static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
 390{
 391        return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
 392}
 393
 394static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
 395{
 396        return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
 397}
 398
 399#ifdef CONFIG_NUMA_BALANCING
 400/*
 401 * See the comment in include/linux/pgtable.h
 402 */
 403static inline int pte_protnone(pte_t pte)
 404{
 405        return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
 406}
 407
 408static inline int pmd_protnone(pmd_t pmd)
 409{
 410        return pte_protnone(pmd_pte(pmd));
 411}
 412#endif
 413
 414#define pmd_present_invalid(pmd)     (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
 415
 416static inline int pmd_present(pmd_t pmd)
 417{
 418        return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
 419}
 420
 421/*
 422 * THP definitions.
 423 */
 424
 425#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 426static inline int pmd_trans_huge(pmd_t pmd)
 427{
 428        return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
 429}
 430#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 431
 432#define pmd_dirty(pmd)          pte_dirty(pmd_pte(pmd))
 433#define pmd_young(pmd)          pte_young(pmd_pte(pmd))
 434#define pmd_valid(pmd)          pte_valid(pmd_pte(pmd))
 435#define pmd_cont(pmd)           pte_cont(pmd_pte(pmd))
 436#define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
 437#define pmd_mkold(pmd)          pte_pmd(pte_mkold(pmd_pte(pmd)))
 438#define pmd_mkwrite(pmd)        pte_pmd(pte_mkwrite(pmd_pte(pmd)))
 439#define pmd_mkclean(pmd)        pte_pmd(pte_mkclean(pmd_pte(pmd)))
 440#define pmd_mkdirty(pmd)        pte_pmd(pte_mkdirty(pmd_pte(pmd)))
 441#define pmd_mkyoung(pmd)        pte_pmd(pte_mkyoung(pmd_pte(pmd)))
 442
 443static inline pmd_t pmd_mkinvalid(pmd_t pmd)
 444{
 445        pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
 446        pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
 447
 448        return pmd;
 449}
 450
 451#define pmd_thp_or_huge(pmd)    (pmd_huge(pmd) || pmd_trans_huge(pmd))
 452
 453#define pmd_write(pmd)          pte_write(pmd_pte(pmd))
 454
 455#define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
 456
 457#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 458#define pmd_devmap(pmd)         pte_devmap(pmd_pte(pmd))
 459#endif
 460static inline pmd_t pmd_mkdevmap(pmd_t pmd)
 461{
 462        return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
 463}
 464
 465#define __pmd_to_phys(pmd)      __pte_to_phys(pmd_pte(pmd))
 466#define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
 467#define pmd_pfn(pmd)            ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
 468#define pfn_pmd(pfn,prot)       __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 469#define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
 470
 471#define pud_young(pud)          pte_young(pud_pte(pud))
 472#define pud_mkyoung(pud)        pte_pud(pte_mkyoung(pud_pte(pud)))
 473#define pud_write(pud)          pte_write(pud_pte(pud))
 474
 475#define pud_mkhuge(pud)         (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
 476
 477#define __pud_to_phys(pud)      __pte_to_phys(pud_pte(pud))
 478#define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
 479#define pud_pfn(pud)            ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
 480#define pfn_pud(pfn,prot)       __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 481
 482#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
 483#define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud))
 484
 485#define __p4d_to_phys(p4d)      __pte_to_phys(p4d_pte(p4d))
 486#define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
 487
 488#define __pgd_to_phys(pgd)      __pte_to_phys(pgd_pte(pgd))
 489#define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
 490
 491#define __pgprot_modify(prot,mask,bits) \
 492        __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
 493
 494#define pgprot_nx(prot) \
 495        __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
 496
 497/*
 498 * Mark the prot value as uncacheable and unbufferable.
 499 */
 500#define pgprot_noncached(prot) \
 501        __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
 502#define pgprot_writecombine(prot) \
 503        __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
 504#define pgprot_device(prot) \
 505        __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
 506#define pgprot_tagged(prot) \
 507        __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
 508#define pgprot_mhp      pgprot_tagged
 509/*
 510 * DMA allocations for non-coherent devices use what the Arm architecture calls
 511 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
 512 * and merging of writes.  This is different from "Device-nGnR[nE]" memory which
 513 * is intended for MMIO and thus forbids speculation, preserves access size,
 514 * requires strict alignment and can also force write responses to come from the
 515 * endpoint.
 516 */
 517#define pgprot_dmacoherent(prot) \
 518        __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
 519                        PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
 520
 521#define __HAVE_PHYS_MEM_ACCESS_PROT
 522struct file;
 523extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 524                                     unsigned long size, pgprot_t vma_prot);
 525
 526#define pmd_none(pmd)           (!pmd_val(pmd))
 527
 528#define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 529                                 PMD_TYPE_TABLE)
 530#define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 531                                 PMD_TYPE_SECT)
 532#define pmd_leaf(pmd)           pmd_sect(pmd)
 533#define pmd_bad(pmd)            (!pmd_table(pmd))
 534
 535#define pmd_leaf_size(pmd)      (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
 536#define pte_leaf_size(pte)      (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
 537
 538#if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
 539static inline bool pud_sect(pud_t pud) { return false; }
 540static inline bool pud_table(pud_t pud) { return true; }
 541#else
 542#define pud_sect(pud)           ((pud_val(pud) & PUD_TYPE_MASK) == \
 543                                 PUD_TYPE_SECT)
 544#define pud_table(pud)          ((pud_val(pud) & PUD_TYPE_MASK) == \
 545                                 PUD_TYPE_TABLE)
 546#endif
 547
 548extern pgd_t init_pg_dir[PTRS_PER_PGD];
 549extern pgd_t init_pg_end[];
 550extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 551extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 552extern pgd_t idmap_pg_end[];
 553extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
 554extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
 555
 556extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
 557
 558static inline bool in_swapper_pgdir(void *addr)
 559{
 560        return ((unsigned long)addr & PAGE_MASK) ==
 561                ((unsigned long)swapper_pg_dir & PAGE_MASK);
 562}
 563
 564static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 565{
 566#ifdef __PAGETABLE_PMD_FOLDED
 567        if (in_swapper_pgdir(pmdp)) {
 568                set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
 569                return;
 570        }
 571#endif /* __PAGETABLE_PMD_FOLDED */
 572
 573        WRITE_ONCE(*pmdp, pmd);
 574
 575        if (pmd_valid(pmd)) {
 576                dsb(ishst);
 577                isb();
 578        }
 579}
 580
 581static inline void pmd_clear(pmd_t *pmdp)
 582{
 583        set_pmd(pmdp, __pmd(0));
 584}
 585
 586static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
 587{
 588        return __pmd_to_phys(pmd);
 589}
 590
 591static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 592{
 593        return (unsigned long)__va(pmd_page_paddr(pmd));
 594}
 595
 596/* Find an entry in the third-level page table. */
 597#define pte_offset_phys(dir,addr)       (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
 598
 599#define pte_set_fixmap(addr)            ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
 600#define pte_set_fixmap_offset(pmd, addr)        pte_set_fixmap(pte_offset_phys(pmd, addr))
 601#define pte_clear_fixmap()              clear_fixmap(FIX_PTE)
 602
 603#define pmd_page(pmd)                   phys_to_page(__pmd_to_phys(pmd))
 604
 605/* use ONLY for statically allocated translation tables */
 606#define pte_offset_kimg(dir,addr)       ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
 607
 608/*
 609 * Conversion functions: convert a page and protection to a page entry,
 610 * and a page entry and page directory to the page they refer to.
 611 */
 612#define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
 613
 614#if CONFIG_PGTABLE_LEVELS > 2
 615
 616#define pmd_ERROR(e)    \
 617        pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
 618
 619#define pud_none(pud)           (!pud_val(pud))
 620#define pud_bad(pud)            (!pud_table(pud))
 621#define pud_present(pud)        pte_present(pud_pte(pud))
 622#define pud_leaf(pud)           pud_sect(pud)
 623#define pud_valid(pud)          pte_valid(pud_pte(pud))
 624
 625static inline void set_pud(pud_t *pudp, pud_t pud)
 626{
 627#ifdef __PAGETABLE_PUD_FOLDED
 628        if (in_swapper_pgdir(pudp)) {
 629                set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
 630                return;
 631        }
 632#endif /* __PAGETABLE_PUD_FOLDED */
 633
 634        WRITE_ONCE(*pudp, pud);
 635
 636        if (pud_valid(pud)) {
 637                dsb(ishst);
 638                isb();
 639        }
 640}
 641
 642static inline void pud_clear(pud_t *pudp)
 643{
 644        set_pud(pudp, __pud(0));
 645}
 646
 647static inline phys_addr_t pud_page_paddr(pud_t pud)
 648{
 649        return __pud_to_phys(pud);
 650}
 651
 652static inline pmd_t *pud_pgtable(pud_t pud)
 653{
 654        return (pmd_t *)__va(pud_page_paddr(pud));
 655}
 656
 657/* Find an entry in the second-level page table. */
 658#define pmd_offset_phys(dir, addr)      (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
 659
 660#define pmd_set_fixmap(addr)            ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
 661#define pmd_set_fixmap_offset(pud, addr)        pmd_set_fixmap(pmd_offset_phys(pud, addr))
 662#define pmd_clear_fixmap()              clear_fixmap(FIX_PMD)
 663
 664#define pud_page(pud)                   phys_to_page(__pud_to_phys(pud))
 665
 666/* use ONLY for statically allocated translation tables */
 667#define pmd_offset_kimg(dir,addr)       ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
 668
 669#else
 670
 671#define pud_page_paddr(pud)     ({ BUILD_BUG(); 0; })
 672
 673/* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
 674#define pmd_set_fixmap(addr)            NULL
 675#define pmd_set_fixmap_offset(pudp, addr)       ((pmd_t *)pudp)
 676#define pmd_clear_fixmap()
 677
 678#define pmd_offset_kimg(dir,addr)       ((pmd_t *)dir)
 679
 680#endif  /* CONFIG_PGTABLE_LEVELS > 2 */
 681
 682#if CONFIG_PGTABLE_LEVELS > 3
 683
 684#define pud_ERROR(e)    \
 685        pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
 686
 687#define p4d_none(p4d)           (!p4d_val(p4d))
 688#define p4d_bad(p4d)            (!(p4d_val(p4d) & 2))
 689#define p4d_present(p4d)        (p4d_val(p4d))
 690
 691static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
 692{
 693        if (in_swapper_pgdir(p4dp)) {
 694                set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
 695                return;
 696        }
 697
 698        WRITE_ONCE(*p4dp, p4d);
 699        dsb(ishst);
 700        isb();
 701}
 702
 703static inline void p4d_clear(p4d_t *p4dp)
 704{
 705        set_p4d(p4dp, __p4d(0));
 706}
 707
 708static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
 709{
 710        return __p4d_to_phys(p4d);
 711}
 712
 713static inline pud_t *p4d_pgtable(p4d_t p4d)
 714{
 715        return (pud_t *)__va(p4d_page_paddr(p4d));
 716}
 717
 718/* Find an entry in the first-level page table. */
 719#define pud_offset_phys(dir, addr)      (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
 720
 721#define pud_set_fixmap(addr)            ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
 722#define pud_set_fixmap_offset(p4d, addr)        pud_set_fixmap(pud_offset_phys(p4d, addr))
 723#define pud_clear_fixmap()              clear_fixmap(FIX_PUD)
 724
 725#define p4d_page(p4d)           pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
 726
 727/* use ONLY for statically allocated translation tables */
 728#define pud_offset_kimg(dir,addr)       ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
 729
 730#else
 731
 732#define p4d_page_paddr(p4d)     ({ BUILD_BUG(); 0;})
 733#define pgd_page_paddr(pgd)     ({ BUILD_BUG(); 0;})
 734
 735/* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
 736#define pud_set_fixmap(addr)            NULL
 737#define pud_set_fixmap_offset(pgdp, addr)       ((pud_t *)pgdp)
 738#define pud_clear_fixmap()
 739
 740#define pud_offset_kimg(dir,addr)       ((pud_t *)dir)
 741
 742#endif  /* CONFIG_PGTABLE_LEVELS > 3 */
 743
 744#define pgd_ERROR(e)    \
 745        pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
 746
 747#define pgd_set_fixmap(addr)    ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
 748#define pgd_clear_fixmap()      clear_fixmap(FIX_PGD)
 749
 750static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 751{
 752        /*
 753         * Normal and Normal-Tagged are two different memory types and indices
 754         * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
 755         */
 756        const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
 757                              PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
 758                              PTE_ATTRINDX_MASK;
 759        /* preserve the hardware dirty information */
 760        if (pte_hw_dirty(pte))
 761                pte = pte_mkdirty(pte);
 762        pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
 763        return pte;
 764}
 765
 766static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
 767{
 768        return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
 769}
 770
 771#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 772extern int ptep_set_access_flags(struct vm_area_struct *vma,
 773                                 unsigned long address, pte_t *ptep,
 774                                 pte_t entry, int dirty);
 775
 776#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 777#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
 778static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
 779                                        unsigned long address, pmd_t *pmdp,
 780                                        pmd_t entry, int dirty)
 781{
 782        return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
 783}
 784
 785static inline int pud_devmap(pud_t pud)
 786{
 787        return 0;
 788}
 789
 790static inline int pgd_devmap(pgd_t pgd)
 791{
 792        return 0;
 793}
 794#endif
 795
 796/*
 797 * Atomic pte/pmd modifications.
 798 */
 799#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 800static inline int __ptep_test_and_clear_young(pte_t *ptep)
 801{
 802        pte_t old_pte, pte;
 803
 804        pte = READ_ONCE(*ptep);
 805        do {
 806                old_pte = pte;
 807                pte = pte_mkold(pte);
 808                pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
 809                                               pte_val(old_pte), pte_val(pte));
 810        } while (pte_val(pte) != pte_val(old_pte));
 811
 812        return pte_young(pte);
 813}
 814
 815static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
 816                                            unsigned long address,
 817                                            pte_t *ptep)
 818{
 819        return __ptep_test_and_clear_young(ptep);
 820}
 821
 822#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 823static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 824                                         unsigned long address, pte_t *ptep)
 825{
 826        int young = ptep_test_and_clear_young(vma, address, ptep);
 827
 828        if (young) {
 829                /*
 830                 * We can elide the trailing DSB here since the worst that can
 831                 * happen is that a CPU continues to use the young entry in its
 832                 * TLB and we mistakenly reclaim the associated page. The
 833                 * window for such an event is bounded by the next
 834                 * context-switch, which provides a DSB to complete the TLB
 835                 * invalidation.
 836                 */
 837                flush_tlb_page_nosync(vma, address);
 838        }
 839
 840        return young;
 841}
 842
 843#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 844#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
 845static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
 846                                            unsigned long address,
 847                                            pmd_t *pmdp)
 848{
 849        return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
 850}
 851#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 852
 853#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 854static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 855                                       unsigned long address, pte_t *ptep)
 856{
 857        return __pte(xchg_relaxed(&pte_val(*ptep), 0));
 858}
 859
 860#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 861#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
 862static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
 863                                            unsigned long address, pmd_t *pmdp)
 864{
 865        return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
 866}
 867#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 868
 869/*
 870 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
 871 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
 872 */
 873#define __HAVE_ARCH_PTEP_SET_WRPROTECT
 874static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
 875{
 876        pte_t old_pte, pte;
 877
 878        pte = READ_ONCE(*ptep);
 879        do {
 880                old_pte = pte;
 881                pte = pte_wrprotect(pte);
 882                pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
 883                                               pte_val(old_pte), pte_val(pte));
 884        } while (pte_val(pte) != pte_val(old_pte));
 885}
 886
 887#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 888#define __HAVE_ARCH_PMDP_SET_WRPROTECT
 889static inline void pmdp_set_wrprotect(struct mm_struct *mm,
 890                                      unsigned long address, pmd_t *pmdp)
 891{
 892        ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
 893}
 894
 895#define pmdp_establish pmdp_establish
 896static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
 897                unsigned long address, pmd_t *pmdp, pmd_t pmd)
 898{
 899        return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
 900}
 901#endif
 902
 903/*
 904 * Encode and decode a swap entry:
 905 *      bits 0-1:       present (must be zero)
 906 *      bits 2-7:       swap type
 907 *      bits 8-57:      swap offset
 908 *      bit  58:        PTE_PROT_NONE (must be zero)
 909 */
 910#define __SWP_TYPE_SHIFT        2
 911#define __SWP_TYPE_BITS         6
 912#define __SWP_OFFSET_BITS       50
 913#define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 914#define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
 915#define __SWP_OFFSET_MASK       ((1UL << __SWP_OFFSET_BITS) - 1)
 916
 917#define __swp_type(x)           (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
 918#define __swp_offset(x)         (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
 919#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
 920
 921#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 922#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
 923
 924#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
 925#define __pmd_to_swp_entry(pmd)         ((swp_entry_t) { pmd_val(pmd) })
 926#define __swp_entry_to_pmd(swp)         __pmd((swp).val)
 927#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
 928
 929/*
 930 * Ensure that there are not more swap files than can be encoded in the kernel
 931 * PTEs.
 932 */
 933#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
 934
 935extern int kern_addr_valid(unsigned long addr);
 936
 937#ifdef CONFIG_ARM64_MTE
 938
 939#define __HAVE_ARCH_PREPARE_TO_SWAP
 940static inline int arch_prepare_to_swap(struct page *page)
 941{
 942        if (system_supports_mte())
 943                return mte_save_tags(page);
 944        return 0;
 945}
 946
 947#define __HAVE_ARCH_SWAP_INVALIDATE
 948static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
 949{
 950        if (system_supports_mte())
 951                mte_invalidate_tags(type, offset);
 952}
 953
 954static inline void arch_swap_invalidate_area(int type)
 955{
 956        if (system_supports_mte())
 957                mte_invalidate_tags_area(type);
 958}
 959
 960#define __HAVE_ARCH_SWAP_RESTORE
 961static inline void arch_swap_restore(swp_entry_t entry, struct page *page)
 962{
 963        if (system_supports_mte() && mte_restore_tags(entry, page))
 964                set_bit(PG_mte_tagged, &page->flags);
 965}
 966
 967#endif /* CONFIG_ARM64_MTE */
 968
 969/*
 970 * On AArch64, the cache coherency is handled via the set_pte_at() function.
 971 */
 972static inline void update_mmu_cache(struct vm_area_struct *vma,
 973                                    unsigned long addr, pte_t *ptep)
 974{
 975        /*
 976         * We don't do anything here, so there's a very small chance of
 977         * us retaking a user fault which we just fixed up. The alternative
 978         * is doing a dsb(ishst), but that penalises the fastpath.
 979         */
 980}
 981
 982#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 983
 984#ifdef CONFIG_ARM64_PA_BITS_52
 985#define phys_to_ttbr(addr)      (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
 986#else
 987#define phys_to_ttbr(addr)      (addr)
 988#endif
 989
 990/*
 991 * On arm64 without hardware Access Flag, copying from user will fail because
 992 * the pte is old and cannot be marked young. So we always end up with zeroed
 993 * page after fork() + CoW for pfn mappings. We don't always have a
 994 * hardware-managed access flag on arm64.
 995 */
 996static inline bool arch_faults_on_old_pte(void)
 997{
 998        WARN_ON(preemptible());
 999
1000        return !cpu_has_hw_af();

1001}
1002#define arch_faults_on_old_pte          arch_faults_on_old_pte
1003
1004/*
1005 * Experimentally, it's cheap to set the access flag in hardware and we
1006 * benefit from prefaulting mappings as 'old' to start with.
1007 */
1008static inline bool arch_wants_old_prefaulted_pte(void)
1009{
1010        return !arch_faults_on_old_pte();
1011}
1012#define arch_wants_old_prefaulted_pte   arch_wants_old_prefaulted_pte
1013
1014static inline pgprot_t arch_filter_pgprot(pgprot_t prot)
1015{
1016        if (cpus_have_const_cap(ARM64_HAS_EPAN))
1017                return prot;
1018
1019        if (pgprot_val(prot) != pgprot_val(PAGE_EXECONLY))
1020                return prot;
1021
1022        return PAGE_READONLY_EXEC;
1023}
1024
1025
1026#endif /* !__ASSEMBLY__ */
1027
1028#endif /* __ASM_PGTABLE_H */
1029