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8#ifndef __ASM_PROCESSOR_H
9#define __ASM_PROCESSOR_H
10
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13
14
15
16
17#define NET_IP_ALIGN 0
18
19#define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
20#define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
21
22#define MTE_CTRL_TCF_SYNC (1UL << 16)
23#define MTE_CTRL_TCF_ASYNC (1UL << 17)
24
25#ifndef __ASSEMBLY__
26
27#include <linux/build_bug.h>
28#include <linux/cache.h>
29#include <linux/init.h>
30#include <linux/stddef.h>
31#include <linux/string.h>
32#include <linux/thread_info.h>
33
34#include <vdso/processor.h>
35
36#include <asm/alternative.h>
37#include <asm/cpufeature.h>
38#include <asm/hw_breakpoint.h>
39#include <asm/kasan.h>
40#include <asm/lse.h>
41#include <asm/pgtable-hwdef.h>
42#include <asm/pointer_auth.h>
43#include <asm/ptrace.h>
44#include <asm/spectre.h>
45#include <asm/types.h>
46
47
48
49
50
51
52#define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
53#define TASK_SIZE_64 (UL(1) << vabits_actual)
54#define TASK_SIZE_MAX (UL(1) << VA_BITS)
55
56#ifdef CONFIG_COMPAT
57#if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
58
59
60
61
62#define TASK_SIZE_32 UL(0x100000000)
63#else
64#define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
65#endif
66#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
67 TASK_SIZE_32 : TASK_SIZE_64)
68#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
69 TASK_SIZE_32 : TASK_SIZE_64)
70#define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
71 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
72#else
73#define TASK_SIZE TASK_SIZE_64
74#define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
75#endif
76
77#ifdef CONFIG_ARM64_FORCE_52BIT
78#define STACK_TOP_MAX TASK_SIZE_64
79#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
80#else
81#define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
82#define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
83#endif
84
85#ifdef CONFIG_COMPAT
86#define AARCH32_VECTORS_BASE 0xffff0000
87#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
88 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
89#else
90#define STACK_TOP STACK_TOP_MAX
91#endif
92
93#ifndef CONFIG_ARM64_FORCE_52BIT
94#define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
95 DEFAULT_MAP_WINDOW)
96
97#define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
98 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
99 base)
100#endif
101
102extern phys_addr_t arm64_dma_phys_limit;
103#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
104
105struct debug_info {
106#ifdef CONFIG_HAVE_HW_BREAKPOINT
107
108 int suspended_step;
109
110 int bps_disabled;
111 int wps_disabled;
112
113 struct perf_event *hbp_break[ARM_MAX_BRP];
114 struct perf_event *hbp_watch[ARM_MAX_WRP];
115#endif
116};
117
118struct cpu_context {
119 unsigned long x19;
120 unsigned long x20;
121 unsigned long x21;
122 unsigned long x22;
123 unsigned long x23;
124 unsigned long x24;
125 unsigned long x25;
126 unsigned long x26;
127 unsigned long x27;
128 unsigned long x28;
129 unsigned long fp;
130 unsigned long sp;
131 unsigned long pc;
132};
133
134struct thread_struct {
135 struct cpu_context cpu_context;
136
137
138
139
140
141
142 struct {
143 unsigned long tp_value;
144 unsigned long tp2_value;
145 struct user_fpsimd_state fpsimd_state;
146 } uw;
147
148 unsigned int fpsimd_cpu;
149 void *sve_state;
150 unsigned int sve_vl;
151 unsigned int sve_vl_onexec;
152 unsigned long fault_address;
153 unsigned long fault_code;
154 struct debug_info debug;
155#ifdef CONFIG_ARM64_PTR_AUTH
156 struct ptrauth_keys_user keys_user;
157#ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
158 struct ptrauth_keys_kernel keys_kernel;
159#endif
160#endif
161#ifdef CONFIG_ARM64_MTE
162 u64 mte_ctrl;
163#endif
164 u64 sctlr_user;
165};
166
167#define SCTLR_USER_MASK \
168 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \
169 SCTLR_EL1_TCF0_MASK)
170
171static inline void arch_thread_struct_whitelist(unsigned long *offset,
172 unsigned long *size)
173{
174
175 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
176 sizeof_field(struct thread_struct, uw.tp_value) +
177 sizeof_field(struct thread_struct, uw.tp2_value) +
178 sizeof_field(struct thread_struct, uw.fpsimd_state));
179
180 *offset = offsetof(struct thread_struct, uw);
181 *size = sizeof_field(struct thread_struct, uw);
182}
183
184#ifdef CONFIG_COMPAT
185#define task_user_tls(t) \
186({ \
187 unsigned long *__tls; \
188 if (is_compat_thread(task_thread_info(t))) \
189 __tls = &(t)->thread.uw.tp2_value; \
190 else \
191 __tls = &(t)->thread.uw.tp_value; \
192 __tls; \
193 })
194#else
195#define task_user_tls(t) (&(t)->thread.uw.tp_value)
196#endif
197
198
199void tls_preserve_current_state(void);
200
201#define INIT_THREAD { \
202 .fpsimd_cpu = NR_CPUS, \
203}
204
205static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
206{
207 memset(regs, 0, sizeof(*regs));
208 forget_syscall(regs);
209 regs->pc = pc;
210
211 if (system_uses_irq_prio_masking())
212 regs->pmr_save = GIC_PRIO_IRQON;
213}
214
215static inline void start_thread(struct pt_regs *regs, unsigned long pc,
216 unsigned long sp)
217{
218 start_thread_common(regs, pc);
219 regs->pstate = PSR_MODE_EL0t;
220 spectre_v4_enable_task_mitigation(current);
221 regs->sp = sp;
222}
223
224#ifdef CONFIG_COMPAT
225static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
226 unsigned long sp)
227{
228 start_thread_common(regs, pc);
229 regs->pstate = PSR_AA32_MODE_USR;
230 if (pc & 1)
231 regs->pstate |= PSR_AA32_T_BIT;
232
233#ifdef __AARCH64EB__
234 regs->pstate |= PSR_AA32_E_BIT;
235#endif
236
237 spectre_v4_enable_task_mitigation(current);
238 regs->compat_sp = sp;
239}
240#endif
241
242static inline bool is_ttbr0_addr(unsigned long addr)
243{
244
245 return addr < TASK_SIZE;
246}
247
248static inline bool is_ttbr1_addr(unsigned long addr)
249{
250
251 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
252}
253
254
255struct task_struct;
256
257
258extern void release_thread(struct task_struct *);
259
260unsigned long get_wchan(struct task_struct *p);
261
262void update_sctlr_el1(u64 sctlr);
263
264
265extern struct task_struct *cpu_switch_to(struct task_struct *prev,
266 struct task_struct *next);
267
268#define task_pt_regs(p) \
269 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
270
271#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
272#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
273
274
275
276
277#define ARCH_HAS_PREFETCH
278static inline void prefetch(const void *ptr)
279{
280 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
281}
282
283#define ARCH_HAS_PREFETCHW
284static inline void prefetchw(const void *ptr)
285{
286 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
287}
288
289#define ARCH_HAS_SPINLOCK_PREFETCH
290static inline void spin_lock_prefetch(const void *ptr)
291{
292 asm volatile(ARM64_LSE_ATOMIC_INSN(
293 "prfm pstl1strm, %a0",
294 "nop") : : "p" (ptr));
295}
296
297extern unsigned long __ro_after_init signal_minsigstksz;
298extern void __init minsigstksz_setup(void);
299
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306
307
308
309#include <asm/fpsimd.h>
310
311
312#define SVE_SET_VL(arg) sve_set_current_vl(arg)
313#define SVE_GET_VL() sve_get_current_vl()
314
315
316#define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
317
318
319#define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \
320 ptrauth_set_enabled_keys(tsk, keys, enabled)
321#define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
322
323#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
324
325long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
326long get_tagged_addr_ctrl(struct task_struct *task);
327#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
328#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
329#endif
330
331
332
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334
335
336
337
338#define current_top_of_stack() \
339({ \
340 struct stack_info _info; \
341 BUG_ON(!on_accessible_stack(current, current_stack_pointer, 1, &_info)); \
342 _info.high; \
343})
344#define on_thread_stack() (on_task_stack(current, current_stack_pointer, 1, NULL))
345
346#endif
347#endif
348