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8#include <linux/arm-smccc.h>
9#include <linux/types.h>
10#include <linux/cpu.h>
11#include <asm/cpu.h>
12#include <asm/cputype.h>
13#include <asm/cpufeature.h>
14#include <asm/kvm_asm.h>
15#include <asm/smp_plat.h>
16
17static bool __maybe_unused
18is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
19{
20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
22
23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
24 if (!is_midr_in_range(midr, &entry->midr_range))
25 return false;
26
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
31 return false;
32
33 return true;
34}
35
36static bool __maybe_unused
37is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
38 int scope)
39{
40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
42}
43
44static bool __maybe_unused
45is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
46{
47 u32 model;
48
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
54
55 return model == entry->midr_range.model;
56}
57
58static bool
59has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
60 int scope)
61{
62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
65
66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
67
68
69
70
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73
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81
82
83
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
86
87 return (ctr_real != sys) && (ctr_raw != sys);
88}
89
90static void
91cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
92{
93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
94 bool enable_uct_trap = false;
95
96
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
99 enable_uct_trap = true;
100
101
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
104
105 if (enable_uct_trap)
106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
107}
108
109#ifdef CONFIG_ARM64_ERRATUM_1463225
110static bool
111has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
112 int scope)
113{
114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
115}
116#endif
117
118static void __maybe_unused
119cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
120{
121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
122}
123
124#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
125 .matches = is_affected_midr_range, \
126 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
127
128#define CAP_MIDR_ALL_VERSIONS(model) \
129 .matches = is_affected_midr_range, \
130 .midr_range = MIDR_ALL_VERSIONS(model)
131
132#define MIDR_FIXED(rev, revidr_mask) \
133 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
134
135#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
136 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
137 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
138
139#define CAP_MIDR_RANGE_LIST(list) \
140 .matches = is_affected_midr_range_list, \
141 .midr_range_list = list
142
143
144#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
145 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
146
147
148#define ERRATA_MIDR_REV(model, var, rev) \
149 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
150
151
152#define ERRATA_MIDR_ALL_VERSIONS(model) \
153 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
154 CAP_MIDR_ALL_VERSIONS(model)
155
156
157#define ERRATA_MIDR_RANGE_LIST(midr_list) \
158 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
159 CAP_MIDR_RANGE_LIST(midr_list)
160
161static const __maybe_unused struct midr_range tx2_family_cpus[] = {
162 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
163 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
164 {},
165};
166
167static bool __maybe_unused
168needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
169 int scope)
170{
171 int i;
172
173 if (!is_affected_midr_range_list(entry, scope) ||
174 !is_hyp_mode_available())
175 return false;
176
177 for_each_possible_cpu(i) {
178 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
179 return true;
180 }
181
182 return false;
183}
184
185static bool __maybe_unused
186has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
187 int scope)
188{
189 u32 midr = read_cpuid_id();
190 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
191 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
192
193 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
194 return is_midr_in_range(midr, &range) && has_dic;
195}
196
197#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
198static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
199#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
200 {
201 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
202 },
203 {
204 .midr_range.model = MIDR_QCOM_KRYO,
205 .matches = is_kryo_midr,
206 },
207#endif
208#ifdef CONFIG_ARM64_ERRATUM_1286807
209 {
210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
211 },
212#endif
213 {},
214};
215#endif
216
217#ifdef CONFIG_CAVIUM_ERRATUM_27456
218const struct midr_range cavium_erratum_27456_cpus[] = {
219
220 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
221
222 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
223 {},
224};
225#endif
226
227#ifdef CONFIG_CAVIUM_ERRATUM_30115
228static const struct midr_range cavium_erratum_30115_cpus[] = {
229
230 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
231
232 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
233
234 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
235 {},
236};
237#endif
238
239#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
240static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
241 {
242 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
243 },
244 {
245 .midr_range.model = MIDR_QCOM_KRYO,
246 .matches = is_kryo_midr,
247 },
248 {},
249};
250#endif
251
252#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
253static const struct midr_range workaround_clean_cache[] = {
254#if defined(CONFIG_ARM64_ERRATUM_826319) || \
255 defined(CONFIG_ARM64_ERRATUM_827319) || \
256 defined(CONFIG_ARM64_ERRATUM_824069)
257
258 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
259#endif
260#ifdef CONFIG_ARM64_ERRATUM_819472
261
262 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
263#endif
264 {},
265};
266#endif
267
268#ifdef CONFIG_ARM64_ERRATUM_1418040
269
270
271
272
273static const struct midr_range erratum_1418040_list[] = {
274
275 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
276
277 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
278
279 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
280 {},
281};
282#endif
283
284#ifdef CONFIG_ARM64_ERRATUM_845719
285static const struct midr_range erratum_845719_list[] = {
286
287 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
288
289 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
290
291 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
292 {},
293};
294#endif
295
296#ifdef CONFIG_ARM64_ERRATUM_843419
297static const struct arm64_cpu_capabilities erratum_843419_list[] = {
298 {
299
300 .matches = is_affected_midr_range,
301 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
302 MIDR_FIXED(0x4, BIT(8)),
303 },
304 {
305
306 .matches = is_affected_midr_range,
307 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
308 },
309 {},
310};
311#endif
312
313#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
314static const struct midr_range erratum_speculative_at_list[] = {
315#ifdef CONFIG_ARM64_ERRATUM_1165522
316
317 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
318#endif
319#ifdef CONFIG_ARM64_ERRATUM_1319367
320 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
321 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
322#endif
323#ifdef CONFIG_ARM64_ERRATUM_1530923
324
325 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
326
327 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
328#endif
329 {},
330};
331#endif
332
333#ifdef CONFIG_ARM64_ERRATUM_1463225
334static const struct midr_range erratum_1463225[] = {
335
336 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
337
338 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
339 {},
340};
341#endif
342
343const struct arm64_cpu_capabilities arm64_errata[] = {
344#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
345 {
346 .desc = "ARM errata 826319, 827319, 824069, or 819472",
347 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
348 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
349 .cpu_enable = cpu_enable_cache_maint_trap,
350 },
351#endif
352#ifdef CONFIG_ARM64_ERRATUM_832075
353 {
354
355 .desc = "ARM erratum 832075",
356 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
357 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
358 0, 0,
359 1, 2),
360 },
361#endif
362#ifdef CONFIG_ARM64_ERRATUM_834220
363 {
364
365 .desc = "ARM erratum 834220",
366 .capability = ARM64_WORKAROUND_834220,
367 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
368 0, 0,
369 1, 2),
370 },
371#endif
372#ifdef CONFIG_ARM64_ERRATUM_843419
373 {
374 .desc = "ARM erratum 843419",
375 .capability = ARM64_WORKAROUND_843419,
376 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
377 .matches = cpucap_multi_entry_cap_matches,
378 .match_list = erratum_843419_list,
379 },
380#endif
381#ifdef CONFIG_ARM64_ERRATUM_845719
382 {
383 .desc = "ARM erratum 845719",
384 .capability = ARM64_WORKAROUND_845719,
385 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
386 },
387#endif
388#ifdef CONFIG_CAVIUM_ERRATUM_23154
389 {
390
391 .desc = "Cavium erratum 23154",
392 .capability = ARM64_WORKAROUND_CAVIUM_23154,
393 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
394 },
395#endif
396#ifdef CONFIG_CAVIUM_ERRATUM_27456
397 {
398 .desc = "Cavium erratum 27456",
399 .capability = ARM64_WORKAROUND_CAVIUM_27456,
400 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
401 },
402#endif
403#ifdef CONFIG_CAVIUM_ERRATUM_30115
404 {
405 .desc = "Cavium erratum 30115",
406 .capability = ARM64_WORKAROUND_CAVIUM_30115,
407 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
408 },
409#endif
410 {
411 .desc = "Mismatched cache type (CTR_EL0)",
412 .capability = ARM64_MISMATCHED_CACHE_TYPE,
413 .matches = has_mismatched_cache_type,
414 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
415 .cpu_enable = cpu_enable_trap_ctr_access,
416 },
417#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
418 {
419 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
420 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
421 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
422 .matches = cpucap_multi_entry_cap_matches,
423 .match_list = qcom_erratum_1003_list,
424 },
425#endif
426#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
427 {
428 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
429 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
430 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
431 .matches = cpucap_multi_entry_cap_matches,
432 .match_list = arm64_repeat_tlbi_list,
433 },
434#endif
435#ifdef CONFIG_ARM64_ERRATUM_858921
436 {
437
438 .desc = "ARM erratum 858921",
439 .capability = ARM64_WORKAROUND_858921,
440 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
441 },
442#endif
443 {
444 .desc = "Spectre-v2",
445 .capability = ARM64_SPECTRE_V2,
446 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
447 .matches = has_spectre_v2,
448 .cpu_enable = spectre_v2_enable_mitigation,
449 },
450#ifdef CONFIG_RANDOMIZE_BASE
451 {
452
453 .desc = "Spectre-v3a",
454 .capability = ARM64_SPECTRE_V3A,
455 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
456 .matches = has_spectre_v3a,
457 .cpu_enable = spectre_v3a_enable_mitigation,
458 },
459#endif
460 {
461 .desc = "Spectre-v4",
462 .capability = ARM64_SPECTRE_V4,
463 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
464 .matches = has_spectre_v4,
465 .cpu_enable = spectre_v4_enable_mitigation,
466 },
467#ifdef CONFIG_ARM64_ERRATUM_1418040
468 {
469 .desc = "ARM erratum 1418040",
470 .capability = ARM64_WORKAROUND_1418040,
471 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
472
473
474
475
476
477 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
478 },
479#endif
480#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
481 {
482 .desc = "ARM errata 1165522, 1319367, or 1530923",
483 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
484 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
485 },
486#endif
487#ifdef CONFIG_ARM64_ERRATUM_1463225
488 {
489 .desc = "ARM erratum 1463225",
490 .capability = ARM64_WORKAROUND_1463225,
491 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
492 .matches = has_cortex_a76_erratum_1463225,
493 .midr_range_list = erratum_1463225,
494 },
495#endif
496#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
497 {
498 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
499 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
500 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
501 .matches = needs_tx2_tvm_workaround,
502 },
503 {
504 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
505 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
506 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
507 },
508#endif
509#ifdef CONFIG_ARM64_ERRATUM_1542419
510 {
511
512 .desc = "ARM erratum 1542419 (kernel portion)",
513 .capability = ARM64_WORKAROUND_1542419,
514 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
515 .matches = has_neoverse_n1_erratum_1542419,
516 .cpu_enable = cpu_enable_trap_ctr_access,
517 },
518#endif
519#ifdef CONFIG_ARM64_ERRATUM_1508412
520 {
521
522 .desc = "ARM erratum 1508412 (kernel portion)",
523 .capability = ARM64_WORKAROUND_1508412,
524 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
525 0, 0,
526 1, 0),
527 },
528#endif
529#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
530 {
531
532 .desc = "NVIDIA Carmel CNP erratum",
533 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
534 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
535 },
536#endif
537 {
538 }
539};
540