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63#define pr_fmt(fmt) "CPU features: " fmt
64
65#include <linux/bsearch.h>
66#include <linux/cpumask.h>
67#include <linux/crash_dump.h>
68#include <linux/sort.h>
69#include <linux/stop_machine.h>
70#include <linux/sysfs.h>
71#include <linux/types.h>
72#include <linux/minmax.h>
73#include <linux/mm.h>
74#include <linux/cpu.h>
75#include <linux/kasan.h>
76#include <asm/cpu.h>
77#include <asm/cpufeature.h>
78#include <asm/cpu_ops.h>
79#include <asm/fpsimd.h>
80#include <asm/insn.h>
81#include <asm/kvm_host.h>
82#include <asm/mmu_context.h>
83#include <asm/mte.h>
84#include <asm/processor.h>
85#include <asm/smp.h>
86#include <asm/sysreg.h>
87#include <asm/traps.h>
88#include <asm/virt.h>
89
90
91static unsigned long elf_hwcap __read_mostly;
92
93#ifdef CONFIG_COMPAT
94#define COMPAT_ELF_HWCAP_DEFAULT \
95 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
96 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
97 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
98 COMPAT_HWCAP_LPAE)
99unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
100unsigned int compat_elf_hwcap2 __read_mostly;
101#endif
102
103DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
104EXPORT_SYMBOL(cpu_hwcaps);
105static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
106
107
108DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
109
110bool arm64_use_ng_mappings = false;
111EXPORT_SYMBOL(arm64_use_ng_mappings);
112
113
114
115
116
117static bool __read_mostly allow_mismatched_32bit_el0;
118
119
120
121
122
123DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
124
125
126
127
128
129static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
130
131
132
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135
136
137
138
139
140DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
141EXPORT_SYMBOL(arm64_const_caps_ready);
142static inline void finalize_system_capabilities(void)
143{
144 static_branch_enable(&arm64_const_caps_ready);
145}
146
147void dump_cpu_features(void)
148{
149
150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
151}
152
153DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
154EXPORT_SYMBOL(cpu_hwcap_keys);
155
156#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
157 { \
158 .sign = SIGNED, \
159 .visible = VISIBLE, \
160 .strict = STRICT, \
161 .type = TYPE, \
162 .shift = SHIFT, \
163 .width = WIDTH, \
164 .safe_val = SAFE_VAL, \
165 }
166
167
168#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
169 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
170
171
172#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
173 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
174
175#define ARM64_FTR_END \
176 { \
177 .width = 0, \
178 }
179
180static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
181
182static bool __system_matches_cap(unsigned int n);
183
184
185
186
187
188static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
203 ARM64_FTR_END,
204};
205
206static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
216 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
221 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
223 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
225 ARM64_FTR_END,
226};
227
228static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
236 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
239 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
240 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
245 ARM64_FTR_END,
246};
247
248static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
256 ARM64_FTR_END,
257};
258
259static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
277 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
278 ARM64_FTR_END,
279};
280
281static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
285
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299
300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
303
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310 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
311 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
313
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
315
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
319
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321
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323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
324 ARM64_FTR_END,
325};
326
327static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
338 ARM64_FTR_END,
339};
340
341static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
357 ARM64_FTR_END,
358};
359
360static const struct arm64_ftr_bits ftr_ctr[] = {
361 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),
362 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
363 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
364 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
365 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
367
368
369
370
371
372 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT),
373 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
374 ARM64_FTR_END,
375};
376
377static struct arm64_ftr_override __ro_after_init no_override = { };
378
379struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
380 .name = "SYS_CTR_EL0",
381 .ftr_bits = ftr_ctr,
382 .override = &no_override,
383};
384
385static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
386 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
391 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
394 ARM64_FTR_END,
395};
396
397static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
398 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
403
404
405
406
407 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
409 ARM64_FTR_END,
410};
411
412static const struct arm64_ftr_bits ftr_mvfr2[] = {
413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
415 ARM64_FTR_END,
416};
417
418static const struct arm64_ftr_bits ftr_dczid[] = {
419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
421 ARM64_FTR_END,
422};
423
424static const struct arm64_ftr_bits ftr_gmid[] = {
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
426 ARM64_FTR_END,
427};
428
429static const struct arm64_ftr_bits ftr_id_isar0[] = {
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
437 ARM64_FTR_END,
438};
439
440static const struct arm64_ftr_bits ftr_id_isar5[] = {
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
447 ARM64_FTR_END,
448};
449
450static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
458
459
460
461
462
463
464
465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
466 ARM64_FTR_END,
467};
468
469static const struct arm64_ftr_bits ftr_id_isar4[] = {
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
478 ARM64_FTR_END,
479};
480
481static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
483 ARM64_FTR_END,
484};
485
486static const struct arm64_ftr_bits ftr_id_isar6[] = {
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
494 ARM64_FTR_END,
495};
496
497static const struct arm64_ftr_bits ftr_id_pfr0[] = {
498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
504 ARM64_FTR_END,
505};
506
507static const struct arm64_ftr_bits ftr_id_pfr1[] = {
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
516 ARM64_FTR_END,
517};
518
519static const struct arm64_ftr_bits ftr_id_pfr2[] = {
520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
522 ARM64_FTR_END,
523};
524
525static const struct arm64_ftr_bits ftr_id_dfr0[] = {
526
527 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
534 ARM64_FTR_END,
535};
536
537static const struct arm64_ftr_bits ftr_id_dfr1[] = {
538 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
539 ARM64_FTR_END,
540};
541
542static const struct arm64_ftr_bits ftr_zcr[] = {
543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
544 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),
545 ARM64_FTR_END,
546};
547
548
549
550
551
552
553
554static const struct arm64_ftr_bits ftr_generic_32bits[] = {
555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
563 ARM64_FTR_END,
564};
565
566
567static const struct arm64_ftr_bits ftr_single32[] = {
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
569 ARM64_FTR_END,
570};
571
572static const struct arm64_ftr_bits ftr_raz[] = {
573 ARM64_FTR_END,
574};
575
576#define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \
577 .sys_id = id, \
578 .reg = &(struct arm64_ftr_reg){ \
579 .name = #id, \
580 .override = (ovr), \
581 .ftr_bits = &((table)[0]), \
582 }}
583
584#define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override)
585
586struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
587struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
588struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
589
590static const struct __ftr_reg_entry {
591 u32 sys_id;
592 struct arm64_ftr_reg *reg;
593} arm64_ftr_regs[] = {
594
595
596 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
597 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
598 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
599 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
600 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
601 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
602 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
603
604
605 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
606 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
607 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
608 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
609 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
610 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
611 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
612 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
613
614
615 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
616 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
617 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
618 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
619 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
620 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
621
622
623 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
624 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
625 &id_aa64pfr1_override),
626 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
627
628
629 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
630 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
631
632
633 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
634 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
635 &id_aa64isar1_override),
636
637
638 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
639 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
640 &id_aa64mmfr1_override),
641 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
642
643
644 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
645
646
647 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
648
649
650 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
651 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
652
653
654 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
655};
656
657static int search_cmp_ftr_reg(const void *id, const void *regp)
658{
659 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
660}
661
662
663
664
665
666
667
668
669
670
671
672static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
673{
674 const struct __ftr_reg_entry *ret;
675
676 ret = bsearch((const void *)(unsigned long)sys_id,
677 arm64_ftr_regs,
678 ARRAY_SIZE(arm64_ftr_regs),
679 sizeof(arm64_ftr_regs[0]),
680 search_cmp_ftr_reg);
681 if (ret)
682 return ret->reg;
683 return NULL;
684}
685
686
687
688
689
690
691
692
693static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
694{
695 struct arm64_ftr_reg *reg;
696
697 reg = get_arm64_ftr_reg_nowarn(sys_id);
698
699
700
701
702
703 WARN_ON(!reg);
704 return reg;
705}
706
707static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
708 s64 ftr_val)
709{
710 u64 mask = arm64_ftr_mask(ftrp);
711
712 reg &= ~mask;
713 reg |= (ftr_val << ftrp->shift) & mask;
714 return reg;
715}
716
717static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
718 s64 cur)
719{
720 s64 ret = 0;
721
722 switch (ftrp->type) {
723 case FTR_EXACT:
724 ret = ftrp->safe_val;
725 break;
726 case FTR_LOWER_SAFE:
727 ret = min(new, cur);
728 break;
729 case FTR_HIGHER_OR_ZERO_SAFE:
730 if (!cur || !new)
731 break;
732 fallthrough;
733 case FTR_HIGHER_SAFE:
734 ret = max(new, cur);
735 break;
736 default:
737 BUG();
738 }
739
740 return ret;
741}
742
743static void __init sort_ftr_regs(void)
744{
745 unsigned int i;
746
747 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
748 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
749 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
750 unsigned int j = 0;
751
752
753
754
755
756 for (; ftr_bits->width != 0; ftr_bits++, j++) {
757 unsigned int width = ftr_reg->ftr_bits[j].width;
758 unsigned int shift = ftr_reg->ftr_bits[j].shift;
759 unsigned int prev_shift;
760
761 WARN((shift + width) > 64,
762 "%s has invalid feature at shift %d\n",
763 ftr_reg->name, shift);
764
765
766
767
768
769 if (j == 0)
770 continue;
771
772 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
773 WARN((shift + width) > prev_shift,
774 "%s has feature overlap at shift %d\n",
775 ftr_reg->name, shift);
776 }
777
778
779
780
781
782 if (i == 0)
783 continue;
784
785
786
787
788
789 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
790 }
791}
792
793
794
795
796
797
798
799static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
800{
801 u64 val = 0;
802 u64 strict_mask = ~0x0ULL;
803 u64 user_mask = 0;
804 u64 valid_mask = 0;
805
806 const struct arm64_ftr_bits *ftrp;
807 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
808
809 if (!reg)
810 return;
811
812 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
813 u64 ftr_mask = arm64_ftr_mask(ftrp);
814 s64 ftr_new = arm64_ftr_value(ftrp, new);
815 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
816
817 if ((ftr_mask & reg->override->mask) == ftr_mask) {
818 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
819 char *str = NULL;
820
821 if (ftr_ovr != tmp) {
822
823 reg->override->mask &= ~ftr_mask;
824 reg->override->val &= ~ftr_mask;
825 tmp = ftr_ovr;
826 str = "ignoring override";
827 } else if (ftr_new != tmp) {
828
829 ftr_new = tmp;
830 str = "forced";
831 } else if (ftr_ovr == tmp) {
832
833 str = "already set";
834 }
835
836 if (str)
837 pr_warn("%s[%d:%d]: %s to %llx\n",
838 reg->name,
839 ftrp->shift + ftrp->width - 1,
840 ftrp->shift, str, tmp);
841 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
842 reg->override->val &= ~ftr_mask;
843 pr_warn("%s[%d:%d]: impossible override, ignored\n",
844 reg->name,
845 ftrp->shift + ftrp->width - 1,
846 ftrp->shift);
847 }
848
849 val = arm64_ftr_set_value(ftrp, val, ftr_new);
850
851 valid_mask |= ftr_mask;
852 if (!ftrp->strict)
853 strict_mask &= ~ftr_mask;
854 if (ftrp->visible)
855 user_mask |= ftr_mask;
856 else
857 reg->user_val = arm64_ftr_set_value(ftrp,
858 reg->user_val,
859 ftrp->safe_val);
860 }
861
862 val &= valid_mask;
863
864 reg->sys_val = val;
865 reg->strict_mask = strict_mask;
866 reg->user_mask = user_mask;
867}
868
869extern const struct arm64_cpu_capabilities arm64_errata[];
870static const struct arm64_cpu_capabilities arm64_features[];
871
872static void __init
873init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
874{
875 for (; caps->matches; caps++) {
876 if (WARN(caps->capability >= ARM64_NCAPS,
877 "Invalid capability %d\n", caps->capability))
878 continue;
879 if (WARN(cpu_hwcaps_ptrs[caps->capability],
880 "Duplicate entry for capability %d\n",
881 caps->capability))
882 continue;
883 cpu_hwcaps_ptrs[caps->capability] = caps;
884 }
885}
886
887static void __init init_cpu_hwcaps_indirect_list(void)
888{
889 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
890 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
891}
892
893static void __init setup_boot_cpu_capabilities(void);
894
895static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
896{
897 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
898 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
899 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
900 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
901 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
902 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
903 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
904 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
905 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
906 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
907 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
908 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
909 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
910 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
911 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
912 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
913 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
914 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
915 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
916 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
917 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
918}
919
920void __init init_cpu_features(struct cpuinfo_arm64 *info)
921{
922
923 sort_ftr_regs();
924
925 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
926 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
927 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
928 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
929 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
930 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
931 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
932 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
933 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
934 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
935 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
936 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
937 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
938
939 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
940 init_32bit_cpu_features(&info->aarch32);
941
942 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
943 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
944 sve_init_vq_map();
945 }
946
947 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
948 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
949
950
951
952
953
954 init_cpu_hwcaps_indirect_list();
955
956
957
958
959
960 setup_boot_cpu_capabilities();
961}
962
963static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
964{
965 const struct arm64_ftr_bits *ftrp;
966
967 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
968 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
969 s64 ftr_new = arm64_ftr_value(ftrp, new);
970
971 if (ftr_cur == ftr_new)
972 continue;
973
974 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
975 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
976 }
977
978}
979
980static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
981{
982 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
983
984 if (!regp)
985 return 0;
986
987 update_cpu_ftr_reg(regp, val);
988 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
989 return 0;
990 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
991 regp->name, boot, cpu, val);
992 return 1;
993}
994
995static void relax_cpu_ftr_reg(u32 sys_id, int field)
996{
997 const struct arm64_ftr_bits *ftrp;
998 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
999
1000 if (!regp)
1001 return;
1002
1003 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1004 if (ftrp->shift == field) {
1005 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1006 break;
1007 }
1008 }
1009
1010
1011 WARN_ON(!ftrp->width);
1012}
1013
1014static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1015 struct cpuinfo_arm64 *boot)
1016{
1017 static bool boot_cpu_32bit_regs_overridden = false;
1018
1019 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1020 return;
1021
1022 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1023 return;
1024
1025 boot->aarch32 = info->aarch32;
1026 init_32bit_cpu_features(&boot->aarch32);
1027 boot_cpu_32bit_regs_overridden = true;
1028}
1029
1030static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1031 struct cpuinfo_32bit *boot)
1032{
1033 int taint = 0;
1034 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1035
1036
1037
1038
1039
1040 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1041 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1042 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1043 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1044 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1045 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1046 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1047 }
1048
1049 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1050 info->reg_id_dfr0, boot->reg_id_dfr0);
1051 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1052 info->reg_id_dfr1, boot->reg_id_dfr1);
1053 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1054 info->reg_id_isar0, boot->reg_id_isar0);
1055 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1056 info->reg_id_isar1, boot->reg_id_isar1);
1057 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1058 info->reg_id_isar2, boot->reg_id_isar2);
1059 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1060 info->reg_id_isar3, boot->reg_id_isar3);
1061 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1062 info->reg_id_isar4, boot->reg_id_isar4);
1063 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1064 info->reg_id_isar5, boot->reg_id_isar5);
1065 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1066 info->reg_id_isar6, boot->reg_id_isar6);
1067
1068
1069
1070
1071
1072
1073 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1074 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1075 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1076 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1077 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1078 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1079 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1080 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1081 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1082 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1083 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1084 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1085 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1086 info->reg_id_pfr0, boot->reg_id_pfr0);
1087 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1088 info->reg_id_pfr1, boot->reg_id_pfr1);
1089 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1090 info->reg_id_pfr2, boot->reg_id_pfr2);
1091 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1092 info->reg_mvfr0, boot->reg_mvfr0);
1093 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1094 info->reg_mvfr1, boot->reg_mvfr1);
1095 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1096 info->reg_mvfr2, boot->reg_mvfr2);
1097
1098 return taint;
1099}
1100
1101
1102
1103
1104
1105
1106void update_cpu_features(int cpu,
1107 struct cpuinfo_arm64 *info,
1108 struct cpuinfo_arm64 *boot)
1109{
1110 int taint = 0;
1111
1112
1113
1114
1115
1116
1117 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1118 info->reg_ctr, boot->reg_ctr);
1119
1120
1121
1122
1123
1124
1125 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1126 info->reg_dczid, boot->reg_dczid);
1127
1128
1129 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1130 info->reg_cntfrq, boot->reg_cntfrq);
1131
1132
1133
1134
1135
1136
1137
1138 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1139 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1140 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1141 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1142
1143
1144
1145
1146 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1147 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1148 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1149 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1150
1151
1152
1153
1154
1155
1156 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1157 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1158 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1159 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1160 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1161 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1162
1163 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1164 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1165 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1166 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1167
1168 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1169 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1170
1171 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1172 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1173 info->reg_zcr, boot->reg_zcr);
1174
1175
1176 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1177 !system_capabilities_finalized())
1178 sve_update_vq_map();
1179 }
1180
1181
1182
1183
1184
1185
1186 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1187 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1188 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1189 info->reg_gmid, boot->reg_gmid);
1190 }
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1201 lazy_init_32bit_cpu_features(info, boot);
1202 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1203 &boot->aarch32);
1204 }
1205
1206
1207
1208
1209
1210 if (taint) {
1211 pr_warn_once("Unsupported CPU feature variation detected.\n");
1212 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1213 }
1214}
1215
1216u64 read_sanitised_ftr_reg(u32 id)
1217{
1218 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1219
1220 if (!regp)
1221 return 0;
1222 return regp->sys_val;
1223}
1224EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1225
1226#define read_sysreg_case(r) \
1227 case r: val = read_sysreg_s(r); break;
1228
1229
1230
1231
1232
1233u64 __read_sysreg_by_encoding(u32 sys_id)
1234{
1235 struct arm64_ftr_reg *regp;
1236 u64 val;
1237
1238 switch (sys_id) {
1239 read_sysreg_case(SYS_ID_PFR0_EL1);
1240 read_sysreg_case(SYS_ID_PFR1_EL1);
1241 read_sysreg_case(SYS_ID_PFR2_EL1);
1242 read_sysreg_case(SYS_ID_DFR0_EL1);
1243 read_sysreg_case(SYS_ID_DFR1_EL1);
1244 read_sysreg_case(SYS_ID_MMFR0_EL1);
1245 read_sysreg_case(SYS_ID_MMFR1_EL1);
1246 read_sysreg_case(SYS_ID_MMFR2_EL1);
1247 read_sysreg_case(SYS_ID_MMFR3_EL1);
1248 read_sysreg_case(SYS_ID_MMFR4_EL1);
1249 read_sysreg_case(SYS_ID_MMFR5_EL1);
1250 read_sysreg_case(SYS_ID_ISAR0_EL1);
1251 read_sysreg_case(SYS_ID_ISAR1_EL1);
1252 read_sysreg_case(SYS_ID_ISAR2_EL1);
1253 read_sysreg_case(SYS_ID_ISAR3_EL1);
1254 read_sysreg_case(SYS_ID_ISAR4_EL1);
1255 read_sysreg_case(SYS_ID_ISAR5_EL1);
1256 read_sysreg_case(SYS_ID_ISAR6_EL1);
1257 read_sysreg_case(SYS_MVFR0_EL1);
1258 read_sysreg_case(SYS_MVFR1_EL1);
1259 read_sysreg_case(SYS_MVFR2_EL1);
1260
1261 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1262 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1263 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1264 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1265 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1266 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1267 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1268 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1269 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1270 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1271
1272 read_sysreg_case(SYS_CNTFRQ_EL0);
1273 read_sysreg_case(SYS_CTR_EL0);
1274 read_sysreg_case(SYS_DCZID_EL0);
1275
1276 default:
1277 BUG();
1278 return 0;
1279 }
1280
1281 regp = get_arm64_ftr_reg(sys_id);
1282 if (regp) {
1283 val &= ~regp->override->mask;
1284 val |= (regp->override->val & regp->override->mask);
1285 }
1286
1287 return val;
1288}
1289
1290#include <linux/irqchip/arm-gic-v3.h>
1291
1292static bool
1293feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1294{
1295 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1296
1297 return val >= entry->min_field_value;
1298}
1299
1300static bool
1301has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1302{
1303 u64 val;
1304
1305 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1306 if (scope == SCOPE_SYSTEM)
1307 val = read_sanitised_ftr_reg(entry->sys_reg);
1308 else
1309 val = __read_sysreg_by_encoding(entry->sys_reg);
1310
1311 return feature_matches(val, entry);
1312}
1313
1314const struct cpumask *system_32bit_el0_cpumask(void)
1315{
1316 if (!system_supports_32bit_el0())
1317 return cpu_none_mask;
1318
1319 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1320 return cpu_32bit_el0_mask;
1321
1322 return cpu_possible_mask;
1323}
1324
1325static int __init parse_32bit_el0_param(char *str)
1326{
1327 allow_mismatched_32bit_el0 = true;
1328 return 0;
1329}
1330early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1331
1332static ssize_t aarch32_el0_show(struct device *dev,
1333 struct device_attribute *attr, char *buf)
1334{
1335 const struct cpumask *mask = system_32bit_el0_cpumask();
1336
1337 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1338}
1339static const DEVICE_ATTR_RO(aarch32_el0);
1340
1341static int __init aarch32_el0_sysfs_init(void)
1342{
1343 if (!allow_mismatched_32bit_el0)
1344 return 0;
1345
1346 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1347}
1348device_initcall(aarch32_el0_sysfs_init);
1349
1350static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1351{
1352 if (!has_cpuid_feature(entry, scope))
1353 return allow_mismatched_32bit_el0;
1354
1355 if (scope == SCOPE_SYSTEM)
1356 pr_info("detected: 32-bit EL0 Support\n");
1357
1358 return true;
1359}
1360
1361static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1362{
1363 bool has_sre;
1364
1365 if (!has_cpuid_feature(entry, scope))
1366 return false;
1367
1368 has_sre = gic_enable_sre();
1369 if (!has_sre)
1370 pr_warn_once("%s present but disabled by higher exception level\n",
1371 entry->desc);
1372
1373 return has_sre;
1374}
1375
1376static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1377{
1378 u32 midr = read_cpuid_id();
1379
1380
1381 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1382 MIDR_CPU_VAR_REV(0, 0),
1383 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1384}
1385
1386static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1387{
1388 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1389
1390 return cpuid_feature_extract_signed_field(pfr0,
1391 ID_AA64PFR0_FP_SHIFT) < 0;
1392}
1393
1394static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1395 int scope)
1396{
1397 u64 ctr;
1398
1399 if (scope == SCOPE_SYSTEM)
1400 ctr = arm64_ftr_reg_ctrel0.sys_val;
1401 else
1402 ctr = read_cpuid_effective_cachetype();
1403
1404 return ctr & BIT(CTR_IDC_SHIFT);
1405}
1406
1407static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1408{
1409
1410
1411
1412
1413
1414
1415 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1416 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1417}
1418
1419static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1420 int scope)
1421{
1422 u64 ctr;
1423
1424 if (scope == SCOPE_SYSTEM)
1425 ctr = arm64_ftr_reg_ctrel0.sys_val;
1426 else
1427 ctr = read_cpuid_cachetype();
1428
1429 return ctr & BIT(CTR_DIC_SHIFT);
1430}
1431
1432static bool __maybe_unused
1433has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1434{
1435
1436
1437
1438
1439
1440 if (is_kdump_kernel())
1441 return false;
1442
1443 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1444 return false;
1445
1446 return has_cpuid_feature(entry, scope);
1447}
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458bool kaslr_requires_kpti(void)
1459{
1460 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1461 return false;
1462
1463
1464
1465
1466
1467 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1468 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1469 if (cpuid_feature_extract_unsigned_field(mmfr2,
1470 ID_AA64MMFR2_E0PD_SHIFT))
1471 return false;
1472 }
1473
1474
1475
1476
1477
1478 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1479 extern const struct midr_range cavium_erratum_27456_cpus[];
1480
1481 if (is_midr_in_range_list(read_cpuid_id(),
1482 cavium_erratum_27456_cpus))
1483 return false;
1484 }
1485
1486 return kaslr_offset() > 0;
1487}
1488
1489static bool __meltdown_safe = true;
1490static int __kpti_forced;
1491
1492static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1493 int scope)
1494{
1495
1496 static const struct midr_range kpti_safe_list[] = {
1497 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1498 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1499 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1500 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1501 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1502 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1503 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1504 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1505 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1506 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1507 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1508 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1509 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1510 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1511 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1512 { }
1513 };
1514 char const *str = "kpti command line option";
1515 bool meltdown_safe;
1516
1517 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1518
1519
1520 if (has_cpuid_feature(entry, scope))
1521 meltdown_safe = true;
1522
1523 if (!meltdown_safe)
1524 __meltdown_safe = false;
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1536 str = "ARM64_WORKAROUND_CAVIUM_27456";
1537 __kpti_forced = -1;
1538 }
1539
1540
1541 if (kaslr_requires_kpti()) {
1542 if (!__kpti_forced) {
1543 str = "KASLR";
1544 __kpti_forced = 1;
1545 }
1546 }
1547
1548 if (cpu_mitigations_off() && !__kpti_forced) {
1549 str = "mitigations=off";
1550 __kpti_forced = -1;
1551 }
1552
1553 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1554 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1555 return false;
1556 }
1557
1558
1559 if (__kpti_forced) {
1560 pr_info_once("kernel page table isolation forced %s by %s\n",
1561 __kpti_forced > 0 ? "ON" : "OFF", str);
1562 return __kpti_forced > 0;
1563 }
1564
1565 return !meltdown_safe;
1566}
1567
1568#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1569static void __nocfi
1570kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1571{
1572 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1573 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1574 kpti_remap_fn *remap_fn;
1575
1576 int cpu = smp_processor_id();
1577
1578
1579
1580
1581
1582
1583 if (arm64_use_ng_mappings)
1584 return;
1585
1586 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1587
1588 cpu_install_idmap();
1589 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1590 cpu_uninstall_idmap();
1591
1592 if (!cpu)
1593 arm64_use_ng_mappings = true;
1594}
1595#else
1596static void
1597kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1598{
1599}
1600#endif
1601
1602static int __init parse_kpti(char *str)
1603{
1604 bool enabled;
1605 int ret = strtobool(str, &enabled);
1606
1607 if (ret)
1608 return ret;
1609
1610 __kpti_forced = enabled ? 1 : -1;
1611 return 0;
1612}
1613early_param("kpti", parse_kpti);
1614
1615#ifdef CONFIG_ARM64_HW_AFDBM
1616static inline void __cpu_enable_hw_dbm(void)
1617{
1618 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1619
1620 write_sysreg(tcr, tcr_el1);
1621 isb();
1622 local_flush_tlb_all();
1623}
1624
1625static bool cpu_has_broken_dbm(void)
1626{
1627
1628 static const struct midr_range cpus[] = {
1629#ifdef CONFIG_ARM64_ERRATUM_1024718
1630 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1631
1632 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1633#endif
1634 {},
1635 };
1636
1637 return is_midr_in_range_list(read_cpuid_id(), cpus);
1638}
1639
1640static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1641{
1642 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1643 !cpu_has_broken_dbm();
1644}
1645
1646static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1647{
1648 if (cpu_can_use_dbm(cap))
1649 __cpu_enable_hw_dbm();
1650}
1651
1652static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1653 int __unused)
1654{
1655 static bool detected = false;
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673 if (!detected && cpu_can_use_dbm(cap)) {
1674 detected = true;
1675 pr_info("detected: Hardware dirty bit management\n");
1676 }
1677
1678 return true;
1679}
1680
1681#endif
1682
1683#ifdef CONFIG_ARM64_AMU_EXTN
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694static struct cpumask amu_cpus __read_mostly;
1695
1696bool cpu_has_amu_feat(int cpu)
1697{
1698 return cpumask_test_cpu(cpu, &amu_cpus);
1699}
1700
1701int get_cpu_with_amu_feat(void)
1702{
1703 return cpumask_any(&amu_cpus);
1704}
1705
1706static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1707{
1708 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1709 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1710 smp_processor_id());
1711 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1712 update_freq_counters_refs();
1713 }
1714}
1715
1716static bool has_amu(const struct arm64_cpu_capabilities *cap,
1717 int __unused)
1718{
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732 return true;
1733}
1734#else
1735int get_cpu_with_amu_feat(void)
1736{
1737 return nr_cpu_ids;
1738}
1739#endif
1740
1741static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1742{
1743 return is_kernel_in_hyp_mode();
1744}
1745
1746static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1747{
1748
1749
1750
1751
1752
1753
1754
1755
1756 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1757 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1758}
1759
1760static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1761{
1762 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1763
1764
1765 WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val));
1766}
1767
1768#ifdef CONFIG_ARM64_PAN
1769static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1770{
1771
1772
1773
1774
1775 WARN_ON_ONCE(in_interrupt());
1776
1777 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1778 set_pstate_pan(1);
1779}
1780#endif
1781
1782#ifdef CONFIG_ARM64_RAS_EXTN
1783static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1784{
1785
1786 write_sysreg_s(0, SYS_DISR_EL1);
1787}
1788#endif
1789
1790#ifdef CONFIG_ARM64_PTR_AUTH
1791static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1792{
1793 int boot_val, sec_val;
1794
1795
1796 WARN_ON(scope == SCOPE_SYSTEM);
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1808 entry->field_pos, entry->sign);
1809 if (scope & SCOPE_BOOT_CPU)
1810 return boot_val >= entry->min_field_value;
1811
1812 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1813 entry->field_pos, entry->sign);
1814 return sec_val == boot_val;
1815}
1816
1817static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1818 int scope)
1819{
1820 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1821 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1822}
1823
1824static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1825 int __unused)
1826{
1827 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1828 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1829}
1830#endif
1831
1832#ifdef CONFIG_ARM64_E0PD
1833static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1834{
1835 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1836 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1837}
1838#endif
1839
1840#ifdef CONFIG_ARM64_PSEUDO_NMI
1841static bool enable_pseudo_nmi;
1842
1843static int __init early_enable_pseudo_nmi(char *p)
1844{
1845 return strtobool(p, &enable_pseudo_nmi);
1846}
1847early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1848
1849static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1850 int scope)
1851{
1852 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1853}
1854#endif
1855
1856#ifdef CONFIG_ARM64_BTI
1857static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1858{
1859
1860
1861
1862
1863
1864
1865
1866 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1867 isb();
1868}
1869#endif
1870
1871#ifdef CONFIG_ARM64_MTE
1872static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1873{
1874 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
1875 isb();
1876
1877
1878
1879
1880
1881 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1882 mte_clear_page_tags(lm_alias(empty_zero_page));
1883
1884 kasan_init_hw_tags_cpu();
1885}
1886#endif
1887
1888#ifdef CONFIG_KVM
1889static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1890{
1891 if (kvm_get_mode() != KVM_MODE_PROTECTED)
1892 return false;
1893
1894 if (is_kernel_in_hyp_mode()) {
1895 pr_warn("Protected KVM not available with VHE\n");
1896 return false;
1897 }
1898
1899 return true;
1900}
1901#endif
1902
1903
1904static bool
1905cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1906{
1907 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1908}
1909
1910static bool
1911cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1912{
1913 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1914}
1915
1916static bool
1917cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1918{
1919 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1920}
1921
1922static const struct arm64_cpu_capabilities arm64_features[] = {
1923 {
1924 .desc = "GIC system register CPU interface",
1925 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1926 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1927 .matches = has_useable_gicv3_cpuif,
1928 .sys_reg = SYS_ID_AA64PFR0_EL1,
1929 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1930 .sign = FTR_UNSIGNED,
1931 .min_field_value = 1,
1932 },
1933#ifdef CONFIG_ARM64_PAN
1934 {
1935 .desc = "Privileged Access Never",
1936 .capability = ARM64_HAS_PAN,
1937 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1938 .matches = has_cpuid_feature,
1939 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1940 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1941 .sign = FTR_UNSIGNED,
1942 .min_field_value = 1,
1943 .cpu_enable = cpu_enable_pan,
1944 },
1945#endif
1946#ifdef CONFIG_ARM64_EPAN
1947 {
1948 .desc = "Enhanced Privileged Access Never",
1949 .capability = ARM64_HAS_EPAN,
1950 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1951 .matches = has_cpuid_feature,
1952 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1953 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1954 .sign = FTR_UNSIGNED,
1955 .min_field_value = 3,
1956 },
1957#endif
1958#ifdef CONFIG_ARM64_LSE_ATOMICS
1959 {
1960 .desc = "LSE atomic instructions",
1961 .capability = ARM64_HAS_LSE_ATOMICS,
1962 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1963 .matches = has_cpuid_feature,
1964 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1965 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1966 .sign = FTR_UNSIGNED,
1967 .min_field_value = 2,
1968 },
1969#endif
1970 {
1971 .desc = "Software prefetching using PRFM",
1972 .capability = ARM64_HAS_NO_HW_PREFETCH,
1973 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1974 .matches = has_no_hw_prefetch,
1975 },
1976 {
1977 .desc = "Virtualization Host Extensions",
1978 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1979 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1980 .matches = runs_at_el2,
1981 .cpu_enable = cpu_copy_el2regs,
1982 },
1983 {
1984 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
1985 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1986 .matches = has_32bit_el0,
1987 .sys_reg = SYS_ID_AA64PFR0_EL1,
1988 .sign = FTR_UNSIGNED,
1989 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1990 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
1991 },
1992#ifdef CONFIG_KVM
1993 {
1994 .desc = "32-bit EL1 Support",
1995 .capability = ARM64_HAS_32BIT_EL1,
1996 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1997 .matches = has_cpuid_feature,
1998 .sys_reg = SYS_ID_AA64PFR0_EL1,
1999 .sign = FTR_UNSIGNED,
2000 .field_pos = ID_AA64PFR0_EL1_SHIFT,
2001 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2002 },
2003 {
2004 .desc = "Protected KVM",
2005 .capability = ARM64_KVM_PROTECTED_MODE,
2006 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2007 .matches = is_kvm_protected_mode,
2008 },
2009#endif
2010 {
2011 .desc = "Kernel page table isolation (KPTI)",
2012 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2013 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2014
2015
2016
2017
2018
2019 .sys_reg = SYS_ID_AA64PFR0_EL1,
2020 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
2021 .min_field_value = 1,
2022 .matches = unmap_kernel_at_el0,
2023 .cpu_enable = kpti_install_ng_mappings,
2024 },
2025 {
2026
2027 .capability = ARM64_HAS_NO_FPSIMD,
2028 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2029 .min_field_value = 0,
2030 .matches = has_no_fpsimd,
2031 },
2032#ifdef CONFIG_ARM64_PMEM
2033 {
2034 .desc = "Data cache clean to Point of Persistence",
2035 .capability = ARM64_HAS_DCPOP,
2036 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2037 .matches = has_cpuid_feature,
2038 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2039 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2040 .min_field_value = 1,
2041 },
2042 {
2043 .desc = "Data cache clean to Point of Deep Persistence",
2044 .capability = ARM64_HAS_DCPODP,
2045 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2046 .matches = has_cpuid_feature,
2047 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2048 .sign = FTR_UNSIGNED,
2049 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2050 .min_field_value = 2,
2051 },
2052#endif
2053#ifdef CONFIG_ARM64_SVE
2054 {
2055 .desc = "Scalable Vector Extension",
2056 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2057 .capability = ARM64_SVE,
2058 .sys_reg = SYS_ID_AA64PFR0_EL1,
2059 .sign = FTR_UNSIGNED,
2060 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2061 .min_field_value = ID_AA64PFR0_SVE,
2062 .matches = has_cpuid_feature,
2063 .cpu_enable = sve_kernel_enable,
2064 },
2065#endif
2066#ifdef CONFIG_ARM64_RAS_EXTN
2067 {
2068 .desc = "RAS Extension Support",
2069 .capability = ARM64_HAS_RAS_EXTN,
2070 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2071 .matches = has_cpuid_feature,
2072 .sys_reg = SYS_ID_AA64PFR0_EL1,
2073 .sign = FTR_UNSIGNED,
2074 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2075 .min_field_value = ID_AA64PFR0_RAS_V1,
2076 .cpu_enable = cpu_clear_disr,
2077 },
2078#endif
2079#ifdef CONFIG_ARM64_AMU_EXTN
2080 {
2081
2082
2083
2084
2085
2086
2087 .capability = ARM64_HAS_AMU_EXTN,
2088 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2089 .matches = has_amu,
2090 .sys_reg = SYS_ID_AA64PFR0_EL1,
2091 .sign = FTR_UNSIGNED,
2092 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2093 .min_field_value = ID_AA64PFR0_AMU,
2094 .cpu_enable = cpu_amu_enable,
2095 },
2096#endif
2097 {
2098 .desc = "Data cache clean to the PoU not required for I/D coherence",
2099 .capability = ARM64_HAS_CACHE_IDC,
2100 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2101 .matches = has_cache_idc,
2102 .cpu_enable = cpu_emulate_effective_ctr,
2103 },
2104 {
2105 .desc = "Instruction cache invalidation not required for I/D coherence",
2106 .capability = ARM64_HAS_CACHE_DIC,
2107 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2108 .matches = has_cache_dic,
2109 },
2110 {
2111 .desc = "Stage-2 Force Write-Back",
2112 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2113 .capability = ARM64_HAS_STAGE2_FWB,
2114 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2115 .sign = FTR_UNSIGNED,
2116 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2117 .min_field_value = 1,
2118 .matches = has_cpuid_feature,
2119 .cpu_enable = cpu_has_fwb,
2120 },
2121 {
2122 .desc = "ARMv8.4 Translation Table Level",
2123 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2124 .capability = ARM64_HAS_ARMv8_4_TTL,
2125 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2126 .sign = FTR_UNSIGNED,
2127 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2128 .min_field_value = 1,
2129 .matches = has_cpuid_feature,
2130 },
2131 {
2132 .desc = "TLB range maintenance instructions",
2133 .capability = ARM64_HAS_TLB_RANGE,
2134 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2135 .matches = has_cpuid_feature,
2136 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2137 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
2138 .sign = FTR_UNSIGNED,
2139 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
2140 },
2141#ifdef CONFIG_ARM64_HW_AFDBM
2142 {
2143
2144
2145
2146
2147
2148
2149
2150
2151 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2152 .capability = ARM64_HW_DBM,
2153 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2154 .sign = FTR_UNSIGNED,
2155 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2156 .min_field_value = 2,
2157 .matches = has_hw_dbm,
2158 .cpu_enable = cpu_enable_hw_dbm,
2159 },
2160#endif
2161 {
2162 .desc = "CRC32 instructions",
2163 .capability = ARM64_HAS_CRC32,
2164 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2165 .matches = has_cpuid_feature,
2166 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2167 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2168 .min_field_value = 1,
2169 },
2170 {
2171 .desc = "Speculative Store Bypassing Safe (SSBS)",
2172 .capability = ARM64_SSBS,
2173 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2174 .matches = has_cpuid_feature,
2175 .sys_reg = SYS_ID_AA64PFR1_EL1,
2176 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2177 .sign = FTR_UNSIGNED,
2178 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2179 },
2180#ifdef CONFIG_ARM64_CNP
2181 {
2182 .desc = "Common not Private translations",
2183 .capability = ARM64_HAS_CNP,
2184 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2185 .matches = has_useable_cnp,
2186 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2187 .sign = FTR_UNSIGNED,
2188 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2189 .min_field_value = 1,
2190 .cpu_enable = cpu_enable_cnp,
2191 },
2192#endif
2193 {
2194 .desc = "Speculation barrier (SB)",
2195 .capability = ARM64_HAS_SB,
2196 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2197 .matches = has_cpuid_feature,
2198 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2199 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2200 .sign = FTR_UNSIGNED,
2201 .min_field_value = 1,
2202 },
2203#ifdef CONFIG_ARM64_PTR_AUTH
2204 {
2205 .desc = "Address authentication (architected algorithm)",
2206 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2207 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2208 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2209 .sign = FTR_UNSIGNED,
2210 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2211 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2212 .matches = has_address_auth_cpucap,
2213 },
2214 {
2215 .desc = "Address authentication (IMP DEF algorithm)",
2216 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2217 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2218 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2219 .sign = FTR_UNSIGNED,
2220 .field_pos = ID_AA64ISAR1_API_SHIFT,
2221 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2222 .matches = has_address_auth_cpucap,
2223 },
2224 {
2225 .capability = ARM64_HAS_ADDRESS_AUTH,
2226 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2227 .matches = has_address_auth_metacap,
2228 },
2229 {
2230 .desc = "Generic authentication (architected algorithm)",
2231 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2232 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2233 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2234 .sign = FTR_UNSIGNED,
2235 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2236 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2237 .matches = has_cpuid_feature,
2238 },
2239 {
2240 .desc = "Generic authentication (IMP DEF algorithm)",
2241 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2242 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2243 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2244 .sign = FTR_UNSIGNED,
2245 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2246 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2247 .matches = has_cpuid_feature,
2248 },
2249 {
2250 .capability = ARM64_HAS_GENERIC_AUTH,
2251 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2252 .matches = has_generic_auth,
2253 },
2254#endif
2255#ifdef CONFIG_ARM64_PSEUDO_NMI
2256 {
2257
2258
2259
2260 .desc = "IRQ priority masking",
2261 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2262 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2263 .matches = can_use_gic_priorities,
2264 .sys_reg = SYS_ID_AA64PFR0_EL1,
2265 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2266 .sign = FTR_UNSIGNED,
2267 .min_field_value = 1,
2268 },
2269#endif
2270#ifdef CONFIG_ARM64_E0PD
2271 {
2272 .desc = "E0PD",
2273 .capability = ARM64_HAS_E0PD,
2274 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2275 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2276 .sign = FTR_UNSIGNED,
2277 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2278 .matches = has_cpuid_feature,
2279 .min_field_value = 1,
2280 .cpu_enable = cpu_enable_e0pd,
2281 },
2282#endif
2283#ifdef CONFIG_ARCH_RANDOM
2284 {
2285 .desc = "Random Number Generator",
2286 .capability = ARM64_HAS_RNG,
2287 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2288 .matches = has_cpuid_feature,
2289 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2290 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2291 .sign = FTR_UNSIGNED,
2292 .min_field_value = 1,
2293 },
2294#endif
2295#ifdef CONFIG_ARM64_BTI
2296 {
2297 .desc = "Branch Target Identification",
2298 .capability = ARM64_BTI,
2299#ifdef CONFIG_ARM64_BTI_KERNEL
2300 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2301#else
2302 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2303#endif
2304 .matches = has_cpuid_feature,
2305 .cpu_enable = bti_enable,
2306 .sys_reg = SYS_ID_AA64PFR1_EL1,
2307 .field_pos = ID_AA64PFR1_BT_SHIFT,
2308 .min_field_value = ID_AA64PFR1_BT_BTI,
2309 .sign = FTR_UNSIGNED,
2310 },
2311#endif
2312#ifdef CONFIG_ARM64_MTE
2313 {
2314 .desc = "Memory Tagging Extension",
2315 .capability = ARM64_MTE,
2316 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2317 .matches = has_cpuid_feature,
2318 .sys_reg = SYS_ID_AA64PFR1_EL1,
2319 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2320 .min_field_value = ID_AA64PFR1_MTE,
2321 .sign = FTR_UNSIGNED,
2322 .cpu_enable = cpu_enable_mte,
2323 },
2324#endif
2325 {
2326 .desc = "RCpc load-acquire (LDAPR)",
2327 .capability = ARM64_HAS_LDAPR,
2328 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2329 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2330 .sign = FTR_UNSIGNED,
2331 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2332 .matches = has_cpuid_feature,
2333 .min_field_value = 1,
2334 },
2335 {},
2336};
2337
2338#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2339 .matches = has_cpuid_feature, \
2340 .sys_reg = reg, \
2341 .field_pos = field, \
2342 .sign = s, \
2343 .min_field_value = min_value,
2344
2345#define __HWCAP_CAP(name, cap_type, cap) \
2346 .desc = name, \
2347 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2348 .hwcap_type = cap_type, \
2349 .hwcap = cap, \
2350
2351#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2352 { \
2353 __HWCAP_CAP(#cap, cap_type, cap) \
2354 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2355 }
2356
2357#define HWCAP_MULTI_CAP(list, cap_type, cap) \
2358 { \
2359 __HWCAP_CAP(#cap, cap_type, cap) \
2360 .matches = cpucap_multi_entry_cap_matches, \
2361 .match_list = list, \
2362 }
2363
2364#define HWCAP_CAP_MATCH(match, cap_type, cap) \
2365 { \
2366 __HWCAP_CAP(#cap, cap_type, cap) \
2367 .matches = match, \
2368 }
2369
2370#ifdef CONFIG_ARM64_PTR_AUTH
2371static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2372 {
2373 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2374 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2375 },
2376 {
2377 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2378 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2379 },
2380 {},
2381};
2382
2383static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2384 {
2385 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2386 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2387 },
2388 {
2389 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2390 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2391 },
2392 {},
2393};
2394#endif
2395
2396static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2397 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2398 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2399 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2400 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2401 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2402 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2403 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2404 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2405 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2406 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2407 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2408 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2409 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2410 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2411 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2412 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2413 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2414 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2415 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2416 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2417 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2418 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2419 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2420 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2421 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2422 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2423 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2424 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2425 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2426 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2427 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2428 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2429 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2430#ifdef CONFIG_ARM64_SVE
2431 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2432 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2433 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2434 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2435 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2436 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2437 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2438 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2439 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2440 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2441 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2442#endif
2443 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2444#ifdef CONFIG_ARM64_BTI
2445 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2446#endif
2447#ifdef CONFIG_ARM64_PTR_AUTH
2448 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2449 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2450#endif
2451#ifdef CONFIG_ARM64_MTE
2452 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2453#endif
2454 {},
2455};
2456
2457#ifdef CONFIG_COMPAT
2458static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2459{
2460
2461
2462
2463
2464
2465 u32 mvfr1;
2466
2467 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2468 if (scope == SCOPE_SYSTEM)
2469 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2470 else
2471 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2472
2473 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2474 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2475 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2476}
2477#endif
2478
2479static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2480#ifdef CONFIG_COMPAT
2481 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2482 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2483
2484 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2485 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2486 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2487 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2488 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2489 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2490 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2491#endif
2492 {},
2493};
2494
2495static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2496{
2497 switch (cap->hwcap_type) {
2498 case CAP_HWCAP:
2499 cpu_set_feature(cap->hwcap);
2500 break;
2501#ifdef CONFIG_COMPAT
2502 case CAP_COMPAT_HWCAP:
2503 compat_elf_hwcap |= (u32)cap->hwcap;
2504 break;
2505 case CAP_COMPAT_HWCAP2:
2506 compat_elf_hwcap2 |= (u32)cap->hwcap;
2507 break;
2508#endif
2509 default:
2510 WARN_ON(1);
2511 break;
2512 }
2513}
2514
2515
2516static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2517{
2518 bool rc;
2519
2520 switch (cap->hwcap_type) {
2521 case CAP_HWCAP:
2522 rc = cpu_have_feature(cap->hwcap);
2523 break;
2524#ifdef CONFIG_COMPAT
2525 case CAP_COMPAT_HWCAP:
2526 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2527 break;
2528 case CAP_COMPAT_HWCAP2:
2529 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2530 break;
2531#endif
2532 default:
2533 WARN_ON(1);
2534 rc = false;
2535 }
2536
2537 return rc;
2538}
2539
2540static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2541{
2542
2543 cpu_set_named_feature(CPUID);
2544 for (; hwcaps->matches; hwcaps++)
2545 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2546 cap_set_elf_hwcap(hwcaps);
2547}
2548
2549static void update_cpu_capabilities(u16 scope_mask)
2550{
2551 int i;
2552 const struct arm64_cpu_capabilities *caps;
2553
2554 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2555 for (i = 0; i < ARM64_NCAPS; i++) {
2556 caps = cpu_hwcaps_ptrs[i];
2557 if (!caps || !(caps->type & scope_mask) ||
2558 cpus_have_cap(caps->capability) ||
2559 !caps->matches(caps, cpucap_default_scope(caps)))
2560 continue;
2561
2562 if (caps->desc)
2563 pr_info("detected: %s\n", caps->desc);
2564 cpus_set_cap(caps->capability);
2565
2566 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2567 set_bit(caps->capability, boot_capabilities);
2568 }
2569}
2570
2571
2572
2573
2574
2575static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2576{
2577 int i;
2578 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2579
2580 for_each_available_cap(i) {
2581 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2582
2583 if (WARN_ON(!cap))
2584 continue;
2585
2586 if (!(cap->type & non_boot_scope))
2587 continue;
2588
2589 if (cap->cpu_enable)
2590 cap->cpu_enable(cap);
2591 }
2592 return 0;
2593}
2594
2595
2596
2597
2598
2599static void __init enable_cpu_capabilities(u16 scope_mask)
2600{
2601 int i;
2602 const struct arm64_cpu_capabilities *caps;
2603 bool boot_scope;
2604
2605 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2606 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2607
2608 for (i = 0; i < ARM64_NCAPS; i++) {
2609 unsigned int num;
2610
2611 caps = cpu_hwcaps_ptrs[i];
2612 if (!caps || !(caps->type & scope_mask))
2613 continue;
2614 num = caps->capability;
2615 if (!cpus_have_cap(num))
2616 continue;
2617
2618
2619 static_branch_enable(&cpu_hwcap_keys[num]);
2620
2621 if (boot_scope && caps->cpu_enable)
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631 caps->cpu_enable(caps);
2632 }
2633
2634
2635
2636
2637
2638
2639
2640 if (!boot_scope)
2641 stop_machine(cpu_enable_non_boot_scope_capabilities,
2642 NULL, cpu_online_mask);
2643}
2644
2645
2646
2647
2648
2649
2650static void verify_local_cpu_caps(u16 scope_mask)
2651{
2652 int i;
2653 bool cpu_has_cap, system_has_cap;
2654 const struct arm64_cpu_capabilities *caps;
2655
2656 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2657
2658 for (i = 0; i < ARM64_NCAPS; i++) {
2659 caps = cpu_hwcaps_ptrs[i];
2660 if (!caps || !(caps->type & scope_mask))
2661 continue;
2662
2663 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2664 system_has_cap = cpus_have_cap(caps->capability);
2665
2666 if (system_has_cap) {
2667
2668
2669
2670
2671 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2672 break;
2673
2674
2675
2676
2677
2678
2679 if (caps->cpu_enable)
2680 caps->cpu_enable(caps);
2681 } else {
2682
2683
2684
2685
2686 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2687 break;
2688 }
2689 }
2690
2691 if (i < ARM64_NCAPS) {
2692 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2693 smp_processor_id(), caps->capability,
2694 caps->desc, system_has_cap, cpu_has_cap);
2695
2696 if (cpucap_panic_on_conflict(caps))
2697 cpu_panic_kernel();
2698 else
2699 cpu_die_early();
2700 }
2701}
2702
2703
2704
2705
2706
2707static void check_early_cpu_features(void)
2708{
2709 verify_cpu_asid_bits();
2710
2711 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2712}
2713
2714static void
2715__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2716{
2717
2718 for (; caps->matches; caps++)
2719 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2720 pr_crit("CPU%d: missing HWCAP: %s\n",
2721 smp_processor_id(), caps->desc);
2722 cpu_die_early();
2723 }
2724}
2725
2726static void verify_local_elf_hwcaps(void)
2727{
2728 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
2729
2730 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
2731 __verify_local_elf_hwcaps(compat_elf_hwcaps);
2732}
2733
2734static void verify_sve_features(void)
2735{
2736 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2737 u64 zcr = read_zcr_features();
2738
2739 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2740 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2741
2742 if (len < safe_len || sve_verify_vq_map()) {
2743 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2744 smp_processor_id());
2745 cpu_die_early();
2746 }
2747
2748
2749}
2750
2751static void verify_hyp_capabilities(void)
2752{
2753 u64 safe_mmfr1, mmfr0, mmfr1;
2754 int parange, ipa_max;
2755 unsigned int safe_vmid_bits, vmid_bits;
2756
2757 if (!IS_ENABLED(CONFIG_KVM))
2758 return;
2759
2760 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2761 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2762 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2763
2764
2765 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2766 vmid_bits = get_vmid_bits(mmfr1);
2767 if (vmid_bits < safe_vmid_bits) {
2768 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2769 cpu_die_early();
2770 }
2771
2772
2773 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2774 ID_AA64MMFR0_PARANGE_SHIFT);
2775 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2776 if (ipa_max < get_kvm_ipa_limit()) {
2777 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2778 cpu_die_early();
2779 }
2780}
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790static void verify_local_cpu_capabilities(void)
2791{
2792
2793
2794
2795
2796
2797 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2798 verify_local_elf_hwcaps();
2799
2800 if (system_supports_sve())
2801 verify_sve_features();
2802
2803 if (is_hyp_mode_available())
2804 verify_hyp_capabilities();
2805}
2806
2807void check_local_cpu_capabilities(void)
2808{
2809
2810
2811
2812
2813 check_early_cpu_features();
2814
2815
2816
2817
2818
2819
2820
2821 if (!system_capabilities_finalized())
2822 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2823 else
2824 verify_local_cpu_capabilities();
2825}
2826
2827static void __init setup_boot_cpu_capabilities(void)
2828{
2829
2830 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2831
2832 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2833}
2834
2835bool this_cpu_has_cap(unsigned int n)
2836{
2837 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2838 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2839
2840 if (cap)
2841 return cap->matches(cap, SCOPE_LOCAL_CPU);
2842 }
2843
2844 return false;
2845}
2846
2847
2848
2849
2850
2851
2852
2853static bool __maybe_unused __system_matches_cap(unsigned int n)
2854{
2855 if (n < ARM64_NCAPS) {
2856 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2857
2858 if (cap)
2859 return cap->matches(cap, SCOPE_SYSTEM);
2860 }
2861 return false;
2862}
2863
2864void cpu_set_feature(unsigned int num)
2865{
2866 WARN_ON(num >= MAX_CPU_FEATURES);
2867 elf_hwcap |= BIT(num);
2868}
2869EXPORT_SYMBOL_GPL(cpu_set_feature);
2870
2871bool cpu_have_feature(unsigned int num)
2872{
2873 WARN_ON(num >= MAX_CPU_FEATURES);
2874 return elf_hwcap & BIT(num);
2875}
2876EXPORT_SYMBOL_GPL(cpu_have_feature);
2877
2878unsigned long cpu_get_elf_hwcap(void)
2879{
2880
2881
2882
2883
2884
2885 return lower_32_bits(elf_hwcap);
2886}
2887
2888unsigned long cpu_get_elf_hwcap2(void)
2889{
2890 return upper_32_bits(elf_hwcap);
2891}
2892
2893static void __init setup_system_capabilities(void)
2894{
2895
2896
2897
2898
2899
2900
2901 update_cpu_capabilities(SCOPE_SYSTEM);
2902 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2903}
2904
2905void __init setup_cpu_features(void)
2906{
2907 u32 cwg;
2908
2909 setup_system_capabilities();
2910 setup_elf_hwcaps(arm64_elf_hwcaps);
2911
2912 if (system_supports_32bit_el0())
2913 setup_elf_hwcaps(compat_elf_hwcaps);
2914
2915 if (system_uses_ttbr0_pan())
2916 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2917
2918 sve_setup();
2919 minsigstksz_setup();
2920
2921
2922 finalize_system_capabilities();
2923
2924
2925
2926
2927 cwg = cache_type_cwg();
2928 if (!cwg)
2929 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2930 ARCH_DMA_MINALIGN);
2931}
2932
2933static int enable_mismatched_32bit_el0(unsigned int cpu)
2934{
2935
2936
2937
2938
2939
2940 static int lucky_winner = -1;
2941
2942 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
2943 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
2944
2945 if (cpu_32bit) {
2946 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
2947 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
2948 }
2949
2950 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
2951 return 0;
2952
2953 if (lucky_winner >= 0)
2954 return 0;
2955
2956
2957
2958
2959
2960
2961 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
2962 cpu_active_mask);
2963 get_cpu_device(lucky_winner)->offline_disabled = true;
2964 setup_elf_hwcaps(compat_elf_hwcaps);
2965 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
2966 cpu, lucky_winner);
2967 return 0;
2968}
2969
2970static int __init init_32bit_el0_mask(void)
2971{
2972 if (!allow_mismatched_32bit_el0)
2973 return 0;
2974
2975 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
2976 return -ENOMEM;
2977
2978 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
2979 "arm64/mismatched_32bit_el0:online",
2980 enable_mismatched_32bit_el0, NULL);
2981}
2982subsys_initcall_sync(init_32bit_el0_mask);
2983
2984static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2985{
2986 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2987}
2988
2989
2990
2991
2992
2993
2994
2995static inline bool __attribute_const__ is_emulated(u32 id)
2996{
2997 return (sys_reg_Op0(id) == 0x3 &&
2998 sys_reg_CRn(id) == 0x0 &&
2999 sys_reg_Op1(id) == 0x0 &&
3000 (sys_reg_CRm(id) == 0 ||
3001 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
3002}
3003
3004
3005
3006
3007
3008static inline int emulate_id_reg(u32 id, u64 *valp)
3009{
3010 switch (id) {
3011 case SYS_MIDR_EL1:
3012 *valp = read_cpuid_id();
3013 break;
3014 case SYS_MPIDR_EL1:
3015 *valp = SYS_MPIDR_SAFE_VAL;
3016 break;
3017 case SYS_REVIDR_EL1:
3018
3019 *valp = 0;
3020 break;
3021 default:
3022 return -EINVAL;
3023 }
3024
3025 return 0;
3026}
3027
3028static int emulate_sys_reg(u32 id, u64 *valp)
3029{
3030 struct arm64_ftr_reg *regp;
3031
3032 if (!is_emulated(id))
3033 return -EINVAL;
3034
3035 if (sys_reg_CRm(id) == 0)
3036 return emulate_id_reg(id, valp);
3037
3038 regp = get_arm64_ftr_reg_nowarn(id);
3039 if (regp)
3040 *valp = arm64_ftr_reg_user_value(regp);
3041 else
3042
3043
3044
3045
3046 *valp = 0;
3047 return 0;
3048}
3049
3050int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3051{
3052 int rc;
3053 u64 val;
3054
3055 rc = emulate_sys_reg(sys_reg, &val);
3056 if (!rc) {
3057 pt_regs_write_reg(regs, rt, val);
3058 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3059 }
3060 return rc;
3061}
3062
3063static int emulate_mrs(struct pt_regs *regs, u32 insn)
3064{
3065 u32 sys_reg, rt;
3066
3067
3068
3069
3070
3071 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3072 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3073 return do_emulate_mrs(regs, sys_reg, rt);
3074}
3075
3076static struct undef_hook mrs_hook = {
3077 .instr_mask = 0xffff0000,
3078 .instr_val = 0xd5380000,
3079 .pstate_mask = PSR_AA32_MODE_MASK,
3080 .pstate_val = PSR_MODE_EL0t,
3081 .fn = emulate_mrs,
3082};
3083
3084static int __init enable_mrs_emulation(void)
3085{
3086 register_undef_hook(&mrs_hook);
3087 return 0;
3088}
3089
3090core_initcall(enable_mrs_emulation);
3091
3092enum mitigation_state arm64_get_meltdown_state(void)
3093{
3094 if (__meltdown_safe)
3095 return SPECTRE_UNAFFECTED;
3096
3097 if (arm64_kernel_unmapped_at_el0())
3098 return SPECTRE_MITIGATED;
3099
3100 return SPECTRE_VULNERABLE;
3101}
3102
3103ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3104 char *buf)
3105{
3106 switch (arm64_get_meltdown_state()) {
3107 case SPECTRE_UNAFFECTED:
3108 return sprintf(buf, "Not affected\n");
3109
3110 case SPECTRE_MITIGATED:
3111 return sprintf(buf, "Mitigation: PTI\n");
3112
3113 default:
3114 return sprintf(buf, "Vulnerable\n");
3115 }
3116}
3117