LXR linux/arch/arm64/kvm/vgic/vgic.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2015, 2016 ARM Ltd.
   4 */
   5#ifndef __KVM_ARM_VGIC_NEW_H__
   6#define __KVM_ARM_VGIC_NEW_H__
   7
   8#include <linux/irqchip/arm-gic-common.h>
   9
  10#define PRODUCT_ID_KVM          0x4b    /* ASCII code K */
  11#define IMPLEMENTER_ARM         0x43b
  12
  13#define VGIC_ADDR_UNDEF         (-1)
  14#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
  15
  16#define INTERRUPT_ID_BITS_SPIS  10
  17#define INTERRUPT_ID_BITS_ITS   16
  18#define VGIC_PRI_BITS           5
  19
  20#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
  21
  22#define VGIC_AFFINITY_0_SHIFT 0
  23#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
  24#define VGIC_AFFINITY_1_SHIFT 8
  25#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
  26#define VGIC_AFFINITY_2_SHIFT 16
  27#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
  28#define VGIC_AFFINITY_3_SHIFT 24
  29#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
  30
  31#define VGIC_AFFINITY_LEVEL(reg, level) \
  32        ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
  33        >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
  34
  35/*
  36 * The Userspace encodes the affinity differently from the MPIDR,
  37 * Below macro converts vgic userspace format to MPIDR reg format.
  38 */
  39#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
  40                            VGIC_AFFINITY_LEVEL(val, 1) | \
  41                            VGIC_AFFINITY_LEVEL(val, 2) | \
  42                            VGIC_AFFINITY_LEVEL(val, 3))
  43
  44/*
  45 * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst,
  46 * below macros are defined for CPUREG encoding.
  47 */
  48#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
  49#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT  14
  50#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
  51#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT  11
  52#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
  53#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT  7
  54#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
  55#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT  3
  56#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
  57#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT  0
  58
  59#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
  60                                      KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
  61                                      KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
  62                                      KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
  63                                      KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
  64
  65/*
  66 * As per Documentation/virt/kvm/devices/arm-vgic-its.rst,
  67 * below macros are defined for ITS table entry encoding.
  68 */
  69#define KVM_ITS_CTE_VALID_SHIFT         63
  70#define KVM_ITS_CTE_VALID_MASK          BIT_ULL(63)
  71#define KVM_ITS_CTE_RDBASE_SHIFT        16
  72#define KVM_ITS_CTE_ICID_MASK           GENMASK_ULL(15, 0)
  73#define KVM_ITS_ITE_NEXT_SHIFT          48
  74#define KVM_ITS_ITE_PINTID_SHIFT        16
  75#define KVM_ITS_ITE_PINTID_MASK         GENMASK_ULL(47, 16)
  76#define KVM_ITS_ITE_ICID_MASK           GENMASK_ULL(15, 0)
  77#define KVM_ITS_DTE_VALID_SHIFT         63
  78#define KVM_ITS_DTE_VALID_MASK          BIT_ULL(63)
  79#define KVM_ITS_DTE_NEXT_SHIFT          49
  80#define KVM_ITS_DTE_NEXT_MASK           GENMASK_ULL(62, 49)
  81#define KVM_ITS_DTE_ITTADDR_SHIFT       5
  82#define KVM_ITS_DTE_ITTADDR_MASK        GENMASK_ULL(48, 5)
  83#define KVM_ITS_DTE_SIZE_MASK           GENMASK_ULL(4, 0)
  84#define KVM_ITS_L1E_VALID_MASK          BIT_ULL(63)
  85/* we only support 64 kB translation table page size */
  86#define KVM_ITS_L1E_ADDR_MASK           GENMASK_ULL(51, 16)
  87
  88#define KVM_VGIC_V3_RDIST_INDEX_MASK    GENMASK_ULL(11, 0)
  89#define KVM_VGIC_V3_RDIST_FLAGS_MASK    GENMASK_ULL(15, 12)
  90#define KVM_VGIC_V3_RDIST_FLAGS_SHIFT   12
  91#define KVM_VGIC_V3_RDIST_BASE_MASK     GENMASK_ULL(51, 16)
  92#define KVM_VGIC_V3_RDIST_COUNT_MASK    GENMASK_ULL(63, 52)
  93#define KVM_VGIC_V3_RDIST_COUNT_SHIFT   52
  94
  95#ifdef CONFIG_DEBUG_SPINLOCK
  96#define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p)
  97#else
  98#define DEBUG_SPINLOCK_BUG_ON(p)
  99#endif
 100
 101/* Requires the irq_lock to be held by the caller. */
 102static inline bool irq_is_pending(struct vgic_irq *irq)
 103{
 104        if (irq->config == VGIC_CONFIG_EDGE)
 105                return irq->pending_latch;
 106        else
 107                return irq->pending_latch || irq->line_level;
 108}
 109
 110static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
 111{
 112        return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
 113}
 114
 115static inline int vgic_irq_get_lr_count(struct vgic_irq *irq)
 116{
 117        /* Account for the active state as an interrupt */
 118        if (vgic_irq_is_sgi(irq->intid) && irq->source)
 119                return hweight8(irq->source) + irq->active;
 120
 121        return irq_is_pending(irq) || irq->active;
 122}
 123
 124static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq)
 125{
 126        return vgic_irq_get_lr_count(irq) > 1;
 127}
 128
 129/*
 130 * This struct provides an intermediate representation of the fields contained
 131 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
 132 * state to userspace can generate either GICv2 or GICv3 CPU interface
 133 * registers regardless of the hardware backed GIC used.
 134 */
 135struct vgic_vmcr {
 136        u32     grpen0;
 137        u32     grpen1;
 138
 139        u32     ackctl;
 140        u32     fiqen;
 141        u32     cbpr;
 142        u32     eoim;
 143
 144        u32     abpr;
 145        u32     bpr;
 146        u32     pmr;  /* Priority mask field in the GICC_PMR and
 147                       * ICC_PMR_EL1 priority field format */
 148};
 149
 150struct vgic_reg_attr {
 151        struct kvm_vcpu *vcpu;
 152        gpa_t addr;
 153};
 154
 155int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
 156                       struct vgic_reg_attr *reg_attr);
 157int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
 158                       struct vgic_reg_attr *reg_attr);
 159const struct vgic_register_region *
 160vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
 161                     gpa_t addr, int len);
 162struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
 163                              u32 intid);
 164void __vgic_put_lpi_locked(struct kvm *kvm, struct vgic_irq *irq);
 165void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
 166bool vgic_get_phys_line_level(struct vgic_irq *irq);
 167void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
 168void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
 169bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
 170                           unsigned long flags);
 171void vgic_kick_vcpus(struct kvm *kvm);
 172void vgic_irq_handle_resampling(struct vgic_irq *irq,
 173                                bool lr_deactivated, bool lr_pending);
 174
 175int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
 176                      phys_addr_t addr, phys_addr_t alignment);
 177
 178void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
 179void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 180void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
 181void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
 182void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
 183int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 184int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 185                         int offset, u32 *val);
 186int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 187                          int offset, u32 *val);
 188void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 189void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 190void vgic_v2_enable(struct kvm_vcpu *vcpu);
 191int vgic_v2_probe(const struct gic_kvm_info *info);
 192int vgic_v2_map_resources(struct kvm *kvm);
 193int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 194                             enum vgic_type);
 195
 196void vgic_v2_init_lrs(void);
 197void vgic_v2_load(struct kvm_vcpu *vcpu);
 198void vgic_v2_put(struct kvm_vcpu *vcpu);
 199void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu);
 200
 201void vgic_v2_save_state(struct kvm_vcpu *vcpu);
 202void vgic_v2_restore_state(struct kvm_vcpu *vcpu);
 203
 204static inline void vgic_get_irq_kref(struct vgic_irq *irq)
 205{
 206        if (irq->intid < VGIC_MIN_LPI)
 207                return;
 208
 209        kref_get(&irq->refcount);
 210}
 211
 212void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
 213void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 214void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
 215void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
 216void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
 217void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 218void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 219void vgic_v3_enable(struct kvm_vcpu *vcpu);
 220int vgic_v3_probe(const struct gic_kvm_info *info);
 221int vgic_v3_map_resources(struct kvm *kvm);
 222int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
 223int vgic_v3_save_pending_tables(struct kvm *kvm);
 224int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count);
 225int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
 226bool vgic_v3_check_base(struct kvm *kvm);
 227
 228void vgic_v3_load(struct kvm_vcpu *vcpu);
 229void vgic_v3_put(struct kvm_vcpu *vcpu);
 230void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu);
 231
 232bool vgic_has_its(struct kvm *kvm);
 233int kvm_vgic_register_its_device(void);
 234void vgic_enable_lpis(struct kvm_vcpu *vcpu);
 235void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu);
 236int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
 237int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 238int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 239                         int offset, u32 *val);
 240int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 241                         int offset, u32 *val);
 242int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 243                         u64 id, u64 *val);
 244int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
 245                                u64 *reg);
 246int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 247                                    u32 intid, u64 *val);
 248int kvm_register_vgic_device(unsigned long type);
 249void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 250void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 251int vgic_lazy_init(struct kvm *kvm);
 252int vgic_init(struct kvm *kvm);
 253
 254void vgic_debug_init(struct kvm *kvm);
 255void vgic_debug_destroy(struct kvm *kvm);
 256
 257bool lock_all_vcpus(struct kvm *kvm);
 258void unlock_all_vcpus(struct kvm *kvm);
 259
 260static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
 261{
 262        struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
 263
 264        /*
 265         * num_pri_bits are initialized with HW supported values.
 266         * We can rely safely on num_pri_bits even if VM has not
 267         * restored ICC_CTLR_EL1 before restoring APnR registers.
 268         */
 269        switch (cpu_if->num_pri_bits) {
 270        case 7: return 3;
 271        case 6: return 1;
 272        default: return 0;
 273        }
 274}
 275
 276static inline bool
 277vgic_v3_redist_region_full(struct vgic_redist_region *region)
 278{
 279        if (!region->count)
 280                return false;
 281
 282        return (region->free_index >= region->count);
 283}
 284
 285struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs);
 286
 287static inline size_t
 288vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg)
 289{
 290        if (!rdreg->count)
 291                return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE;
 292        else
 293                return rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
 294}
 295
 296struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
 297                                                           u32 index);
 298void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg);
 299
 300bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size);
 301
 302static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size)
 303{
 304        struct vgic_dist *d = &kvm->arch.vgic;
 305
 306        return (base + size > d->vgic_dist_base) &&
 307                (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);
 308}
 309
 310int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr);
 311int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
 312                         u32 devid, u32 eventid, struct vgic_irq **irq);
 313struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
 314int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi);
 315void vgic_lpi_translation_cache_init(struct kvm *kvm);
 316void vgic_lpi_translation_cache_destroy(struct kvm *kvm);
 317void vgic_its_invalidate_cache(struct kvm *kvm);
 318
 319bool vgic_supports_direct_msis(struct kvm *kvm);
 320int vgic_v4_init(struct kvm *kvm);
 321void vgic_v4_teardown(struct kvm *kvm);
 322void vgic_v4_configure_vsgis(struct kvm *kvm);
 323void vgic_v4_get_vlpi_state(struct vgic_irq *irq, bool *val);
 324
 325#endif
 326