1
2
3#ifndef __ASM_CSKY_CKMMUV2_H
4#define __ASM_CSKY_CKMMUV2_H
5
6#include <abi/reg_ops.h>
7#include <asm/barrier.h>
8
9static inline int read_mmu_index(void)
10{
11 return mfcr("cr<0, 15>");
12}
13
14static inline void write_mmu_index(int value)
15{
16 mtcr("cr<0, 15>", value);
17}
18
19static inline int read_mmu_entrylo0(void)
20{
21 return mfcr("cr<2, 15>");
22}
23
24static inline int read_mmu_entrylo1(void)
25{
26 return mfcr("cr<3, 15>");
27}
28
29static inline void write_mmu_pagemask(int value)
30{
31 mtcr("cr<6, 15>", value);
32}
33
34static inline int read_mmu_entryhi(void)
35{
36 return mfcr("cr<4, 15>");
37}
38
39static inline void write_mmu_entryhi(int value)
40{
41 mtcr("cr<4, 15>", value);
42}
43
44static inline unsigned long read_mmu_msa0(void)
45{
46 return mfcr("cr<30, 15>");
47}
48
49static inline void write_mmu_msa0(unsigned long value)
50{
51 mtcr("cr<30, 15>", value);
52}
53
54static inline unsigned long read_mmu_msa1(void)
55{
56 return mfcr("cr<31, 15>");
57}
58
59static inline void write_mmu_msa1(unsigned long value)
60{
61 mtcr("cr<31, 15>", value);
62}
63
64
65
66
67static inline void tlb_probe(void)
68{
69 mtcr("cr<8, 15>", 0x80000000);
70}
71
72static inline void tlb_read(void)
73{
74 mtcr("cr<8, 15>", 0x40000000);
75}
76
77static inline void tlb_invalid_all(void)
78{
79#ifdef CONFIG_CPU_HAS_TLBI
80 sync_is();
81 asm volatile(
82 "tlbi.alls \n"
83 "sync.i \n"
84 :
85 :
86 : "memory");
87#else
88 mtcr("cr<8, 15>", 0x04000000);
89#endif
90}
91
92static inline void local_tlb_invalid_all(void)
93{
94#ifdef CONFIG_CPU_HAS_TLBI
95 sync_is();
96 asm volatile(
97 "tlbi.all \n"
98 "sync.i \n"
99 :
100 :
101 : "memory");
102#else
103 tlb_invalid_all();
104#endif
105}
106
107static inline void tlb_invalid_indexed(void)
108{
109 mtcr("cr<8, 15>", 0x02000000);
110}
111
112#define NOP32 ".long 0x4820c400\n"
113
114static inline void setup_pgd(pgd_t *pgd, int asid)
115{
116#ifdef CONFIG_CPU_HAS_TLBI
117 sync_is();
118#else
119 mb();
120#endif
121 asm volatile(
122#ifdef CONFIG_CPU_HAS_TLBI
123 "mtcr %1, cr<28, 15> \n"
124#endif
125 "mtcr %1, cr<29, 15> \n"
126 "mtcr %0, cr< 4, 15> \n"
127 ".rept 64 \n"
128 NOP32
129 ".endr \n"
130 :
131 :"r"(asid), "r"(__pa(pgd) | BIT(0))
132 :"memory");
133}
134
135static inline pgd_t *get_pgd(void)
136{
137 return __va(mfcr("cr<29, 15>") & ~BIT(0));
138}
139#endif
140