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2#ifndef _ASM_IA64_PGTABLE_H
3#define _ASM_IA64_PGTABLE_H
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17#include <asm/mman.h>
18#include <asm/page.h>
19#include <asm/processor.h>
20#include <asm/types.h>
21
22#define IA64_MAX_PHYS_BITS 50
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28
29#define _PAGE_P_BIT 0
30#define _PAGE_A_BIT 5
31#define _PAGE_D_BIT 6
32
33#define _PAGE_P (1 << _PAGE_P_BIT)
34#define _PAGE_MA_WB (0x0 << 2)
35#define _PAGE_MA_UC (0x4 << 2)
36#define _PAGE_MA_UCE (0x5 << 2)
37#define _PAGE_MA_WC (0x6 << 2)
38#define _PAGE_MA_NAT (0x7 << 2)
39#define _PAGE_MA_MASK (0x7 << 2)
40#define _PAGE_PL_0 (0 << 7)
41#define _PAGE_PL_1 (1 << 7)
42#define _PAGE_PL_2 (2 << 7)
43#define _PAGE_PL_3 (3 << 7)
44#define _PAGE_PL_MASK (3 << 7)
45#define _PAGE_AR_R (0 << 9)
46#define _PAGE_AR_RX (1 << 9)
47#define _PAGE_AR_RW (2 << 9)
48#define _PAGE_AR_RWX (3 << 9)
49#define _PAGE_AR_R_RW (4 << 9)
50#define _PAGE_AR_RX_RWX (5 << 9)
51#define _PAGE_AR_RWX_RW (6 << 9)
52#define _PAGE_AR_X_RX (7 << 9)
53#define _PAGE_AR_MASK (7 << 9)
54#define _PAGE_AR_SHIFT 9
55#define _PAGE_A (1 << _PAGE_A_BIT)
56#define _PAGE_D (1 << _PAGE_D_BIT)
57#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
58#define _PAGE_ED (__IA64_UL(1) << 52)
59#define _PAGE_PROTNONE (__IA64_UL(1) << 63)
60
61#define _PFN_MASK _PAGE_PPN_MASK
62
63#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
64
65#define _PAGE_SIZE_4K 12
66#define _PAGE_SIZE_8K 13
67#define _PAGE_SIZE_16K 14
68#define _PAGE_SIZE_64K 16
69#define _PAGE_SIZE_256K 18
70#define _PAGE_SIZE_1M 20
71#define _PAGE_SIZE_4M 22
72#define _PAGE_SIZE_16M 24
73#define _PAGE_SIZE_64M 26
74#define _PAGE_SIZE_256M 28
75#define _PAGE_SIZE_1G 30
76#define _PAGE_SIZE_4G 32
77
78#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
79#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
80#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
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84
85#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3)
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90#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
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98#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
99#define PMD_SIZE (1UL << PMD_SHIFT)
100#define PMD_MASK (~(PMD_SIZE-1))
101#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT))
102
103#if CONFIG_PGTABLE_LEVELS == 4
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110#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
111#define PUD_SIZE (1UL << PUD_SHIFT)
112#define PUD_MASK (~(PUD_SIZE-1))
113#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT))
114#endif
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120
121#if CONFIG_PGTABLE_LEVELS == 4
122#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
123#else
124#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
125#endif
126#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
127#define PGDIR_MASK (~(PGDIR_SIZE-1))
128#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT
129#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT)
130#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8)
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136
137#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
138#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
139#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
140#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
141#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
142#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
143#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
144#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
145#define PAGE_KERNEL_UC __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX | \
146 _PAGE_MA_UC)
147
148# ifndef __ASSEMBLY__
149
150#include <linux/sched/mm.h>
151#include <linux/bitops.h>
152#include <asm/cacheflush.h>
153#include <asm/mmu_context.h>
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164#define __P000 PAGE_NONE
165#define __P001 PAGE_READONLY
166#define __P010 PAGE_READONLY
167#define __P011 PAGE_READONLY
168#define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
169#define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
170#define __P110 PAGE_COPY_EXEC
171#define __P111 PAGE_COPY_EXEC
172
173#define __S000 PAGE_NONE
174#define __S001 PAGE_READONLY
175#define __S010 PAGE_SHARED
176#define __S011 PAGE_SHARED
177#define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
178#define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
179#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
180#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
181
182#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
183#if CONFIG_PGTABLE_LEVELS == 4
184#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
185#endif
186#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
187#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
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195
196static inline long
197ia64_phys_addr_valid (unsigned long addr)
198{
199 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
200}
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215#define kern_addr_valid(addr) (1)
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224#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
225#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
226
227# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10)))
228# define vmemmap ((struct page *)VMALLOC_END)
229#else
230# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
231#endif
232
233
234#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
235#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
236
237#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
238#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE)
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243
244#define pfn_pte(pfn, pgprot) \
245({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
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247
248#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
249
250#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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252
253#define mk_pte_phys(physpage, pgprot) \
254({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
255
256#define pte_modify(_pte, newprot) \
257 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
258
259#define pte_none(pte) (!pte_val(pte))
260#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
261#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
262
263#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
264
265#define pmd_none(pmd) (!pmd_val(pmd))
266#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
267#define pmd_present(pmd) (pmd_val(pmd) != 0UL)
268#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
269#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
270#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
271
272#define pud_none(pud) (!pud_val(pud))
273#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
274#define pud_present(pud) (pud_val(pud) != 0UL)
275#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
276#define pud_pgtable(pud) ((pmd_t *) __va(pud_val(pud) & _PFN_MASK))
277#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET))
278
279#if CONFIG_PGTABLE_LEVELS == 4
280#define p4d_none(p4d) (!p4d_val(p4d))
281#define p4d_bad(p4d) (!ia64_phys_addr_valid(p4d_val(p4d)))
282#define p4d_present(p4d) (p4d_val(p4d) != 0UL)
283#define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL)
284#define p4d_pgtable(p4d) ((pud_t *) __va(p4d_val(p4d) & _PFN_MASK))
285#define p4d_page(p4d) virt_to_page((p4d_val(p4d) + PAGE_OFFSET))
286#endif
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291#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
292#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
293#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
294#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
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300#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
301#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
302#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
303#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
304#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
305#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
306#define pte_mkhuge(pte) (__pte(pte_val(pte)))
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317#define pte_present_exec_user(pte)\
318 ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
319 (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
320
321extern void __ia64_sync_icache_dcache(pte_t pteval);
322static inline void set_pte(pte_t *ptep, pte_t pteval)
323{
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327
328 if (pte_present_exec_user(pteval) &&
329 (!pte_present(*ptep) ||
330 pte_pfn(*ptep) != pte_pfn(pteval)))
331
332 __ia64_sync_icache_dcache(pteval);
333 *ptep = pteval;
334}
335
336#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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344#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
345#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
346#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
347
348struct file;
349extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
350 unsigned long size, pgprot_t vma_prot);
351#define __HAVE_PHYS_MEM_ACCESS_PROT
352
353static inline unsigned long
354pgd_index (unsigned long address)
355{
356 unsigned long region = address >> 61;
357 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
358
359 return (region << (PAGE_SHIFT - 6)) | l1index;
360}
361#define pgd_index pgd_index
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369#define pgd_offset_k(addr) \
370 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
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375#define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
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378
379static inline int
380ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
381{
382#ifdef CONFIG_SMP
383 if (!pte_young(*ptep))
384 return 0;
385 return test_and_clear_bit(_PAGE_A_BIT, ptep);
386#else
387 pte_t pte = *ptep;
388 if (!pte_young(pte))
389 return 0;
390 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
391 return 1;
392#endif
393}
394
395static inline pte_t
396ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
397{
398#ifdef CONFIG_SMP
399 return __pte(xchg((long *) ptep, 0));
400#else
401 pte_t pte = *ptep;
402 pte_clear(mm, addr, ptep);
403 return pte;
404#endif
405}
406
407static inline void
408ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
409{
410#ifdef CONFIG_SMP
411 unsigned long new, old;
412
413 do {
414 old = pte_val(*ptep);
415 new = pte_val(pte_wrprotect(__pte (old)));
416 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
417#else
418 pte_t old_pte = *ptep;
419 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
420#endif
421}
422
423static inline int
424pte_same (pte_t a, pte_t b)
425{
426 return pte_val(a) == pte_val(b);
427}
428
429#define update_mmu_cache(vma, address, ptep) do { } while (0)
430
431extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
432extern void paging_init (void);
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446#define __swp_type(entry) (((entry).val >> 1) & 0x7f)
447#define __swp_offset(entry) (((entry).val << 1) >> 9)
448#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((long) (offset) << 8) })
449#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
450#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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456extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
457extern struct page *zero_page_memmap_ptr;
458#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
459
460
461#define HAVE_ARCH_UNMAPPED_AREA
462
463#ifdef CONFIG_HUGETLB_PAGE
464#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
465#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
466#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
467#endif
468
469
470#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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493#ifdef CONFIG_SMP
494# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
495({ \
496 int __changed = !pte_same(*(__ptep), __entry); \
497 if (__changed && __safely_writable) { \
498 set_pte(__ptep, __entry); \
499 flush_tlb_page(__vma, __addr); \
500 } \
501 __changed; \
502})
503#else
504# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
505({ \
506 int __changed = !pte_same(*(__ptep), __entry); \
507 if (__changed) { \
508 set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \
509 flush_tlb_page(__vma, __addr); \
510 } \
511 __changed; \
512})
513#endif
514# endif
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519
520
521#if defined(CONFIG_IA64_GRANULE_64MB)
522# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
523#elif defined(CONFIG_IA64_GRANULE_16MB)
524# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
525#endif
526#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
527
528
529
530#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
531#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
532
533
534#define FIXADDR_USER_START GATE_ADDR
535#ifdef HAVE_BUGGY_SEGREL
536# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
537#else
538# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
539#endif
540
541#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
542#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
543#define __HAVE_ARCH_PTEP_SET_WRPROTECT
544#define __HAVE_ARCH_PTE_SAME
545#define __HAVE_ARCH_PGD_OFFSET_GATE
546
547
548#if CONFIG_PGTABLE_LEVELS == 3
549#include <asm-generic/pgtable-nopud.h>
550#endif
551#include <asm-generic/pgtable-nop4d.h>
552
553#endif
554