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10#ifndef __M68K_DVMA_H
11#define __M68K_DVMA_H
12
13
14#define DVMA_PAGE_SHIFT 13
15#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
16#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
17#define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
18
19extern void dvma_init(void);
20extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
21 int len);
22
23#define dvma_malloc(x) dvma_malloc_align(x, 0)
24#define dvma_map(x, y) dvma_map_align(x, y, 0)
25#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
26#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
27extern unsigned long dvma_map_align(unsigned long kaddr, int len,
28 int align);
29extern void *dvma_malloc_align(unsigned long len, unsigned long align);
30
31extern void dvma_unmap(void *baddr);
32extern void dvma_free(void *vaddr);
33
34
35#ifdef CONFIG_SUN3
36
37
38
39#define DVMA_PMEG_START 10
40#define DVMA_PMEG_END 16
41#define DVMA_START 0xf00000
42#define DVMA_END 0xfe0000
43#define DVMA_SIZE (DVMA_END-DVMA_START)
44#define IOMMU_TOTAL_ENTRIES 128
45#define IOMMU_ENTRIES 120
46
47
48
49#define DVMA_REGION_SIZE 0x10000
50#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
51 ~(DVMA_REGION_SIZE-1))
52
53
54#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
55#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
56#define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
57#define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
58#define dvma_vtob(x) dvma_vtop(x)
59#define dvma_btov(x) dvma_ptov(x)
60
61static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
62 int len)
63{
64 return 0;
65}
66
67#else
68
69
70
71#define DVMA_START 0x0
72#define DVMA_END 0xf00000
73#define DVMA_SIZE (DVMA_END-DVMA_START)
74#define IOMMU_TOTAL_ENTRIES 2048
75
76#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
77
78#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
79#define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
80
81extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
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87
88
89struct sparc_dma_registers {
90 __volatile__ unsigned long cond_reg;
91 __volatile__ unsigned long st_addr;
92 __volatile__ unsigned long cnt;
93 __volatile__ unsigned long dma_test;
94};
95
96
97enum dvma_rev {
98 dvmarev0,
99 dvmaesc1,
100 dvmarev1,
101 dvmarev2,
102 dvmarev3,
103 dvmarevplus,
104 dvmahme
105};
106
107#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
108
109
110struct Linux_SBus_DMA {
111 struct Linux_SBus_DMA *next;
112 struct linux_sbus_device *SBus_dev;
113 struct sparc_dma_registers *regs;
114
115
116 int node;
117 int running;
118 int allocated;
119
120
121 unsigned long addr;
122 int nbytes;
123 int realbytes;
124
125
126 enum dvma_rev revision;
127};
128
129extern struct Linux_SBus_DMA *dma_chain;
130
131
132#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
133#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
134
135
136
137#define DMA_DEVICE_ID 0xf0000000
138#define DMA_VERS0 0x00000000
139#define DMA_ESCV1 0x40000000
140#define DMA_VERS1 0x80000000
141#define DMA_VERS2 0xa0000000
142#define DMA_VERHME 0xb0000000
143#define DMA_VERSPLUS 0x90000000
144
145#define DMA_HNDL_INTR 0x00000001
146#define DMA_HNDL_ERROR 0x00000002
147#define DMA_FIFO_ISDRAIN 0x0000000c
148#define DMA_INT_ENAB 0x00000010
149#define DMA_FIFO_INV 0x00000020
150#define DMA_ACC_SZ_ERR 0x00000040
151#define DMA_FIFO_STDRAIN 0x00000040
152#define DMA_RST_SCSI 0x00000080
153#define DMA_RST_ENET DMA_RST_SCSI
154#define DMA_ST_WRITE 0x00000100
155#define DMA_ENABLE 0x00000200
156#define DMA_PEND_READ 0x00000400
157#define DMA_ESC_BURST 0x00000800
158#define DMA_READ_AHEAD 0x00001800
159#define DMA_DSBL_RD_DRN 0x00001000
160#define DMA_BCNT_ENAB 0x00002000
161#define DMA_TERM_CNTR 0x00004000
162#define DMA_CSR_DISAB 0x00010000
163#define DMA_SCSI_DISAB 0x00020000
164#define DMA_DSBL_WR_INV 0x00020000
165#define DMA_ADD_ENABLE 0x00040000
166#define DMA_E_BURST8 0x00040000
167#define DMA_BRST_SZ 0x000c0000
168#define DMA_BRST64 0x00080000
169#define DMA_BRST32 0x00040000
170#define DMA_BRST16 0x00000000
171#define DMA_BRST0 0x00080000
172#define DMA_ADDR_DISAB 0x00100000
173#define DMA_2CLKS 0x00200000
174#define DMA_3CLKS 0x00400000
175#define DMA_EN_ENETAUI DMA_3CLKS
176#define DMA_CNTR_DISAB 0x00800000
177#define DMA_AUTO_NADDR 0x01000000
178#define DMA_SCSI_ON 0x02000000
179#define DMA_PARITY_OFF 0x02000000
180#define DMA_LOADED_ADDR 0x04000000
181#define DMA_LOADED_NADDR 0x08000000
182
183
184#define DMA_BURST1 0x01
185#define DMA_BURST2 0x02
186#define DMA_BURST4 0x04
187#define DMA_BURST8 0x08
188#define DMA_BURST16 0x10
189#define DMA_BURST32 0x20
190#define DMA_BURST64 0x40
191#define DMA_BURSTBITS 0x7f
192
193
194#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
195
196
197#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
198#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
199#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
200#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
201#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
202#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
203#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
204#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
205#define DMA_BEGINDMA_W(regs) \
206 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
207#define DMA_BEGINDMA_R(regs) \
208 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
209
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213
214
215#define DMA_IRQ_ENTRY(dma, dregs) do { \
216 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
217 } while (0)
218
219#define DMA_IRQ_EXIT(dma, dregs) do { \
220 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
221 } while(0)
222
223
224#define DMA_RESET(dma) do { \
225 struct sparc_dma_registers *regs = dma->regs; \
226 \
227 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
228 \
229 regs->cond_reg |= (DMA_RST_SCSI); \
230 __delay(400); \
231 regs->cond_reg &= ~(DMA_RST_SCSI); \
232 sparc_dma_enable_interrupts(regs); \
233 \
234 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
235 dma->running = 0; \
236} while(0)
237
238
239#endif
240
241#endif
242