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12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/memblock.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/of_clk.h>
19#include <linux/of_fdt.h>
20#include <linux/irqchip.h>
21
22#include <asm/bootinfo.h>
23#include <asm/idle.h>
24#include <asm/time.h>
25#include <asm/reboot.h>
26#include <asm/prom.h>
27#include <asm/fw/fw.h>
28
29#include <asm/mach-ath79/ath79.h>
30#include <asm/mach-ath79/ar71xx_regs.h>
31#include "common.h"
32
33#define ATH79_SYS_TYPE_LEN 64
34
35static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
36
37static void ath79_restart(char *command)
38{
39 local_irq_disable();
40 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
41 for (;;)
42 if (cpu_wait)
43 cpu_wait();
44}
45
46static void ath79_halt(void)
47{
48 while (1)
49 cpu_wait();
50}
51
52static void __init ath79_detect_sys_type(void)
53{
54 char *chip = "????";
55 u32 id;
56 u32 major;
57 u32 minor;
58 u32 rev = 0;
59 u32 ver = 1;
60
61 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
62 major = id & REV_ID_MAJOR_MASK;
63
64 switch (major) {
65 case REV_ID_MAJOR_AR71XX:
66 minor = id & AR71XX_REV_ID_MINOR_MASK;
67 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
68 rev &= AR71XX_REV_ID_REVISION_MASK;
69 switch (minor) {
70 case AR71XX_REV_ID_MINOR_AR7130:
71 ath79_soc = ATH79_SOC_AR7130;
72 chip = "7130";
73 break;
74
75 case AR71XX_REV_ID_MINOR_AR7141:
76 ath79_soc = ATH79_SOC_AR7141;
77 chip = "7141";
78 break;
79
80 case AR71XX_REV_ID_MINOR_AR7161:
81 ath79_soc = ATH79_SOC_AR7161;
82 chip = "7161";
83 break;
84 }
85 break;
86
87 case REV_ID_MAJOR_AR7240:
88 ath79_soc = ATH79_SOC_AR7240;
89 chip = "7240";
90 rev = id & AR724X_REV_ID_REVISION_MASK;
91 break;
92
93 case REV_ID_MAJOR_AR7241:
94 ath79_soc = ATH79_SOC_AR7241;
95 chip = "7241";
96 rev = id & AR724X_REV_ID_REVISION_MASK;
97 break;
98
99 case REV_ID_MAJOR_AR7242:
100 ath79_soc = ATH79_SOC_AR7242;
101 chip = "7242";
102 rev = id & AR724X_REV_ID_REVISION_MASK;
103 break;
104
105 case REV_ID_MAJOR_AR913X:
106 minor = id & AR913X_REV_ID_MINOR_MASK;
107 rev = id >> AR913X_REV_ID_REVISION_SHIFT;
108 rev &= AR913X_REV_ID_REVISION_MASK;
109 switch (minor) {
110 case AR913X_REV_ID_MINOR_AR9130:
111 ath79_soc = ATH79_SOC_AR9130;
112 chip = "9130";
113 break;
114
115 case AR913X_REV_ID_MINOR_AR9132:
116 ath79_soc = ATH79_SOC_AR9132;
117 chip = "9132";
118 break;
119 }
120 break;
121
122 case REV_ID_MAJOR_AR9330:
123 ath79_soc = ATH79_SOC_AR9330;
124 chip = "9330";
125 rev = id & AR933X_REV_ID_REVISION_MASK;
126 break;
127
128 case REV_ID_MAJOR_AR9331:
129 ath79_soc = ATH79_SOC_AR9331;
130 chip = "9331";
131 rev = id & AR933X_REV_ID_REVISION_MASK;
132 break;
133
134 case REV_ID_MAJOR_AR9341:
135 ath79_soc = ATH79_SOC_AR9341;
136 chip = "9341";
137 rev = id & AR934X_REV_ID_REVISION_MASK;
138 break;
139
140 case REV_ID_MAJOR_AR9342:
141 ath79_soc = ATH79_SOC_AR9342;
142 chip = "9342";
143 rev = id & AR934X_REV_ID_REVISION_MASK;
144 break;
145
146 case REV_ID_MAJOR_AR9344:
147 ath79_soc = ATH79_SOC_AR9344;
148 chip = "9344";
149 rev = id & AR934X_REV_ID_REVISION_MASK;
150 break;
151
152 case REV_ID_MAJOR_QCA9533_V2:
153 ver = 2;
154 ath79_soc_rev = 2;
155 fallthrough;
156 case REV_ID_MAJOR_QCA9533:
157 ath79_soc = ATH79_SOC_QCA9533;
158 chip = "9533";
159 rev = id & QCA953X_REV_ID_REVISION_MASK;
160 break;
161
162 case REV_ID_MAJOR_QCA9556:
163 ath79_soc = ATH79_SOC_QCA9556;
164 chip = "9556";
165 rev = id & QCA955X_REV_ID_REVISION_MASK;
166 break;
167
168 case REV_ID_MAJOR_QCA9558:
169 ath79_soc = ATH79_SOC_QCA9558;
170 chip = "9558";
171 rev = id & QCA955X_REV_ID_REVISION_MASK;
172 break;
173
174 case REV_ID_MAJOR_QCA956X:
175 ath79_soc = ATH79_SOC_QCA956X;
176 chip = "956X";
177 rev = id & QCA956X_REV_ID_REVISION_MASK;
178 break;
179
180 case REV_ID_MAJOR_TP9343:
181 ath79_soc = ATH79_SOC_TP9343;
182 chip = "9343";
183 rev = id & QCA956X_REV_ID_REVISION_MASK;
184 break;
185
186 default:
187 panic("ath79: unknown SoC, id:0x%08x", id);
188 }
189
190 if (ver == 1)
191 ath79_soc_rev = rev;
192
193 if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
194 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
195 chip, ver, rev);
196 else if (soc_is_tp9343())
197 sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
198 chip, rev);
199 else
200 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
201 pr_info("SoC: %s\n", ath79_sys_type);
202}
203
204const char *get_system_type(void)
205{
206 return ath79_sys_type;
207}
208
209unsigned int get_c0_compare_int(void)
210{
211 return CP0_LEGACY_COMPARE_IRQ;
212}
213
214void __init plat_mem_setup(void)
215{
216 void *dtb;
217
218 set_io_port_base(KSEG1);
219
220
221 dtb = (void *)fw_getenvl("fdt_start");
222 if (dtb == NULL)
223 dtb = get_fdt();
224
225 if (dtb)
226 __dt_setup_arch((void *)KSEG0ADDR(dtb));
227
228 ath79_reset_base = ioremap(AR71XX_RESET_BASE,
229 AR71XX_RESET_SIZE);
230 ath79_pll_base = ioremap(AR71XX_PLL_BASE,
231 AR71XX_PLL_SIZE);
232 ath79_detect_sys_type();
233 ath79_ddr_ctrl_init();
234
235 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
236
237 _machine_restart = ath79_restart;
238 _machine_halt = ath79_halt;
239 pm_power_off = ath79_halt;
240}
241
242void __init plat_time_init(void)
243{
244 struct device_node *np;
245 struct clk *clk;
246 unsigned long cpu_clk_rate;
247
248 of_clk_init(NULL);
249
250 np = of_get_cpu_node(0, NULL);
251 if (!np) {
252 pr_err("Failed to get CPU node\n");
253 return;
254 }
255
256 clk = of_clk_get(np, 0);
257 if (IS_ERR(clk)) {
258 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
259 return;
260 }
261
262 cpu_clk_rate = clk_get_rate(clk);
263
264 pr_info("CPU clock: %lu.%03lu MHz\n",
265 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
266
267 mips_hpt_frequency = cpu_clk_rate / 2;
268
269 clk_put(clk);
270}
271
272void __init arch_init_irq(void)
273{
274 irqchip_init();
275}
276
277void __init device_tree_init(void)
278{
279 unflatten_and_copy_device_tree();
280}
281
