LXR linux/arch/mips/include/asm/dma.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   4 * Written by Hennus Bergman, 1992.
   5 * High DMA channel support & info by Hannu Savolainen
   6 * and John Boyd, Nov. 1992.
   7 *
   8 * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
   9 * and can only be used for expansion cards. Onboard DMA controllers, such
  10 * as the R4030 on Jazz boards behave totally different!
  11 */
  12
  13#ifndef _ASM_DMA_H
  14#define _ASM_DMA_H
  15
  16#include <asm/io.h>                     /* need byte IO */
  17#include <linux/spinlock.h>             /* And spinlocks */
  18#include <linux/delay.h>
  19
  20
  21#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  22#define dma_outb        outb_p
  23#else
  24#define dma_outb        outb
  25#endif
  26
  27#define dma_inb         inb
  28
  29/*
  30 * NOTES about DMA transfers:
  31 *
  32 *  controller 1: channels 0-3, byte operations, ports 00-1F
  33 *  controller 2: channels 4-7, word operations, ports C0-DF
  34 *
  35 *  - ALL registers are 8 bits only, regardless of transfer size
  36 *  - channel 4 is not used - cascades 1 into 2.
  37 *  - channels 0-3 are byte - addresses/counts are for physical bytes
  38 *  - channels 5-7 are word - addresses/counts are for physical words
  39 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  40 *  - transfer count loaded to registers is 1 less than actual count
  41 *  - controller 2 offsets are all even (2x offsets for controller 1)
  42 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  43 *  - page registers for 0-3 use bit 0, represent 64K pages
  44 *
  45 * DMA transfers are limited to the lower 16MB of _physical_ memory.
  46 * Note that addresses loaded into registers must be _physical_ addresses,
  47 * not logical addresses (which may differ if paging is active).
  48 *
  49 *  Address mapping for channels 0-3:
  50 *
  51 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  52 *    |  ...  |   |  ... |   |  ... |
  53 *    |  ...  |   |  ... |   |  ... |
  54 *    |  ...  |   |  ... |   |  ... |
  55 *   P7  ...  P0  A7 ... A0  A7 ... A0
  56 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  57 *
  58 *  Address mapping for channels 5-7:
  59 *
  60 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  61 *    |  ...  |   \   \   ... \  \  \  ... \  \
  62 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  63 *    |  ...  |     \   \   ... \  \  \  ... \
  64 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  65 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  66 *
  67 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  68 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  69 * the hardware level, so odd-byte transfers aren't possible).
  70 *
  71 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  72 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  73 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  74 *
  75 */
  76
  77#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
  78#define MAX_DMA_CHANNELS        8
  79#endif
  80
  81/*
  82 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
  83 * platform.  This describes only the PC style part of the DMA logic like on
  84 * Deskstations or Acer PICA but not the much more versatile DMA logic used
  85 * for the local devices on Acer PICA or Magnums.
  86 */
  87#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
  88/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
  89#define MAX_DMA_ADDRESS         PAGE_OFFSET
  90#else
  91#define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
  92#endif
  93#define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
  94
  95#ifndef MAX_DMA32_PFN
  96#define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
  97#endif
  98
  99/* 8237 DMA controllers */
 100#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
 101#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
 102
 103/* DMA controller registers */
 104#define DMA1_CMD_REG            0x08    /* command register (w) */
 105#define DMA1_STAT_REG           0x08    /* status register (r) */
 106#define DMA1_REQ_REG            0x09    /* request register (w) */
 107#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
 108#define DMA1_MODE_REG           0x0B    /* mode register (w) */
 109#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
 110#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 111#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 112#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 113#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 114
 115#define DMA2_CMD_REG            0xD0    /* command register (w) */
 116#define DMA2_STAT_REG           0xD0    /* status register (r) */
 117#define DMA2_REQ_REG            0xD2    /* request register (w) */
 118#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 119#define DMA2_MODE_REG           0xD6    /* mode register (w) */
 120#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 121#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 122#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 123#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 124#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 125
 126#define DMA_ADDR_0              0x00    /* DMA address registers */
 127#define DMA_ADDR_1              0x02
 128#define DMA_ADDR_2              0x04
 129#define DMA_ADDR_3              0x06
 130#define DMA_ADDR_4              0xC0
 131#define DMA_ADDR_5              0xC4
 132#define DMA_ADDR_6              0xC8
 133#define DMA_ADDR_7              0xCC
 134
 135#define DMA_CNT_0               0x01    /* DMA count registers */
 136#define DMA_CNT_1               0x03
 137#define DMA_CNT_2               0x05
 138#define DMA_CNT_3               0x07
 139#define DMA_CNT_4               0xC2
 140#define DMA_CNT_5               0xC6
 141#define DMA_CNT_6               0xCA
 142#define DMA_CNT_7               0xCE
 143
 144#define DMA_PAGE_0              0x87    /* DMA page registers */
 145#define DMA_PAGE_1              0x83
 146#define DMA_PAGE_2              0x81
 147#define DMA_PAGE_3              0x82
 148#define DMA_PAGE_5              0x8B
 149#define DMA_PAGE_6              0x89
 150#define DMA_PAGE_7              0x8A
 151
 152#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 153#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 154#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 155
 156#define DMA_AUTOINIT    0x10
 157
 158extern spinlock_t  dma_spin_lock;
 159
 160static __inline__ unsigned long claim_dma_lock(void)
 161{
 162        unsigned long flags;
 163        spin_lock_irqsave(&dma_spin_lock, flags);
 164        return flags;
 165}
 166
 167static __inline__ void release_dma_lock(unsigned long flags)
 168{
 169        spin_unlock_irqrestore(&dma_spin_lock, flags);
 170}
 171
 172/* enable/disable a specific DMA channel */
 173static __inline__ void enable_dma(unsigned int dmanr)
 174{
 175        if (dmanr<=3)
 176                dma_outb(dmanr,  DMA1_MASK_REG);
 177        else
 178                dma_outb(dmanr & 3,  DMA2_MASK_REG);
 179}
 180
 181static __inline__ void disable_dma(unsigned int dmanr)
 182{
 183        if (dmanr<=3)
 184                dma_outb(dmanr | 4,  DMA1_MASK_REG);
 185        else
 186                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 187}
 188
 189/* Clear the 'DMA Pointer Flip Flop'.
 190 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 191 * Use this once to initialize the FF to a known state.
 192 * After that, keep track of it. :-)
 193 * --- In order to do that, the DMA routines below should ---
 194 * --- only be used while holding the DMA lock ! ---
 195 */
 196static __inline__ void clear_dma_ff(unsigned int dmanr)
 197{
 198        if (dmanr<=3)
 199                dma_outb(0,  DMA1_CLEAR_FF_REG);
 200        else
 201                dma_outb(0,  DMA2_CLEAR_FF_REG);
 202}
 203
 204/* set mode (above) for a specific DMA channel */
 205static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 206{
 207        if (dmanr<=3)
 208                dma_outb(mode | dmanr,  DMA1_MODE_REG);
 209        else
 210                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 211}
 212
 213/* Set only the page register bits of the transfer address.
 214 * This is used for successive transfers when we know the contents of
 215 * the lower 16 bits of the DMA current address register, but a 64k boundary
 216 * may have been crossed.
 217 */
 218static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
 219{
 220        switch(dmanr) {
 221                case 0:
 222                        dma_outb(pagenr, DMA_PAGE_0);
 223                        break;
 224                case 1:
 225                        dma_outb(pagenr, DMA_PAGE_1);
 226                        break;
 227                case 2:
 228                        dma_outb(pagenr, DMA_PAGE_2);
 229                        break;
 230                case 3:
 231                        dma_outb(pagenr, DMA_PAGE_3);
 232                        break;
 233                case 5:
 234                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 235                        break;
 236                case 6:
 237                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 238                        break;
 239                case 7:
 240                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 241                        break;
 242        }
 243}
 244
 245
 246/* Set transfer address & page bits for specific DMA channel.
 247 * Assumes dma flipflop is clear.
 248 */
 249static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
 250{
 251        set_dma_page(dmanr, a>>16);
 252        if (dmanr <= 3)  {
 253            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 254            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 255        }  else  {
 256            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 257            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 258        }
 259}
 260
 261
 262/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
 263 * a specific DMA channel.
 264 * You must ensure the parameters are valid.
 265 * NOTE: from a manual: "the number of transfers is one more
 266 * than the initial word count"! This is taken into account.
 267 * Assumes dma flip-flop is clear.
 268 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 269 */
 270static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 271{
 272        count--;
 273        if (dmanr <= 3)  {
 274            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 275            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 276        } else {
 277            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 278            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 279        }
 280}
 281
 282
 283/* Get DMA residue count. After a DMA transfer, this
 284 * should return zero. Reading this while a DMA transfer is
 285 * still in progress will return unpredictable results.
 286 * If called before the channel has been used, it may return 1.
 287 * Otherwise, it returns the number of _bytes_ left to transfer.
 288 *
 289 * Assumes DMA flip-flop is clear.
 290 */
 291static __inline__ int get_dma_residue(unsigned int dmanr)
 292{
 293        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 294                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 295
 296        /* using short to get 16-bit wrap around */
 297        unsigned short count;
 298
 299        count = 1 + dma_inb(io_port);
 300        count += dma_inb(io_port) << 8;
 301
 302        return (dmanr<=3)? count : (count<<1);
 303}
 304
 305
 306/* These are in kernel/dma.c: */
 307extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 308extern void free_dma(unsigned int dmanr);       /* release it again */
 309
 310/* From PCI */
 311
 312#ifdef CONFIG_PCI
 313extern int isa_dma_bridge_buggy;
 314#else
 315#define isa_dma_bridge_buggy    (0)
 316#endif
 317
 318#endif /* _ASM_DMA_H */
 319