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7#ifndef __ASM_RC32434_RB_H
8#define __ASM_RC32434_RB_H
9
10#define REGBASE 0x18000000
11#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
12#define UART0BASE 0x58000
13#define RST (1 << 15)
14#define DEV0BASE 0x010000
15#define DEV0MASK 0x010004
16#define DEV0C 0x010008
17#define DEV0T 0x01000C
18#define DEV1BASE 0x010010
19#define DEV1MASK 0x010014
20#define DEV1C 0x010018
21#define DEV1TC 0x01001C
22#define DEV2BASE 0x010020
23#define DEV2MASK 0x010024
24#define DEV2C 0x010028
25#define DEV2TC 0x01002C
26#define DEV3BASE 0x010030
27#define DEV3MASK 0x010034
28#define DEV3C 0x010038
29#define DEV3TC 0x01003C
30#define BTCS 0x010040
31#define BTCOMPARE 0x010044
32#define GPIOBASE 0x050000
33
34#define GPIOFUNC 0x00
35#define GPIOCFG 0x04
36#define GPIOD 0x08
37#define GPIOILEVEL 0x0C
38#define GPIOISTAT 0x10
39#define GPIONMIEN 0x14
40#define IMASK6 0x38
41#define LO_WPX (1 << 0)
42#define LO_ALE (1 << 1)
43#define LO_CLE (1 << 2)
44#define LO_CEX (1 << 3)
45#define LO_FOFF (1 << 5)
46#define LO_SPICS (1 << 6)
47#define LO_ULED (1 << 7)
48
49#define BIT_TO_MASK(x) (1 << x)
50
51struct dev_reg {
52 u32 base;
53 u32 mask;
54 u32 ctl;
55 u32 timing;
56};
57
58struct korina_device {
59 char *name;
60 unsigned char mac[6];
61 struct net_device *dev;
62};
63
64struct mpmc_device {
65 unsigned char state;
66 spinlock_t lock;
67 void __iomem *base;
68};
69
70extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
71extern unsigned char get_latch_u5(void);
72
73#endif
74