LXR linux/arch/mips/include/asm/processor.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994 Waldorf GMBH
   7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8 * Copyright (C) 1996 Paul M. Antoine
   9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10 */
  11#ifndef _ASM_PROCESSOR_H
  12#define _ASM_PROCESSOR_H
  13
  14#include <linux/atomic.h>
  15#include <linux/cpumask.h>
  16#include <linux/sizes.h>
  17#include <linux/threads.h>
  18
  19#include <asm/cachectl.h>
  20#include <asm/cpu.h>
  21#include <asm/cpu-info.h>
  22#include <asm/dsemul.h>
  23#include <asm/mipsregs.h>
  24#include <asm/prefetch.h>
  25#include <asm/vdso/processor.h>
  26
  27/*
  28 * System setup and hardware flags..
  29 */
  30
  31extern unsigned int vced_count, vcei_count;
  32extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
  33
  34#ifdef CONFIG_32BIT
  35/*
  36 * User space process size: 2GB. This is hardcoded into a few places,
  37 * so don't change it unless you know what you are doing.
  38 */
  39#define TASK_SIZE       0x80000000UL
  40
  41#define STACK_TOP_MAX   TASK_SIZE
  42
  43#define TASK_IS_32BIT_ADDR 1
  44
  45#endif
  46
  47#ifdef CONFIG_64BIT
  48/*
  49 * User space process size: 1TB. This is hardcoded into a few places,
  50 * so don't change it unless you know what you are doing.  TASK_SIZE
  51 * is limited to 1TB by the R4000 architecture; R10000 and better can
  52 * support 16TB; the architectural reserve for future expansion is
  53 * 8192EB ...
  54 */
  55#define TASK_SIZE32     0x7fff8000UL
  56#ifdef CONFIG_MIPS_VA_BITS_48
  57#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
  58#else
  59#define TASK_SIZE64     0x10000000000UL
  60#endif
  61#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  62#define STACK_TOP_MAX   TASK_SIZE64
  63
  64#define TASK_SIZE_OF(tsk)                                               \
  65        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  66
  67#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
  68
  69#endif
  70
  71#define VDSO_RANDOMIZE_SIZE     (TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)
  72
  73extern unsigned long mips_stack_top(void);
  74#define STACK_TOP               mips_stack_top()
  75
  76/*
  77 * This decides where the kernel will search for a free chunk of vm
  78 * space during mmap's.
  79 */
  80#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  81
  82
  83#define NUM_FPU_REGS    32
  84
  85#ifdef CONFIG_CPU_HAS_MSA
  86# define FPU_REG_WIDTH  128
  87#else
  88# define FPU_REG_WIDTH  64
  89#endif
  90
  91union fpureg {
  92        __u32   val32[FPU_REG_WIDTH / 32];
  93        __u64   val64[FPU_REG_WIDTH / 64];
  94};
  95
  96#ifdef CONFIG_CPU_LITTLE_ENDIAN
  97# define FPR_IDX(width, idx)    (idx)
  98#else
  99# define FPR_IDX(width, idx)    ((idx) ^ ((64 / (width)) - 1))
 100#endif
 101
 102#define BUILD_FPR_ACCESS(width) \
 103static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)  \
 104{                                                                       \
 105        return fpr->val##width[FPR_IDX(width, idx)];                    \
 106}                                                                       \
 107                                                                        \
 108static inline void set_fpr##width(union fpureg *fpr, unsigned idx,      \
 109                                  u##width val)                         \
 110{                                                                       \
 111        fpr->val##width[FPR_IDX(width, idx)] = val;                     \
 112}
 113
 114BUILD_FPR_ACCESS(32)
 115BUILD_FPR_ACCESS(64)
 116
 117/*
 118 * It would be nice to add some more fields for emulator statistics,
 119 * the additional information is private to the FPU emulator for now.
 120 * See arch/mips/include/asm/fpu_emulator.h.
 121 */
 122
 123struct mips_fpu_struct {
 124        union fpureg    fpr[NUM_FPU_REGS];
 125        unsigned int    fcr31;
 126        unsigned int    msacsr;
 127};
 128
 129#define NUM_DSP_REGS   6
 130
 131typedef unsigned long dspreg_t;
 132
 133struct mips_dsp_state {
 134        dspreg_t        dspr[NUM_DSP_REGS];
 135        unsigned int    dspcontrol;
 136};
 137
 138#define INIT_CPUMASK { \
 139        {0,} \
 140}
 141
 142struct mips3264_watch_reg_state {
 143        /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 144           64 bit kernel.  We use unsigned long as it has the same
 145           property. */
 146        unsigned long watchlo[NUM_WATCH_REGS];
 147        /* Only the mask and IRW bits from watchhi. */
 148        u16 watchhi[NUM_WATCH_REGS];
 149};
 150
 151union mips_watch_reg_state {
 152        struct mips3264_watch_reg_state mips3264;
 153};
 154
 155#if defined(CONFIG_CPU_CAVIUM_OCTEON)
 156
 157struct octeon_cop2_state {
 158        /* DMFC2 rt, 0x0201 */
 159        unsigned long   cop2_crc_iv;
 160        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 161        unsigned long   cop2_crc_length;
 162        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 163        unsigned long   cop2_crc_poly;
 164        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 165        unsigned long   cop2_llm_dat[2];
 166       /* DMFC2 rt, 0x0084 */
 167        unsigned long   cop2_3des_iv;
 168        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 169        unsigned long   cop2_3des_key[3];
 170        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 171        unsigned long   cop2_3des_result;
 172        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 173        unsigned long   cop2_aes_inp0;
 174        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 175        unsigned long   cop2_aes_iv[2];
 176        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 177         * rt, 0x0107 */
 178        unsigned long   cop2_aes_key[4];
 179        /* DMFC2 rt, 0x0110 */
 180        unsigned long   cop2_aes_keylen;
 181        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 182        unsigned long   cop2_aes_result[2];
 183        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 184         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 185         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 186         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 187         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 188        unsigned long   cop2_hsh_datw[15];
 189        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 190         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 191         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 192        unsigned long   cop2_hsh_ivw[8];
 193        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 194        unsigned long   cop2_gfm_mult[2];
 195        /* DMFC2 rt, 0x025E - Pass2 */
 196        unsigned long   cop2_gfm_poly;
 197        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 198        unsigned long   cop2_gfm_result[2];
 199        /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
 200        unsigned long   cop2_sha3[2];
 201};
 202#define COP2_INIT                                               \
 203        .cp2                    = {0,},
 204
 205struct octeon_cvmseg_state {
 206        unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 207                            [cpu_dcache_line_size() / sizeof(unsigned long)];
 208};
 209
 210#elif defined(CONFIG_CPU_XLP)
 211struct nlm_cop2_state {
 212        u64     rx[4];
 213        u64     tx[4];
 214        u32     tx_msg_status;
 215        u32     rx_msg_status;
 216};
 217
 218#define COP2_INIT                                               \
 219        .cp2                    = {{0}, {0}, 0, 0},
 220#else
 221#define COP2_INIT
 222#endif
 223
 224#ifdef CONFIG_CPU_HAS_MSA
 225# define ARCH_MIN_TASKALIGN     16
 226# define FPU_ALIGN              __aligned(16)
 227#else
 228# define ARCH_MIN_TASKALIGN     8
 229# define FPU_ALIGN
 230#endif
 231
 232struct mips_abi;
 233
 234/*
 235 * If you change thread_struct remember to change the #defines below too!
 236 */
 237struct thread_struct {
 238        /* Saved main processor registers. */
 239        unsigned long reg16;
 240        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 241        unsigned long reg29, reg30, reg31;
 242
 243        /* Saved cp0 stuff. */
 244        unsigned long cp0_status;
 245
 246#ifdef CONFIG_MIPS_FP_SUPPORT
 247        /* Saved fpu/fpu emulator stuff. */
 248        struct mips_fpu_struct fpu FPU_ALIGN;
 249        /* Assigned branch delay slot 'emulation' frame */
 250        atomic_t bd_emu_frame;
 251        /* PC of the branch from a branch delay slot 'emulation' */
 252        unsigned long bd_emu_branch_pc;
 253        /* PC to continue from following a branch delay slot 'emulation' */
 254        unsigned long bd_emu_cont_pc;
 255#endif
 256#ifdef CONFIG_MIPS_MT_FPAFF
 257        /* Emulated instruction count */
 258        unsigned long emulated_fp;
 259        /* Saved per-thread scheduler affinity mask */
 260        cpumask_t user_cpus_allowed;
 261#endif /* CONFIG_MIPS_MT_FPAFF */
 262
 263        /* Saved state of the DSP ASE, if available. */
 264        struct mips_dsp_state dsp;
 265
 266        /* Saved watch register state, if available. */
 267        union mips_watch_reg_state watch;
 268
 269        /* Other stuff associated with the thread. */
 270        unsigned long cp0_badvaddr;     /* Last user fault */
 271        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 272        unsigned long error_code;
 273        unsigned long trap_nr;
 274#ifdef CONFIG_CPU_CAVIUM_OCTEON
 275        struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 276        struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 277#endif
 278#ifdef CONFIG_CPU_XLP
 279        struct nlm_cop2_state cp2;
 280#endif
 281        struct mips_abi *abi;
 282};
 283
 284#ifdef CONFIG_MIPS_MT_FPAFF
 285#define FPAFF_INIT                                              \
 286        .emulated_fp                    = 0,                    \
 287        .user_cpus_allowed              = INIT_CPUMASK,
 288#else
 289#define FPAFF_INIT
 290#endif /* CONFIG_MIPS_MT_FPAFF */
 291
 292#ifdef CONFIG_MIPS_FP_SUPPORT
 293# define FPU_INIT                                               \
 294        .fpu                    = {                             \
 295                .fpr            = {{{0,},},},                   \
 296                .fcr31          = 0,                            \
 297                .msacsr         = 0,                            \
 298        },                                                      \
 299        /* Delay slot emulation */                              \
 300        .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE),          \
 301        .bd_emu_branch_pc = 0,                                  \
 302        .bd_emu_cont_pc = 0,
 303#else
 304# define FPU_INIT
 305#endif
 306
 307#define INIT_THREAD  {                                          \
 308        /*                                                      \
 309         * Saved main processor registers                       \
 310         */                                                     \
 311        .reg16                  = 0,                            \
 312        .reg17                  = 0,                            \
 313        .reg18                  = 0,                            \
 314        .reg19                  = 0,                            \
 315        .reg20                  = 0,                            \
 316        .reg21                  = 0,                            \
 317        .reg22                  = 0,                            \
 318        .reg23                  = 0,                            \
 319        .reg29                  = 0,                            \
 320        .reg30                  = 0,                            \
 321        .reg31                  = 0,                            \
 322        /*                                                      \
 323         * Saved cp0 stuff                                      \
 324         */                                                     \
 325        .cp0_status             = 0,                            \
 326        /*                                                      \
 327         * Saved FPU/FPU emulator stuff                         \
 328         */                                                     \
 329        FPU_INIT                                                \
 330        /*                                                      \
 331         * FPU affinity state (null if not FPAFF)               \
 332         */                                                     \
 333        FPAFF_INIT                                              \
 334        /*                                                      \
 335         * Saved DSP stuff                                      \
 336         */                                                     \
 337        .dsp                    = {                             \
 338                .dspr           = {0, },                        \
 339                .dspcontrol     = 0,                            \
 340        },                                                      \
 341        /*                                                      \
 342         * saved watch register stuff                           \
 343         */                                                     \
 344        .watch = {{{0,},},},                                    \
 345        /*                                                      \
 346         * Other stuff associated with the process              \
 347         */                                                     \
 348        .cp0_badvaddr           = 0,                            \
 349        .cp0_baduaddr           = 0,                            \
 350        .error_code             = 0,                            \
 351        .trap_nr                = 0,                            \
 352        /*                                                      \
 353         * Platform specific cop2 registers(null if no COP2)    \
 354         */                                                     \
 355        COP2_INIT                                               \
 356}
 357
 358struct task_struct;
 359
 360/* Free all resources held by a thread. */
 361#define release_thread(thread) do { } while(0)
 362
 363/*
 364 * Do necessary setup to start up a newly executed thread.
 365 */
 366extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 367
 368static inline void flush_thread(void)
 369{
 370}
 371
 372unsigned long get_wchan(struct task_struct *p);
 373
 374#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 375                         THREAD_SIZE - 32 - sizeof(struct pt_regs))
 376#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 377#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 378#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 379#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 380
 381/*
 382 * Return_address is a replacement for __builtin_return_address(count)
 383 * which on certain architectures cannot reasonably be implemented in GCC
 384 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 385 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 386 * aborts compilation on some CPUs.  It's simply not possible to unwind
 387 * some CPU's stackframes.
 388 *
 389 * __builtin_return_address works only for non-leaf functions.  We avoid the
 390 * overhead of a function call by forcing the compiler to save the return
 391 * address register on the stack.
 392 */
 393#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 394
 395#ifdef CONFIG_CPU_HAS_PREFETCH
 396
 397#define ARCH_HAS_PREFETCH
 398#define prefetch(x) __builtin_prefetch((x), 0, 1)
 399
 400#define ARCH_HAS_PREFETCHW
 401#define prefetchw(x) __builtin_prefetch((x), 1, 1)
 402
 403#endif
 404
 405/*
 406 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
 407 * to the prctl syscall.
 408 */
 409extern int mips_get_process_fp_mode(struct task_struct *task);
 410extern int mips_set_process_fp_mode(struct task_struct *task,
 411                                    unsigned int value);
 412
 413#define GET_FP_MODE(task)               mips_get_process_fp_mode(task)
 414#define SET_FP_MODE(task,value)         mips_set_process_fp_mode(task, value)
 415
 416#endif /* _ASM_PROCESSOR_H */
 417